CN1400657A - 压铸的功率器件及其制造方法 - Google Patents

压铸的功率器件及其制造方法 Download PDF

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Publication number
CN1400657A
CN1400657A CN02127066A CN02127066A CN1400657A CN 1400657 A CN1400657 A CN 1400657A CN 02127066 A CN02127066 A CN 02127066A CN 02127066 A CN02127066 A CN 02127066A CN 1400657 A CN1400657 A CN 1400657A
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semiconductor chip
metallic plate
chip
semiconductor
semiconductor device
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CN1267990C (zh
Inventor
平野尚彦
手嶋孝纪
中濑好美
八木贤次
大仓康嗣
真光邦明
野村和仁
福田丰
铃木干昌
则武千景
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Denso Corp
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Denso Corp
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Priority claimed from JP2002086408A external-priority patent/JP3580293B2/ja
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Abstract

一种半导体器件，包括在工作中产生热的半导体芯片，用于冷却该芯片的一对散热器和其中埋置该芯片和该散热器的铸模树脂。芯片的厚度t1和用焊料连接到芯片的散热器之一的厚度t2满足式t2/t1≥5。此外，散热器的热膨胀系数α1和铸模树脂的热膨胀系数α2满足式0.5≤α2/α1≤1.5。另外，面对焊料的芯片表面具有满足式Ra≤500nm的粗糙度Ra。此外，焊料是锡－基焊料以抑制芯片中压应力松弛，压应力松弛是由焊料的蠕变引起的。

Description

压铸的功率器件及其制造方法
技术领域
本发明涉及一种压铸的功率器件，该器件包括一个在工作中产生热量的半导体芯片和一个用于冷却该半导体芯片的散热器。
背景技术
提出一种功率器件，它包含一个半导体芯片和仅一个散热器，该散热器为用于散热的铜板，并且也用作电极。在功率器件中，提供电源线和接地线作为接合线。但是当为减少制造成本而缩小芯片尺寸时，这种类型的功率器件有下列问题。为小型化，有必要减少接合线数量，这样提供预定的额定电流变为不可能。此外，虽然随着器件小型化半导体芯片以更高速度工作，但小型化导致较大的电感和增加的浪涌。另外，半导体芯片在吸收预定的额定电流时，它在单位体积产生更多热量。因此，除非热量被更有效的释放，否则半导体芯片较低的温度在工作时变高。
为了解决上述问题，建议一种包含两个散热器的半导体器件。由于热量分别从半导体芯片的两侧释放到两个散热器，后面建议的半导体器件与前面建议的只有一个散热器的功率器件相比提供改善的散热效率。虽然后面建议的半导体器件用铸模树脂铸型，但为改善散热效率，两个散热器的与分别面对半导体芯片的表面相对的表面被暴露在外。
然而，在后面建议的半导体器件中，半导体芯片和散热器彼此间热膨胀系数相对而言差别很大。因此，后面建议的半导体器件工作时在热循环情况下，在半导体芯片中产生相对大的应力，而且最坏情况下，半导体芯片被损坏。特别地，当制造后面建议地半导体器件时，散热器在回流工艺中被焊接到半导体芯片上，其中焊料在加热步骤中被加热到预定温度以使焊料熔化，并且在随后的冷却步骤中冷却硬化焊料。具体地，后面建议的半导体器件中的半导体芯片和散热器基本上分别由单晶硅和铜制成。因此，由于单晶硅和铜之间热膨胀系数的差别，如图29所示分别为3.0ppm和17ppm，半导体芯片和散热器在回流工艺的冷却步骤后立即分别受压应力和拉应力，如图30所示。
当后面建议的半导体器件在冷却步骤之后被置于室温时，由于连接半导体芯片和散热器的焊料的蠕变，应力逐渐松弛。如果应力充分松弛，当半导体器件由工作中半导体芯片所产生的热或来自周围环境的热被再次加热时，由于单晶硅和铜之间热膨胀系数的差别在半导体芯片中产生拉应力。构成半导体芯片的单晶硅即使在超过600MPa的压应力下保持完好，而单晶硅在100MPa的拉应力下就可被破坏。因此，在后面的半导体器件中，使半导体芯片破坏的是拉应力。
半导体芯片包含p-型基区和n+-型源区，它们位于n-型硅衬底的前表面，和位于n-型硅衬底的后表面上的漏电极。前表面和后表面反向相向。在建议的半导体芯片制造方法中，n-型硅的半导体晶片，许多半导体芯片由其制成，被减薄以减小半导体芯片的厚度，因为通过缩短电流路径半导体芯片的接通电阻被降低。
特别地，在一种建议的方法中，在晶片的前表面上形成基区和源区，一个金属化层，以及一个钝化膜(SiN膜或PIQ膜)，并随后减薄晶片。其次，在晶片的后表面上形成后侧电极层。晶片的前表面和后表面反向相向。在建议的方法中，在形成后侧电极前晶片被整体减薄，因此在以后的制造步骤中，晶片易翘曲并变得易碎。
在建议的半导体芯片制造方法中，在晶片的后表面中形成n+区，作为用于晶片和后侧电极层间电接触的杂质扩散区。然后，与n+区接触形成后侧电极层。
为形成n+区，或者采用离子注入法或者采用热扩散法。为接近100％激活注入的离子，离子注入法要求在500～700℃的退火。此外，为获得相对高的杂质浓度，需要相对高的掺杂量。另一方面，热扩散法比离子注入法需要更高温度和更长周期。然而，两种方法中，由于n+区是在晶片前表面上形成金属化层之后被形成，因此退火必须在低于金属化层软化的温度下进行。例如，当使用铝膜时，退火温度需低于450℃。因而，在建议的方法中，退火效果不充分。
发明内容
考虑到上述方面提出，本发明目的在于提供一种包含半导体芯片的半导体器件，该芯片即使在大的热应力下保持完好，同时防止铸模树脂(mold resin)分层并防止焊料破裂，因此保证了半导体器件的长期可靠性。本发明的另一目的在于提供一种用于制造该半导体芯片的方法。利用该方法，半导体器件制造工艺中半导体晶片的易碎性得到改善，而且同时，在相对低的温度下实现晶片和后表面电极之间的电接触。
为达到前面的目的，半导体芯片具有的厚度为t1，而且散热器之一具有的厚度为t2，使得厚度t1和厚度t2满足下式。
t2/t1≥5
通过如此设定厚度，否则不充足的压应力增加，该压应力在回流工艺中的冷却步骤之后立刻在半导体芯片中产生。因此，否则不充足的拉应力减少，该拉应力在半导体器件的工作环境中的热循环期间产生于半导体芯片内。此外，每个散热器具有热膨胀系数α1，而铸模树脂具有热膨胀系数α2，使得热膨胀系数α1和α2满足下式。
0.5≤α2/α1≤1.5
另外，半导体芯片在连接散热器的表面具有表面粗糙度Ra，满足下式。
Ra≤500nm
再者，焊料是锡-基焊料，以抑制半导体芯片中压应力的松弛。
为了达到后面的目的，在晶片的前表面中形成杂质扩散区，然后晶片的后表面被抛光至第一预定厚度。前后表面反向相向。然后，从后表面腐蚀晶片至第二预定厚度，晶片周边除外。然后，在后表面上形成掺杂多晶硅膜，并且形成杂质扩散区，以通过在相对低的温度下将杂质从多晶硅膜扩散到后表面中来获得晶片和后表面电极间的电接触。
附图说明
本发明的上述以及其它目的，特征和优势将在下列参考附图的详述中变得更清楚。图中：
图1是按照本发明第一到第五实施例的半导体器件的一个图解横断面视图；
图2A到2E是示出按照第一到第五实施例的半导体器件的制造步骤的视图；
图3是示出标准化压应力和厚度比间相关关系的曲线图；
图4是示出剪切应力比和厚度比间相关关系的曲线图；
图5是示出半导体芯片中沿Z轴的应力和树脂热膨胀系数间相关关系的曲线图；
图6是示出半导体芯片的剪切应力和树脂热膨胀系数间相关关系的曲线图；
图7是示出焊料中沿Z轴的应力和树脂热膨胀系数间相关关系以及剪切应力绝对值和树脂热膨胀系数间相关关系的曲线图；
图8是示出半导体芯片的破裂百分比和半导体芯片表面粗糙度间相关关系的曲线图；
图9是图1所示半导体器件的局部横断面图；
图10是示出半导体芯片标准化剪切应力和芯片厚度相关关系的曲线图；
图11是示出典型焊料的相对断裂强度和相对屈服应力的表；
图12是示出典型焊料相对应变速率的表；
图13是示出半导体芯片中横向残余应力和延迟时间间的相关关系的曲线图；
图14是按照本发明的第六实施例的半导体器件的图解横断面视图；
图15是按照第六实施例的半导体器件中半导体芯片的横断面视图；
图16A到16D是示出按照第六实施例的半导体器件的制造步骤的横断面视图；
图17是按照第六实施例的腐蚀罐的横断面视图；
图18是示出按照第六实施例的罐腐蚀系统的整体结构的横断面视图；
图19是示出按照第六实施例的半导体器件的制造步骤的横断面视图；
图20是示出和图19相同制造步骤的平面图，其中铜板被焊接到晶片上；
图21是示出按照第六实施例的半导体器件的制造步骤的平面视图；
图22是沿图21中XXII-XXII线截取的横断面视图；
图23是示出按照第六实施例的桥连芯片(bridging chip)结构中变化的平面图；
图24是沿图23中XXIV-XXIV线截取的横断面视图；
图25是包含图23和24所示的桥连芯片的半导体器件的图解横断面视图；
图26是示出包含另一桥连芯片的半导体器件的制造工艺的横断面视图；
图27是示出和图26相同的制造步骤的平面图，其中两个铜板被焊接到一个晶片上；
图28是包含如图26和27所示的两个桥连芯片的半导体器件的图解横断面视图；
图29是示出材料热膨胀系数的表；
图30是示出温度变化和半导体芯片内应力的图解时间图；
图31A和31B是示出半导体芯片内应力分布的曲线图；
图32是示出剪切塑性应变和半导体芯片厚度间相关关系的曲线图；
图33是示出沿Z轴应力和树脂热膨胀系数之间的相关关系的曲线图；以及
图34是示出散热器厚度，半导体芯片厚度，以及耐久性评估结果间相关关系的曲线图。
具体实施方式
参考不同实施例详述本发明。
第一实施例
如图1所示，按照第一实施例的半导体器件1具有类似于图29所示建议半导体器件1A的构造。半导体器件1包含半导体芯片2，下部散热器3(第一金属板)，上部散热器4(第二金属板)，以及桥连芯片5(第三金属板)。如图1所示，半导体芯片2的下表面(第一表面)和下部散热器3的上表面通过焊料6连接起来(接合层)。此外，半导体芯片2的上表面(第二表面)和桥连芯片5的下表面也通过另一的焊料6连接起来。桥连芯片5的上表面和上部散热器4的下表面也通过其它焊料6连接起来。图1中的半导体芯片2通过散热器3，4将来自半导体芯片2两侧的热量释放出去。
图1中的半导体芯片2是一个垂直功率MOS晶体极管。但半导体芯片2可以是其它功率器件如IGBT和半导体闸流管。图1中半导体芯片2的形状基本上是一个长方形薄板，如图2A所示。下部散热器3，上部散热器4，和桥连芯片5由具有相对高的导热性和相对高的导电性的金属如铜和铝构成。下部散热器3和上部散热器4通过焊料6和桥连芯片5被电连接于主电极如半导体芯片2的收集极电极和发射极电极。
如图2A所示，下部散热器3基本上是长方形板并且具有向后突出的引线3a。桥连芯片5，也在图2A中示出，基本上是一个长方形板且比半导体芯片2略小。上部散热器4，如图2D所示，基本上是一个长方形板并且具有向后突出的引线4a。下部散热器3的引线3a的位置和上部散热器4的引线4a的位置彼此偏移，以避免引线3a和4a彼此面对。在图1的半导体器件1中，其中尺寸比例被放大，下部散热器3的上表面和下部散热器4的下表面间的距离为1mm～2mm。
如图1所示，半导体芯片2，桥连芯片5，以及散热器3，4通过压铸被埋置于环氧树脂7中。对于压铸，使用由顶模和底模两部分组成的模，图中未示出顶模和底模。为增强树脂7和散热器3，4间的粘接，树脂7和半导体芯片2之间的粘接以及树脂7和桥连芯片5之间的粘接，优选涂层树脂，图中未示出，如聚酰胺树脂，位于树脂7和散热器3，4中的每个，桥连芯片5以及芯片2之间。
图1中的半导体器件1按下列方法制造。首先，如图2A所示，焊料箔8和芯片2按照这种顺序叠放在下部散热器3的上表面，而另一焊料箔8和桥连芯片5按照这种顺序叠放在芯片2的上面。然后，焊料箔8在作为加热系统的回流系统中熔化，并硬化，将半导体芯片2和桥连芯片5分别焊接到下部散热器3的上表面和半导体芯片2的上表面。
然后，如图2C所示，控制电极如芯片2上的栅垫(gate pad)通过由铝或金制成的接合线10被接合到引线框架9a和9b。接合线10电连接芯片2上的控制电极和引线框架9a，9b。然后，如图2D所示，焊料箔8和上部散热器4按这种顺序叠放在桥连芯片5的上面。焊料箔8在作为加热系统的回流系统中熔化，并硬化，在桥连芯片5的上面焊接上部散热器4。如图2E所示，在上部散热器4的表面放置重物11以便在焊接过程中将上部散热器4向下压。同时，为了保持上部散热器4和下部散热器3间的预定距离，在上部散热器4和下部散热器3之间放置衬垫夹具，图中未示出。
在上部散热器4和桥连芯片5之间的焊料箔8熔化前，上部散热器4和下部散热器3之间的距离设定为大于由衬垫夹具设定的预定距离。当焊料箔8熔化时，来自重物11的压力使熔化的焊料变薄并且使上部散热器4和下部散热器3之间的距离等同于由衬垫夹具设定的距离。焊料6，由焊料箔8形成，被设计成获得一个大致厚度。一旦熔化的焊料层变硬，芯片2，散热器3，4，以及桥连芯片5被焊接并被焊料6电连接。随后，聚酰胺树脂被涂在散热器3，4，桥连芯片5，以及芯片2的表面上。涂层可通过，例如插入包含聚酰胺树脂的溶液中或通过滴漏或通过分散喷嘴喷涂包含聚酰胺树脂的溶液。聚酰胺树脂应根据需要涂覆，因此聚酰胺树脂涂覆可能不是必须的。
涂覆聚酰胺树脂之后，树脂7通过压铸被填充在散热器3和4周围及其之间，图中未示出。一旦树脂7变硬，半导体器件1被从模具取出。在压铸中，铸型如此完成，以使下部散热器3的下表面和上部散热器4的上表面暴露出来，以便改善散热器3，4的散热效率。
在图1的半导体器件1中，半导体芯片2的厚度为t1和下部散热器3的厚度为t2，满足下式。
t2/t1≥5
在图1所示的半导体器件1中，上部散热器4的厚度也为t2。但上部散热器4的厚度不必为t2。通过设定t1和t2厚度以满足上式，有可能增加半导体芯片2内产生的压应力并减少芯片2表面的剪切应力，如下所述。
图3中的曲线绘制出实际上已被作为原型的多个半导体器件1的X-轴方向的厚度比和Y-轴方向的标准化压应力。原型中的压应力值被厚度比为3.75的半导体1的压应力值标准化。当具有厚度比3.75和标准化压应力1.00的原型半导体器件1被暴露于温度差相对大的热循环，原型半导体器件1的半导体芯片2开裂。当具有厚度比2.5和标准化压应力0.98的原型半导体器件1被暴露于热循环，原型半导体器件1的半导体芯片2也开裂。
另一方面，当具有厚度比7.00和标准化压应力1.09的原型半导体器件1，以及具有厚度比15.00和标准化压应力1.13的原型半导体器件1被暴露于热循环，原型半导体器件1的半导体芯片2保持完好。换言之，厚度比越大或器件1中的压应力越大，半导体芯片2开裂的可能性越小。因此，通过设定厚度比t2/t1大于5.00，器件1中的压应力保持足够高，并且即使当半导体器件1被暴露于相对大的热应力，器件1都不会破坏。结果，提高了半导体器件1的长期可靠性。
在不同的半导体器件1原型中的半导体芯片的表面的剪切应力通过模拟法进行了计算。图4的曲线绘制出多个半导体器件1的X-轴方向的厚度比t2/t1和Y-轴方向的标准化剪切应力。原型中的剪切应力值被厚度比为3.75的半导体1的剪切应力值标准化。当具有厚度比3.75和标准化剪切应力1.00被暴露于热循环，与半导体芯片2接触的树脂7分层。当具有厚度比2.5和标准化剪切应力1.02的原型半导体器件1被暴露于热循环，与半导体芯片2接触的树脂7也分层。
另一方面，当具有厚度比7.00和标准化剪切应力0.6的原型半导体器件1，以及具有厚度比15.00和标准化剪切应力0.15的原型半导体器件1被暴露于热循环，与半导体芯片2接触的树脂7不分层。换言之，厚度比t2/t1越大或半导体芯片2的剪切应力越小，在半导体芯片2的表面半导体芯片2分层的可能性越小。因此，通过设定厚度比t2/t1大于5.00，可防止与芯片2接触的树脂7分层，即使当半导体器件1暴露在相对大的热应力。结果，半导体器件1的长期可靠性进一步得到提高。
如上所述，图1的半导体器件优选高厚度比。通过减少半导体芯片2的厚度t1增加厚度比。减少厚度t1有另一个好处。那就是，器件的ON电阻会同步减少，因为芯片2中的电阻由于在图1的垂直方向的垂直电流路径而降低。通过增加下部散热器3的厚度t2也增加了厚度比。增加厚度t2有另一个好处，那就是下部散热器3的散热效率可被同步提高。
但是，由于制造中的实际限制，不可能使半导体芯片2的厚度t1小于0.1mm。另一方面，当下部散热器被增厚，整个半导体器件1变厚。因此，下部散热器3的实际最大厚度t2约为2.5mm。这样，最大可能厚度比实际约为25。考虑到芯片2制造可行性以及器件应用所带来的限制，优选厚度比约为7～8。
半导体器件1中的半导体芯片2的压应力分布通过模拟法进行了计算。图31A表示了半导体芯片2厚度为0.4mm情况下的分布。图31B表示了半导体芯片2厚度为0.2mm情况下的分布。如图31A和31B所示，随着厚度t1减小压应力增加。原因在于半导体芯片2的刚性减小并且半导体芯片2当厚度t1减小时变得易压缩。因此通过减小厚度t1，半导体芯片2的上下表面的剪切应力减小。
此外，如图32所示，焊料6中的应变分量，它与半导体芯片2接触，随着厚度t1减小而减少。特别地，当半导体芯片薄于250μm，剪切塑性应变小于约1％，并且半导体器件1热循环时的耐久性得到改善，如图34所示。
图34中，对实际上作为原型的多个半导体器件1的耐久性评估结果被表示为一个矩阵，其中使用三种符号表示，它们是圆圈，三角和十字。圆圈意味着原型半导体器件1中没有一个半导体芯片2破坏。三角表示一些半导体芯片2破坏。十字意味着所有半导体芯片2破坏。如图34所示，原型半导体器件1中的半导体芯片2具有更好的耐久性，其中半导体芯片2的厚度t1和下部散热器3的厚度t2满足关系t2/t1≥5。
下部散热器优选相对硬的材料，因为材料越硬，产生在半导体芯片2中的压应力越大。特别地，理想的是使用室温下杨氏模量大于100GPa的金属或合金做下部散热器3。杨氏模量大于100GPa的材料具有足够的刚性产生具有足够大压应力的半导体芯片2。满足上述下部散热器3杨氏模量要求的金属和合金的例子包括铜，铜合金，铝，铝合金等。
图1半导体器件中连接半导体芯片2和下部散热器3的焊料6可由二元焊料如Sn-Pb，Sn-Ag，Sn-Sb以及Sn-Cu或多元焊料构成。此外，铸模用树脂7可由环氧型树脂等构成。图1半导体器件1的下部散热器3和上部散热器4的厚度不必相同。可能只有下部散热器3的厚度被固定为t2，而上部4可有不同厚度。另外，上部散热器4和桥连芯片5可被集成为一个独立元件，只要元件和半导体芯片2间的校直是可能的并且芯片2上的控制电极能利用半导体器件1制造工艺中的接合引线10被引线接合到引线框架9a和9b。
第二实施例
在示于图1的半导体器件1中，按照第二实施例，散热器3，4的热膨胀系数α1以及树脂7的热膨胀系数α2被设定为满足下式。
0.5≤α2/α1≤1.5
通过这样设定热膨胀系数α2和α1，可能平衡半导体芯片2中的拉应力和半导体芯片2表面的剪切应力，如下所述。
如图5和33所示，在芯片2的一端的半导体芯片2中的拉应力随树脂7膨胀系数α2的增加而减少。拉应力是沿Z轴的应力，它是在图1的垂直方向，并且通过模拟法计算了对于树脂7具有不同热膨胀系数α2的各种半导体器件1的拉应力。图5和33的曲线中，X轴代表树脂7的热膨胀系数α2，而Y轴代表沿Z轴应力。模拟中，半导体器件1的散热器3，4假定由铜构成，铜的热膨胀系数α1为17ppm。如图5和33所示，树脂7的热膨胀系数α2越大，沿Z轴的拉应力越小。也即，树脂7的热膨胀系数α2越大，半导体芯片2在温差相对大的热循环中的拉应力越小。
但是，如图6所示，半导体芯片2表面的剪切应力随膨胀系数α2增加而减少。对于树脂7具有不同热膨胀系数α2的各种半导体器件1中的剪切应力通过模拟法进行了计算。剪切应力需足够小以阻止树脂7在相对大的热应力下从半导体芯片2的表面分层。然而，根据采用五个半导体器件1的实验结果，在图6中五个半导体器件实际上被作为原型而具有五个系数α2，只要热膨胀系数α2小于25ppm，此处α2/α1约为1.5，树脂7在相对大的热应力下不分层，并且在原型半导体器件1的半导体芯片2完好。
在图7中，X轴代表热膨胀系数比α2/α1，左边的Y轴代表焊料6中沿Z轴的应力，而右边Y轴代表半导体芯片2表面的剪切应力绝对值。两条曲线AA和BB，在图7中分别表示沿Z轴应力和热膨胀系数比α2/α1间的相关关系，以及剪切应力和热膨胀系数比α2/α1间的相关关系。
在图7中，沿Z轴应力值的上限为35到40MPa，因为连接半导体芯片2和散热器3，4的焊料6具有35-40MPa的实际最大抗拉强度，并且焊料6可被大于40MPa的拉应力破坏。因此，热膨胀系数比α2/α1必须大于0.5。另一方面，剪切应力的上限值约为50MPa，以阻止树脂7来自半导体芯片2表面和散热器3，4表面的分层。因此，热膨胀系数比α2/α1必须小于1.5。这样，热膨胀系数α1和α2需满足式：0.5≤α2/α1≤1.5。只要半导体器件1的结构满足这个条件，即使在相对大的热应力下也可防止半导体芯片2开裂并增强其长期稳定性。
根据实验结果，当散热器3，4由铜和铜合金构成时，铜和铜合金的热膨胀系数α1均约为17ppm，树脂7的热膨胀系数α2优选为大于10ppm。此外，当散热器3，4由铜烧结合金或包含铜的复合材料制成，二者均有约8ppm的热膨胀系数α1，优选树脂7的热膨胀系数α2大于6ppm。
在图1的半导体器件1中，树脂7具有大于10GPa的杨氏模量。考虑到半导体器件1中应力的总体平衡，用于保护器件1的树脂7的杨氏模量大于10Gpa是理想的。
在图1的半导体器件1中，散热器3，4的热膨胀系数α1和树脂7的热膨胀系数α2被设定为满足式0.5≤α2/α1≤1.5，而半导体芯片2的厚度t1和下部散热器3的厚度t2被设定为满足式t2/t1≥5，它是按照第一实施例的式子。但是，热膨胀系数α1和α2的条件以及厚度比t2/t1的条件可分别应用。即便在那种情况下，也提供基本相同的效应。
第三实施例
在图1的半导体器件1中，根据本发明的第三实施例，面对下部散热器3的半导体芯片2的下表面的表面粗糙度Ra满足下式。
Ra≤500nm
如图8所示，如果粗糙度Ra等于500nm或更小，可能防止半导体芯片2在相对的大的热应力下开裂，图8表示当具有不同表面粗糙度Ra的各种半导体器件1原型被暴露在热应力中时半导体芯片2的破裂百分比。
在图1的半导体器件1中，半导体芯片2的下表面的粗糙度Ra满足式Ra≤500nm，同时根据第一实施例的厚度比条件根据第二实施例的热膨胀系数α1和α2的条件被满足。但是，按照第三实施例的粗糙度条件可单独应用。即便如此，产生基本相同的效应。
第四实施例
在图1半导体器件1中，根据本发明的第四实施例，散热器3，4的厚度t2约为1.5mm，而半导体芯片2的厚度t1等于250μm或更小，以防止树脂7在图9所示的半导体芯片2的边缘2a分层。
半导体器件1中的半导体芯片2表面的剪切应力通过模拟法进行了计算，其中，散热器3，4的厚度t2约为1.5mm，并且半导体芯片2的厚度t1随参数而变。在图10曲线图中，X轴代表半导体芯片2的厚度，而Y轴代表芯片2表面的标准化剪切应力。剪切应力值被厚度为400μm的半导体芯片2的剪切应力值标准化，即厚度比t2/t1为3.75。如图10所示，半导体芯片2越薄，其剪切应力越小。
另一方面，根据实验结果，当具有厚度400μm的半导体芯片2，此处剪切应力比为1.00，被暴露于温差相对大的热循环时，树脂7从半导体芯片2的表面边缘2a分层。但是，当半导体器件1包含具有200μm厚度的半导体芯片2时，也即当厚度比为7.00且标准化剪切应力为0.6时，在热循环下，树脂7寿命增加10倍。当半导体芯片2的厚度为100μm，也即当厚度比为15.00且标准化剪切应力为0.15时，热循环中树脂在半导体芯片2的边缘2a不分层。
因此，半导体芯片2越薄，即厚度比越大及剪切应力越小，树脂7在半导体芯片2的边缘2a分层的可能性越小。
第五实施例
在图1半导体器件1中，按照第五实施例，连接半导体芯片2和散热器3的焊料6为锡-基焊料。如图11所示，锡-基焊料材料总体上比铅-基焊料有较高的机械强度。因此，通过使用锡-基焊料，可以增加回流工艺中冷却步骤之后半导体芯片2中的压应力。虽然锡-基焊料有许多可能的组成，但如果包含二或三种元素优选导致比铅-基焊料有更高强度和屈服应力的组成。在图11中，在150℃，每分钟6％的应变速率的拉应力实验下测量了断裂强度而屈服应力相对于25℃下的0.2％屈服点。此外，如图12所示，与铅-基焊料相比，总体上锡-基焊料有较低的应变速率，因此当半导体器件在回流焊工艺的冷却步骤之后被置于室温下，半导体芯片2中的压应力以较低速率释放。在图12中，10MPa应力下在50℃时的应变被测量。因此，如图13中的实施例所示，与铅-基焊料相比，锡-基焊料增加产生于半导体芯片2中的应力并更好的保持应力。在图13中，Y轴代表半导体芯片2中心的压应力大小。
在上述实施例中，焊料箔8被用于连接散热器3，4、半导体芯片2，以及桥连芯片以制造图1中的半导体器件1。但是，也可用焊膏代替焊料箔。此外，单个半导体芯片2被夹在图1半导体器件的散热器3，4之间。但也可能有两个或更多芯片，或两种或更多类型芯片被夹在散热器3，4之间。
第六实施例
如图14所示，按照第六实施例的半导体器件100包含半导体芯片2，它是一个DMOS型垂直功率MOSFET2，如图15所示。半导体器件100有和图1半导体器件1类似的结构。焊料6与芯片2和桥连芯片5接触以连接它们。桥连芯片5是由具有高热导的材料构成的板。另一焊料6与上部散热器4和桥连芯片5接触以连接它们。其它焊料6与芯片2和下部散热器3接触以连接它们。此外，芯片2通过接合引线与引线框架电连接。芯片2、桥连芯片5，及散热器3，4用树脂7转化铸模。但是，散热器4的上表面和散热器3的下表面被暴露出来而不被铸模树脂7覆盖，在图1的半导体器件1中也如此。
如图15所示，n一型硅衬底20具有前表面20a和后表面20b，前后表面相对。n-型硅衬底20具有25μm到150μm的厚度，因此衬底20中的电阻相对于图15中垂直方向的电流流量而言相对较低，并且垂直功率MOSFET的ON电阻也如此。
多个p-型基区21位于前表面20a中。两个n+-型源区22位于每个p-型基区21中。p-型基区21和n+-型源区2 2形成前掺杂区21，22。在前表面20a，设置多个多晶硅栅电极24。一个栅氧化物膜位于各个栅电极24和前表面20a之间。氧化膜25位于每个多晶硅栅电极24以覆盖每个电极24。源电极26位于氧化物膜25之上。源电极26基本上由铝构成。虽然没有表示出来，有一个钝化膜位于源电极26之上。
另一方面，一个n+-型漏极接触区27位于基本上整个后表面20b中。n+-型漏极接触区27是一个后掺杂区27。掺杂多晶硅膜28位于n+-型漏极接触区27的基本上整个表面上。漏电极29位于掺杂多晶硅膜28的基本上整个表面上。漏电极29包含钛、镍和金层。n+-型漏极接触区27由来自掺杂多晶硅膜28的扩散杂质形成。如图14所示，桥连芯片被连接到其上设有前掺杂区21、22的垂直功率MOSFET的表面。下部散热器3被连接到电极29。
垂直功率MOSFET2按下述方法制造。首先，栅氧化膜23和多晶硅栅电极24在n-型硅晶片30的前表面30a上形成，示于图16A中。然后，p-型基区21和n+-型源区22在前表面30a内形成。氧化物膜25在多晶栅电极24上形成，而源电极26被形成以通过在氧化物膜25内的接触孔25a与n-型硅衬底30产生电接触。
然后，如图16A所示，通过抛光晶片30的基本上整个后表面30b，它与图16A所示的前表面30a相对，将晶片30减薄至预定厚度。特别地，通过表面研磨，晶片30被减薄到约250μm厚。随后，如图16B所示，后表面30b通过罐腐蚀被腐蚀到预定厚度，晶片30的周边除外。如图16B所示，通过热腐蚀在晶片30内形成一个凹坑。特别地，如图17所示的腐蚀罐和图18所示的罐腐蚀系统被用于罐腐蚀，而晶片30除周边以外的部分被腐蚀到约25-150μm。虽然晶片30的直径为4到8英寸，但较厚的周边防止晶片30翘曲。
如图17所示，腐蚀罐包含一个板状罐底座(pot base)40和一个筒状罐套(pot ring)41。硅晶片30被放置在罐底座40的上面，而罐套41被放置在硅晶片30的上面，这样硅晶片30封闭了罐套41的开口。罐底座40的中心是一个容纳晶片30的平台。一个环状凹坑42位于围绕平台的罐底座40的周边。罐套41的凸出部分卡在凹坑42中。凹坑42用于校直罐套41。下部密封表面S1，它是一个平面且呈环状，位于围绕凹坑42的罐底座40上，如图17所示。环状凹坑44位于下部密封表面S1内起真空槽(vacuum pocket)的作用。
如图17所示，一个平面环状内垫圈Ps被固定在罐套41的下部的内表面中。内垫圈Ps防止充满罐套41的腐蚀溶液从有罐套41和安装在罐底座40上的硅晶片30形成的腐蚀缸中渗漏。此外，上部密封表面S2，它是平面且呈环状，位于罐套41的下部的凸缘上，如图17所示。一个环状凹坑45位于上部密封面S2内用作真空槽。如图17所示的一个外垫圈46，它呈环状且具有X形横断面，被置于下部密封表面S1和上部密封表面S2之间。通过使用真空泵将空气从凹坑44、45排除，X-型垫圈46被吸缩紧固罐基座40和罐套41，并使内垫圈Ps密封罐套41和晶片30间的间隙。具有上述结构的腐蚀罐被装在一个罐腐蚀系统中，如图18所示。然后，在腐蚀罐中装入腐蚀液Le。内垫圈Ps不仅密封罐套41和腐蚀液Le中的晶片30间的间隙，而且能防护晶片30的周边不接触腐蚀液Le。因此，当腐蚀罐内部充满腐蚀液Le时，只有晶片30的后表面30b，周边除外，接触到腐蚀液Le。
更特别地，腐蚀罐被安装到罐平台47，且腐蚀罐的上开口由盖48塞紧。搅拌器49由盖48支撑，并用密封材料50密封。搅拌器49有马达51驱动来搅拌腐蚀液Le。用于加热腐蚀液Le的加热子52由盖48支撑并用密封材料53密封。用于测量腐蚀液Le温度的温度传感器54由盖48支撑并由密封材料55密封。通过图18的罐腐蚀系统腐蚀过程中，腐蚀液Le不断被搅拌器49搅拌，而加热子52由温度控制器56电控，以保持腐蚀液温度在温度传感器54感知的预定温度。
此外，盖48包含一个去离子水(DIW)通道，因此去离子水可以沿罐套41的内壁向下注入腐蚀罐。盖48也包含一个排水口58用于通过从腐蚀罐溢流排除废水。罐底座40包含一个厚度传感器59，它测量凹坑中硅晶片30的厚度以监测腐蚀进程并探测腐蚀终点。当预定厚度被腐蚀且凹坑中晶片30的厚度达到预定厚度，通过通道57将去离子水导入腐蚀罐以稀释和冷却腐蚀液Le并停止腐蚀过程。溢流的废水被从排水口58排出。然后，真空泵停止从凹坑44，45排除空气，且凹坑44，45恢复到大气压力。然后，将盖48和罐套41拿开。在此阶段，被腐蚀的硅晶片30具有如图16B的横断面结构。
其次，如图16C所示，用于形成图15中掺杂多晶硅膜28的掺杂多晶硅膜31被淀积在晶片30的被腐蚀过的后表面30b上。杂质从掺杂多晶硅膜31扩散进入晶片30以在晶片30的后表面30b形成n+-型漏电极接触区27。更特殊地，掺杂多晶硅膜31通过低压CVD或诸如溅射法的PVD于低于450℃被淀积。多晶硅具有比单晶高数倍的扩散速率，并且在晶粒间能够保持高的杂质浓度。结果，即使铝源电极26形成之后，多晶硅能够在后表面30b注入高的杂质浓度。这样，通过淀积掺杂多晶硅膜31和通过退火从掺杂多晶硅膜31引入杂质，在低于450℃下形成n+漏极接触区27，该区能使衬底20和半导体芯片(2)中的漏电极29之间形成低电阻欧姆接触。
其次，如图16D所示，在掺杂多晶硅膜31上淀积用于形成漏电极29的后侧电极32。特别地，Ti、Ni和Au膜被依次淀积。下一步，如图19和20所示，具有相对高地热导的铜板33被焊接到晶片30的前表面30a，源电极26位于其上。然后，晶片30和铜板33被同时切成小块并分成多个焊接芯片，每个芯片包含一个半导体芯片2和一个桥连芯片5。切割晶片30之前焊接铜板33和晶片30存在一个好处。如果晶片30没有铜板33支持被切割成多个半导体芯片2，如图16B所示，由于半导体芯片2薄至25～150μm，因此切割之后很难处理。另一方面，由于桥连芯片5被焊接到半导体芯片2，被焊接后的芯片更易处理。
如图19和20所示，晶片30为圆片形，而铜板33为方形。在板33上形成多个凸起33a。每个凸起33a与位于晶片30中的每个半导体芯片2上的每个源电极26相匹配。凸起33a可通过在平面铜板上形成电镀镍膜以及通过压合镍膜而形成。当板33被焊接到晶片33，板33的每个凸起33a对准晶片30的每个芯片2的相应源电极26。如图21和22所示，在切割后每个被焊芯片中，焊料6与桥连芯片5和半导体芯片2的源电极26接触以将半导体芯片2和桥连芯片5机械和电连接。其次，如图14所示，散热器3、4被分别焊接到每个被焊芯片的半导体芯片2和桥连芯片5。然后，散热器3、4，半导体芯片2，以及桥连芯片5被如此压铸，以使散热器4的上表面和下部散热器3的下表面被暴露出来，如图14所示。
通过根据第六实施例罐腐蚀法，可以减薄其中形成半导体芯片2的晶片30的活性区，而保持晶片30的周边较厚。因此，使用例如溅射法，可能在晶片30的后表面形成漏接触电极而不在晶片30内产生翘曲‘并且可能避免与晶片30中的机械强度问题有关的问题。此外，半导体芯片2的制造成本被减少，因为不必形成外延层用于在晶片上制作衬底20，它具有用于制造n+-型漏接触区27的优选杂质浓度。
在根据第六实施例的制造方法中，当P-型基区21和n+-型源区22，铝源电极26，以及钝化膜如SiN和PIQ在晶片30的前表面30a形成之后，通过由掺杂多晶硅膜28构成的掺杂多晶硅膜31，在晶片30的厚表面30b由形成n+-型漏接触区27，它是一个高掺杂层27。但是，通过在优选低工艺温度下来自掺杂多晶硅膜31的杂质扩散，形成能够在后侧电极32上形成低电阻欧姆接触的高掺杂层27，在半导体器件100的制造过程中，后侧电极接触能够在优选低工艺温度下建立。因此，能够确保比下面描述的建议方法具有更高的可靠性。
传统地，高掺杂层27既可通过离子注入也可通过热扩散形成。离子注入需要500-700℃的后加工退火，以接近100％激活高剂量注入离子。另一方面，热扩散比离子注入需要更高的温度和更长时间。但是，处理温度必须低于铝的软化温度450℃，因为处理工艺是在铝电极在晶片30的前表面30a上形成之后进行的。因此，在建议方法中，退火效果不明显。
在图14，21和22中，面对半导体芯片2的桥连芯片5的表面比面对散热器4的桥连芯片的表面小。但是，在图23、24和25中的桥连芯片60尺寸关系可能相反。
进一步，如图26和27所示，另一个具有高热导的铜板70可被焊接到晶片30的后侧电极32。当铜板33被焊接到晶片30的源电极26上时，铜板70可被焊接。然后，晶片30和铜板33、70被切割并分成多个被焊接芯片。然后，每个芯片被焊接到散热器3、4，并且用树脂7铸型以完成如图28所示的半导体器件300。在图28所示的半导体器件300中，半导体芯片2实际上通过板70被定位于图28垂直方向的器件300的中心，板70将硅芯片2和下部散热器3分隔开。结果，散热能力提高，且器件300中的热应变被平衡，在芯片2中由于应变产生的应力减少。这样，在热循环中器件300具有更好的耐久性。
在根据上述实施例的半导体器件1，100，200，300中，半导体芯片2是一个垂直MOSFET。然而，芯片2也可以是一个垂直IGBT(绝缘栅双极晶体管)。在此情况下，后侧电极29作为收集极电极。

Claims (22)

1.一种半导体器件(1)，包含：
一个在工作中产生热的半导体芯片(2)；
一对用于释放来自半导体芯片(2)的热以使该半导体芯片(2)冷却的金属板(3，4)，其中半导体芯片(2)被连接到金属板(3，4)之一；以及
铸模树脂(7)，半导体芯片(2)和金属板(3，4)被埋置其中，使得每个金属板(3，4)的一个表面被暴露以改善从金属板(3，4)的散热效率，其中半导体芯片(2)的厚度t1和金属板(3，4)之一的厚度t2满足式t2/t1≥5。
2.权利要求1的半导体器件(1)，其中金属板(3，4)具有热膨胀系数α1，而铸模树脂(7)具有热膨胀系数α2，使得热膨胀系数α1和热膨胀系数α2满足式0.5≤α2/α1≤1.5。
3.权利要求1或权利要求2中的半导体器件(1)，其中半导体芯片(2)的表面，在此表面半导体芯片(2)被连接到金属板(3，4)之一，具有满足式Ra≤500 nm的表面粗糙度Ra。
4.一种半导体器件(1)，包含：
一个在工作中产生热的半导体芯片(2)；
一对用于释放来自半导体芯片(2)的热以使该半导体芯片(2)冷却的金属板(3，4)，其中半导体芯片(2)被连接到金属板(3，4)之一；以及
铸模树脂(7)，半导体芯片(2)和金属板(3，4)被埋置其中，使得每个金属板(3，4)的一个表面被暴露以改善金属板(3，4)的散热效率，其中金属板(3，4)的热膨胀系数α1和铸模树脂(7)的热膨胀系数α2满足式0.5≤α2/α1≤1.5。
5.权利要求4的半导体器件(1)，其中半导体芯片(2)的表面，在此表面半导体芯片(2)被连接到金属板(3，4)之一，具有满足式Ra≤500nm的表面粗糙度Ra。
6.一种半导体器件(1)，包含：
一个在工作中产生热的半导体芯片(2)；
一对用于释放来自半导体芯片(2)的热以使该半导体芯片(2)冷却的金属板(3，4)，其中半导体芯片(2)被连接到金属板(3，4)之一；以及
铸模树脂(7)，半导体芯片(2)和金属板(3，4)被埋置其中，使得每个金属板(3，4)的一个表面被暴露以改善从金属板(3，4)的散热效率，其中半导体芯片(2)的表面，在此表面半导体芯片(2)被连接到金属板(3，4)之一，具有满足式Ra≤500nm的表面粗糙度Ra。
7.一种半导体器件(1)，包含：
具有第一表面和第二表面的且在工作中产生热的半导体芯片(2)；
作为电极的被连接到半导体芯片(2)的第一表面的第一金属板(3)，和用于释放来自半导体芯片(2)的热以冷却该半导体芯片(2)的散热器；
第二金属板(4)；
被连接到半导体芯片(2)的第二表面的第三金属板(5)，其中第二金属板(4)被连接到第三金属板(5)用于用作电极以及用于通过第三金属板(5)释放来自半导体芯片(2)的热以冷却半导体芯片(2)的散热器；
一对接合层(6)，由此将半导体芯片(2)的第一表面和第一金属板(3)连接在一起，并将半导体芯片(2)的第二表面和第三金属板(5)连接在一起；以及
铸模树脂(7)，其中埋置半导体芯片(2)和金属板(3，4，5)以使第一和第二金属板(3，4)中每个的一个表面暴露，以便改善第一和第二金属板(3，4)的散热效率，其中半导体芯片(2)相对较薄，以致半导体芯片(2)在第一表面具有预定的低剪切应力且接合层(6)具有预定的低应变。
8.权利要求7的半导体器件(1)，其中半导体芯片(2)的厚度等于或小于250μm。
9.权利要求7或权利要求8的半导体器件(1)，其中金属板(3，4，5)之一具有1.0mm或更大的厚度。
10.权利要求7的半导体器件(1)，其中接合层(6)具有1％或更小的剪切塑性应变。
11.权利要求7的半导体器件(1)，其中半导体芯片(2)的第一表面具有35MPa或更小的剪切应力。
12.权利要求7到11中任何之一的半导体器件(1)，其中接合层(6)由锡-基焊料构成，用于抑制半导体芯片(2)中压应力的松弛，其中该松弛是由接合层(6)的蠕变引起的。
13.权利要求7到12中任何之一的半导体器件(1)，其中半导体芯片(2)是沟槽栅型功率半导体芯片。
14.权利要求7的半导体器件(1)，其中半导体芯片(2)的厚度t1和第一金属板(3)的厚度t2满足式t2/t1≥5。
15.权利要求14的半导体器件(1)，其中金属板(3，4，5)具有热膨胀系数α1，铸模树脂(7)具有热膨胀系数α2，使得热膨胀系数α1和热膨胀系数α2满足式0.5≤α2/α1≤1.5。
16.权利要求14或权利要求15的半导体器件(1)，其中半导体芯片(2)的第一表面具有满足式Ra≤500nm的表面粗糙度Ra。
17.一种用于制造包含半导体芯片(2)的半导体器件(100，200，300)的方法，该方法包括以下步骤：
在半导体晶片(30)的前表面(30a)中形成前掺杂区(21，22)；
通过抛光晶片(30)的基本上整个后表面(30b)，将半导体晶片(30)减薄至预定厚度，其中后表面(30b)与前表面(30a)相对；
将后表面(30b)腐蚀至预定深度，晶片(30)的周边除外；
通过在腐蚀步骤之后在后表面(30b)上淀积掺杂的多晶硅膜(31)，以及通过将杂质从掺杂多晶硅膜(31)扩散进入后表面(30b)中，在后表面(30b)中形成后掺杂层(27)；以及
在掺杂的多晶硅膜(31)上形成后侧电极(32)。
18.权利要求17的方法，包括以下步骤：
在形成后侧电极(32)的步骤之后，将晶片(30)切割成小片以将晶片(30)分成多个半导体芯片(2)；
在每个半导体芯片(2)上焊接一对金属板(3，4)；以及
用铸模树脂(7)铸型每个半导体芯片(2)和金属板(3，4)，使得每个金属板(3，4)的一个表面暴露，以改善金属板(3，4)的散热效率。
19.权利要求17的方法，包括以下步骤：
在形成后侧电极(32)的步骤之后，将晶片(30)切割成小片以将晶片(30)分成多个半导体芯片(2)；
将每个半导体芯片(2)和一个桥连芯片(5)叠放在一起；
在每个半导体芯片(2)和一个桥连芯片(5)上分别焊接一对金属板(3，4)；以及
用铸模树脂(7)铸型每个半导体芯片(2)和金属板对(3，4)，使得每个金属板(3，4)的一个表面暴露，以改善金属板(3，4)的散热效率。
20.权利要求17的方法，包括以下步骤：
焊接具有相对高热导的板(33)到晶片(30)的前表面(30a)上；
将晶片(30)和板(33)切割成小片，以将晶片(30)和板(33)分成多个包含半导体芯片(2)和桥连芯片(5)的被焊接芯片；
在每个被焊接芯片的半导体芯片(2)和桥连芯片(5)上分别焊接一对金属板(3，4)；以及
用铸模树脂(7)铸型每个被焊接芯片和和金属板对(3，4)，使得每个金属板(3，4)的一个表面暴露，以改善金属板(3，4)的散热效率。
21.权利要求20的方法，包括将另一具有相对高热导的板(70)焊接到后侧电极(32)上的步骤。
22.权利要求17到21中任何之一的方法，其中半导体芯片(2)是一个垂直功率MOS晶体管(2)。
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6660664B1 (en) * 2000-03-31 2003-12-09 International Business Machines Corp. Structure and method for formation of a blocked silicide resistor
EP1424728A1 (de) * 2002-11-27 2004-06-02 Abb Research Ltd. Leistungshalbleitermodul
JP3870896B2 (ja) * 2002-12-11 2007-01-24 株式会社デンソー 半導体装置の製造方法およびそれにより製造される半導体装置
US20040212080A1 (en) * 2003-04-22 2004-10-28 Kai-Chi Chen [chip package structure and process for fabricating the same]
JP3661695B2 (ja) * 2003-07-11 2005-06-15 株式会社デンソー 半導体装置
US7180165B2 (en) * 2003-09-05 2007-02-20 Sanmina, Sci Corporation Stackable electronic assembly
EP1681369A4 (en) * 2003-09-30 2008-10-01 Japan Science & Tech Agency METHOD AND DEVICE FOR PRODUCING A METAL THIN-FILM CHIP
US7239016B2 (en) * 2003-10-09 2007-07-03 Denso Corporation Semiconductor device having heat radiation plate and bonding member
DE102004055908A1 (de) * 2003-11-21 2005-07-28 Denso Corp., Kariya Halbleiteranordnung mit einem Paar von Wärmeabstrahlplatten
JP2005167075A (ja) * 2003-12-04 2005-06-23 Denso Corp 半導体装置
JP4254527B2 (ja) * 2003-12-24 2009-04-15 株式会社デンソー 半導体装置
JP2005203548A (ja) * 2004-01-15 2005-07-28 Honda Motor Co Ltd 半導体装置のモジュール構造
JP4302607B2 (ja) * 2004-01-30 2009-07-29 株式会社デンソー 半導体装置
JP3829860B2 (ja) * 2004-01-30 2006-10-04 株式会社デンソー 半導体チップの製造方法
DE102004012818B3 (de) * 2004-03-16 2005-10-27 Infineon Technologies Ag Verfahren zum Herstellen eines Leistungshalbleiterbauelements
DE102005016830A1 (de) * 2004-04-14 2005-11-03 Denso Corp., Kariya Halbleitervorrichtung und Verfahren zu ihrer Herstellung
JP2005310956A (ja) * 2004-04-20 2005-11-04 Denso Corp 半導体装置の製造方法
US20060022263A1 (en) * 2004-07-30 2006-02-02 International Rectifier Corporation Selective substrate thinning for power mosgated devices
JP4604641B2 (ja) * 2004-10-18 2011-01-05 株式会社デンソー 半導体装置
DE102005001151B4 (de) * 2005-01-10 2012-04-19 Infineon Technologies Ag Bauelementanordnung zur Serienschaltung bei Hochspannungsanwendungen
JP2007073743A (ja) * 2005-09-07 2007-03-22 Denso Corp 半導体装置
JP4858290B2 (ja) * 2006-06-05 2012-01-18 株式会社デンソー 負荷駆動装置
JP2007335663A (ja) * 2006-06-15 2007-12-27 Toyota Motor Corp 半導体モジュール
JP4967472B2 (ja) * 2006-06-22 2012-07-04 富士電機株式会社 半導体装置
DE102006046789A1 (de) * 2006-10-02 2008-04-03 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zur Herstellung elektronischer Bauteile
JP2008124430A (ja) * 2006-10-18 2008-05-29 Hitachi Ltd パワー半導体モジュール
US7612447B2 (en) * 2007-06-06 2009-11-03 Gm Global Technology Operations, Inc. Semiconductor devices with layers having extended perimeters for improved cooling and methods for cooling semiconductor devices
US7737548B2 (en) * 2007-08-29 2010-06-15 Fairchild Semiconductor Corporation Semiconductor die package including heat sinks
JP4901669B2 (ja) * 2007-09-26 2012-03-21 株式会社東芝 半導体パッケージ及び半導体パッケージの製造方法
US7773381B2 (en) 2007-09-26 2010-08-10 Rohm Co., Ltd. Semiconductor device
US8710568B2 (en) * 2007-10-24 2014-04-29 Denso Corporation Semiconductor device having a plurality of elements on one semiconductor substrate and method of manufacturing the same
US8211752B2 (en) 2007-11-26 2012-07-03 Infineon Technologies Ag Device and method including a soldering process
JP4748173B2 (ja) * 2008-03-04 2011-08-17 株式会社デンソー 半導体モジュール及びその製造方法
JP2009283741A (ja) * 2008-05-23 2009-12-03 Fuji Electric Device Technology Co Ltd 半導体装置
US7759778B2 (en) * 2008-09-15 2010-07-20 Delphi Technologies, Inc. Leaded semiconductor power module with direct bonding and double sided cooling
US8507352B2 (en) 2008-12-10 2013-08-13 Denso Corporation Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode
CN102473653B (zh) * 2010-02-01 2016-05-04 丰田自动车株式会社 半导体装置的制造方法以及半导体装置
JP5545000B2 (ja) 2010-04-14 2014-07-09 富士電機株式会社 半導体装置の製造方法
US8513798B2 (en) 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
DE102011076662A1 (de) * 2011-05-30 2012-12-06 Robert Bosch Gmbh Halbleiterbauelement und entsprechendes Herstellungsverfahren
JP2013021254A (ja) * 2011-07-14 2013-01-31 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP5888051B2 (ja) * 2012-03-27 2016-03-16 三菱電機株式会社 ウエハ吸着方法、ウエハ吸着ステージ、ウエハ吸着システム
JP2013232495A (ja) * 2012-04-27 2013-11-14 Mitsubishi Electric Corp 半導体装置
US10229870B2 (en) * 2012-11-30 2019-03-12 Infineon Technologies Ag Packaged semiconductor device with tensile stress and method of making a packaged semiconductor device with tensile stress
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CN105103272B (zh) 2013-09-27 2018-10-09 富士电机株式会社 半导体装置的制造方法
JP6384406B2 (ja) 2015-06-18 2018-09-05 株式会社デンソー 半導体装置
JP6822000B2 (ja) 2016-08-05 2021-01-27 株式会社デンソー 半導体装置
KR101905995B1 (ko) * 2016-11-09 2018-10-10 현대자동차주식회사 양면냉각형 파워모듈
KR101956996B1 (ko) * 2016-12-15 2019-06-24 현대자동차주식회사 양면냉각형 파워모듈
FR3092698B1 (fr) * 2019-02-11 2021-05-07 St Microelectronics Tours Sas Assemblage comportant un composant vertical de puissance monté sur une plaque métallique de connexion
US11081422B2 (en) * 2019-03-14 2021-08-03 Toyota Motor Engineering & Manufacturing North America, Inc. Self-healing PDMS encapsulation and repair of power modules
KR102614904B1 (ko) * 2019-05-02 2023-12-15 알파 앤드 오메가 세미컨덕터 (케이맨) 리미티드 전력 반도체 패키지 및 이를 포함하는 고전압 컨버터
JP7367352B2 (ja) * 2019-06-24 2023-10-24 富士電機株式会社 半導体モジュール、車両、および半導体モジュールの製造方法
TWI752398B (zh) 2020-01-02 2022-01-11 財團法人工業技術研究院 功率模組
JP7183354B1 (ja) * 2021-07-27 2022-12-05 三菱電機株式会社 半導体モジュール

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2556749A1 (de) * 1975-12-17 1977-06-23 Bbc Brown Boveri & Cie Leistungshalbleiterbauelement in scheibenzellenbauweise
DE2810416C2 (de) 1978-03-10 1983-09-01 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Halbleiterbauelement mit Kunststoffummantelung
JPS5662342A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device
JPS56146261A (en) 1980-04-15 1981-11-13 Hitachi Ltd Semiconductor device
JPS5787139A (en) * 1980-11-19 1982-05-31 Hitachi Ltd Semiconductor device
JPS58165348A (ja) 1982-03-26 1983-09-30 Hitachi Ltd 半導体装置の配線板
JPS61234041A (ja) 1985-04-09 1986-10-18 Tdk Corp 半導体装置及びその製造方法
JPS63142640A (ja) 1986-12-05 1988-06-15 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JPH01272183A (ja) * 1988-04-25 1989-10-31 Toshiba Corp セラミックス回路基板
US4970579A (en) * 1988-09-21 1990-11-13 International Business Machines Corp. Integrated circuit package with improved cooling means
US5157478A (en) * 1989-04-19 1992-10-20 Mitsubishi Denki Kabushiki Kaisha Tape automated bonding packaged semiconductor device incorporating a heat sink
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5164815A (en) * 1989-12-22 1992-11-17 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
JP2513055B2 (ja) 1990-02-14 1996-07-03 日本電装株式会社 半導体装置の製造方法
JPH0411758A (ja) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp 半導体装置
US5293301A (en) * 1990-11-30 1994-03-08 Shinko Electric Industries Co., Ltd. Semiconductor device and lead frame used therein
JPH0563113A (ja) 1991-09-04 1993-03-12 Sony Corp 樹脂封止型半導体装置
US5200809A (en) * 1991-09-27 1993-04-06 Vlsi Technology, Inc. Exposed die-attach heatsink package
JPH05109945A (ja) * 1991-10-21 1993-04-30 Mitsubishi Electric Corp 半導体冷却装置
JP3284604B2 (ja) * 1992-09-18 2002-05-20 株式会社デンソー 放熱板付樹脂封止半導体装置の製造方法
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
JPH06268114A (ja) 1993-03-12 1994-09-22 Nippon Steel Corp 半導体装置
JPH06275759A (ja) * 1993-03-17 1994-09-30 Fujitsu Ltd 半導体装置及びその製造方法
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
JPH06334069A (ja) 1993-05-24 1994-12-02 Toyota Autom Loom Works Ltd ヒートスプレッダを内蔵した半導体パッケージ
US6552417B2 (en) * 1993-09-03 2003-04-22 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
JPH0799272A (ja) 1993-09-28 1995-04-11 Fuji Xerox Co Ltd 電子回路実装体
JPH07153878A (ja) 1993-11-26 1995-06-16 Tokyo Tungsten Co Ltd プラスチックパッケージされた半導体装置ならびにヒートシンクの製造方法
EP0658937A1 (en) * 1993-12-08 1995-06-21 Hughes Aircraft Company Vertical IC chip stack with discrete chip carriers formed from dielectric tape
JP3362530B2 (ja) * 1993-12-16 2003-01-07 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
DE4421319A1 (de) * 1994-06-17 1995-12-21 Abb Management Ag Niederinduktives Leistungshalbleitermodul
CN1123515A (zh) 1994-11-24 1996-05-29 三菱电机株式会社 树脂模压的电子电路装置
KR0170023B1 (ko) * 1994-12-16 1999-02-01 황인길 반도체 패키지
US5726466A (en) * 1995-09-11 1998-03-10 Kabushiki Kaisha Toshiba Press pack power semiconductor device incorporating a plurality of semiconductor elements
JPH0982859A (ja) * 1995-09-11 1997-03-28 Toshiba Corp ヒートシンク組立体
US5847929A (en) * 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
JPH10116934A (ja) 1996-10-09 1998-05-06 Fuji Electric Co Ltd 樹脂封止半導体装置およびその製造方法
US5825087A (en) * 1996-12-03 1998-10-20 International Business Machines Corporation Integral mesh flat plate cooling module
US6114413A (en) * 1997-07-10 2000-09-05 International Business Machines Corporation Thermally conducting materials and applications for microelectronic packaging
KR19990071282A (ko) * 1998-02-28 1999-09-15 구본준 반도체 패키지 제조방법
US6329705B1 (en) * 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
JP3922809B2 (ja) 1998-07-09 2007-05-30 株式会社東芝 半導体装置
JP3427751B2 (ja) 1998-10-20 2003-07-22 株式会社デンソー 半導体チップの薄肉加工方法および薄肉加工用エッチング装置
US6442033B1 (en) * 1999-09-24 2002-08-27 Virginia Tech Intellectual Properties, Inc. Low-cost 3D flip-chip packaging technology for integrated power electronics modules
US6693350B2 (en) 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US6703707B1 (en) 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
US6559525B2 (en) * 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
US6246111B1 (en) * 2000-01-25 2001-06-12 Siliconware Precision Industries Co., Ltd. Universal lead frame type of quad flat non-lead package of semiconductor
EP1128432B1 (de) * 2000-02-24 2016-04-06 Infineon Technologies AG Befestigung von Halbleitermodulen an einem Kühlkörper
TW476147B (en) * 2001-02-13 2002-02-11 Siliconware Precision Industries Co Ltd BGA semiconductor packaging with through ventilator heat dissipation structure
US6853070B2 (en) * 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
JP4479121B2 (ja) * 2001-04-25 2010-06-09 株式会社デンソー 半導体装置の製造方法
JP2003124437A (ja) * 2001-10-19 2003-04-25 Mitsubishi Electric Corp 半導体装置

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1319161C (zh) * 2003-03-26 2007-05-30 株式会社电装 半导体器件
CN100382288C (zh) * 2003-05-26 2008-04-16 株式会社电装 具有冷却系统的半导体装置
CN100353541C (zh) * 2003-06-23 2007-12-05 株式会社电装 塑模型半导体器件及其制造方法
CN100350598C (zh) * 2003-09-17 2007-11-21 株式会社电装 具有一对散热器的半导体器件及其制造方法
CN100343987C (zh) * 2003-10-29 2007-10-17 株式会社电装 具有金属板和半导体芯片的半导体器件
CN101569009A (zh) * 2006-09-29 2009-10-28 美高森美公司 塑料表面安装大面积功率器件
CN102088008A (zh) * 2010-01-28 2011-06-08 江苏长电科技股份有限公司 内脚露出芯片倒装带锁定孔散热块封装结构
CN102044508A (zh) * 2010-01-30 2011-05-04 江苏长电科技股份有限公司 树脂线路板芯片正装锁孔散热块凸柱外接散热器封装结构
CN102299117A (zh) * 2010-06-23 2011-12-28 株式会社电装 具有冷却机制的半导体模块及其生产方法
CN103836191A (zh) * 2012-11-27 2014-06-04 北京航天试验技术研究所 一种低温传感器密封方法
CN105555848A (zh) * 2013-09-24 2016-05-04 日东电工株式会社 半导体芯片密封用热固化性树脂片及半导体封装体的制造方法
CN105555848B (zh) * 2013-09-24 2019-04-23 日东电工株式会社 半导体芯片密封用热固化性树脂片及半导体封装体的制造方法
CN106463491A (zh) * 2014-06-02 2017-02-22 株式会社电装 半导体装置
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CN106298729A (zh) * 2015-05-12 2017-01-04 南茂科技股份有限公司 封装结构及其制作方法
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CN109874371A (zh) * 2016-09-23 2019-06-11 株式会社电装 半导体装置
CN109874371B (zh) * 2016-09-23 2021-03-30 株式会社电装 半导体装置

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US7145254B2 (en) 2006-12-05
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