CN1890809A - 带有增强内连接金属化部的引线接合的半导体元件 - Google Patents

带有增强内连接金属化部的引线接合的半导体元件 Download PDF

Info

Publication number
CN1890809A
CN1890809A CNA2004800369010A CN200480036901A CN1890809A CN 1890809 A CN1890809 A CN 1890809A CN A2004800369010 A CNA2004800369010 A CN A2004800369010A CN 200480036901 A CN200480036901 A CN 200480036901A CN 1890809 A CN1890809 A CN 1890809A
Authority
CN
China
Prior art keywords
metallization
wire
semiconductor
chip
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800369010A
Other languages
English (en)
Inventor
J·贝伦斯
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1890809A publication Critical patent/CN1890809A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

半导体元件包括由掺杂硅衬底制成的半导体芯片(2)，所述芯片掺入半导体器件中并且进行构造，并且包括位于接触窗口中的内连接金属化部(7)，并且所述半导体芯片的所述内连接金属化部通过引线接合连接(9)连接到相应外连接金属化部上，其特征在于，内连接金属化部包括具有位于掺杂硅衬底上的开放栅格结构的增强系统(8)。

Description

带有增强内连接金属化部的引线接合的半导体元件
本发明涉及一种引线接合的半导体元件，包括由掺杂硅衬底制成的半导体芯片，该芯片被掺入半导体器件中并进行构造，并且包括接触窗口中的内连接金属化部，所述半导体芯片的所述内连接金属化部通过接合引线回路连接到半导体元件的相应外连接金属化部。
引线接合的半导体芯片通过接合引线与外界电连接，所述接合引线在半导体芯片与陶瓷衬底、十字叉状载体或引线框架的连接插脚上的外连接金属化部形成连接，以及与另一个半导体芯片的连接金属化部形成连接。在半导体芯片上，接合引线端接于电流连接部分中，该电流连接部分与提供于接触窗口中的芯片表面上的金属化部一起形成冶金接触点。
在接合引线的电流连接部分、金属化部以及芯片表面之间，必须形成导电良好、机械稳定以及可靠的冶金接触点。
然而，引线接合中涉及的工序很敏感。经验表明，通常使用的冷焊过程对芯片表面产生相当大的机械负荷。特别是在超声引线接合的情况下，机械负荷和超声应力都应用于接触点上。在引线接合期间引起的损害通常并不立刻显现，但是在半导体器件操作期间，当随后的封装于外壳中的操作、促进使用寿命试验或温度变化对半导体元件应用进一步的热机负荷时，这种损害自身就出现。
损害可表现为微裂纹，该微裂纹可能扩展，产生致命的裂纹(裂缝)，或表现为脆性的、机械上薄弱的电介质层中的焊口，其常常延伸至金属化部(坑穴)，或表现为脱离金属化部层。
在集成电路的情况下，已知的是在设置于金属化部的顶层上的大接合垫盘下面提供增强系统。例如，EP 0 875 934公开了用于接合垫盘的增强系统，其包括在接合垫盘之下的至少一个电介质层和位于电介质层内的带图案增强系统。
在带有分立的半导体器件的半导体芯片的情况下，接触点并不一定通过提供在电介质层(中间体氧化物)上的金属化部层来制做，而是可替代地通过绝缘涂层或钝化层中的接触窗口中的冶金接触点直接制做于芯片表面上，以便限制接触点需要的空间和增加性能。
在分立的半导体器件中，接合引线的电流连接部分通过其与芯片表面上的金属化部接触的接触表面比较小，因此冶金接触点中的连接强度相应地非常弱。因此，使得接合引线通过金属化部连接到芯片表面上的连接特别容易断裂或形成坑穴，其中裂缝或坑穴延伸至芯片的表面中。
为了解决上述问题，本发明的一个目的是提供引线接合的半导体元件，其中引线接合连接从半导体芯片表面上分离的趋势得以减少，同时电属性基本上没有改变。
根据本发明，这个目的通过一种引线接合半导体元件来实现，所述半导体元件包括由掺杂硅衬底制成的半导体芯片2，该芯片掺入半导体器件中并且进行构造，并且包括位于接触窗口中的内连接金属化部7，并且所述半导体芯片的所述内连接金属化部通过引线接合连接9连接到相应外连接金属化部上，并且该内连接金属化部包括具有位于掺杂硅衬底上的开放栅格结构的增强系统8。
本发明基于以下发明构思，即根据本发明的带有增强系统的内连接金属化部使得能够获得大面积、力耦接触点；以及基于以下发明构思，即通过压缩两层具有不同物理性能的材料，就中断了在接触点区域中的力的侧向线。
因此增强系统减少了由热机应力引起问题的可能性。内连接金属化部和半导体芯片表面之间的力耦被连续地中断。出现的所有应力并不被传递因此不能累加到临界大小。
增强系统还将连接金属化部和半导体芯片的热膨胀系数之间的差别减至最小，因此改进了半导体元件的可靠性。
根据本发明的优选实施例，增强系统为由隔离涂层形成的开放栅格结构。
特别优选的是增强系统为由热氧化物形成的开放栅格结构。热氧化物通过半导体表面的转换而在内部产生进而形成特征层。
在本发明的范围内，优选的是形成的栅格结构为开放的凹槽结构。
根据本发明的另一个实施例，形成的栅格结构可为开放的管状结构。
当栅格结构的表面比例大于接触面积的50％时，就实现了最佳效果。
本发明的这些和其它方面可以清楚地从下面所述的实施例看出，并参考它们来阐明。
在附图中：
图1为带有引线接合接触点、金属化部和增强系统的半导体芯片的示意性剖视图。
图2为带有引线接合接触点、金属化部和增强系统的半导体芯片的示意性平面图。
图3示出了具有开放栅格结构的各种增强系统。
图4为一种常规型SMD包装的示意性侧视图，所述常规型SMD包装带有半导体芯片、引线接合连接和具有位于衬底上的连接插脚的引线框架。
尽管在下文中参考SMD双极型晶体管作为半导体元件对本发明进行描述，但本发明所属领域的普通技术人员应当理解本发明并不限于所述晶体管。
本发明整体涉及所有带有引线接合连接的半导体元件，并且其中接合引线回路的冶金接触点与半导体芯片晶体表面处的连接金属化部直接接触。
半导体器件可优选地为分立式双极型晶体管，特别是平面晶体管或场效应晶体管，以及半导体二极管，特别是结型二极管或肖特基二极管，以及传感器器件、电容器、电阻器或这些器件及其它器件的组合。
根据本发明的一个实施例，这种类型的半导体器件特别是分立式双极型晶体管，其带有适当掺杂并构造的半导体芯片，半导体芯片具有基极、集电极和发射极接触点，该半导体芯片由掺杂硅衬底制成并且封闭于壳体1中，而其基极、集电极和发射极接触点通过引线接合连接9连接到壳体的相应的基极、集电极和发射极端子上。壳体通常为表面可安装的壳体，即所谓的SOT或SMD壳体，其优选地由带有塑料封装的引线框架组成。
尽管市场上可买到各种各样的分立式晶体管，但它们全部共有一种共同的构造：有源芯片的硅衬底用作集电极接触点。例如为n型掺杂的硅衬底利用其位于芯片下侧的集电极接触点(金属化部)连接至壳体的集电极端子上，或者设置于其上并附连于其上。连至半导体的发射极和基极接触点以非常精细的几何形状(＜1μm)设置于芯片的上侧上。如图1和2中所示，发射极和基极接触点在半导体芯片的表面处以掺杂的发射极和基极区上的内连接金属化部的形式提供。这些发射极和基极接触点在各情况下通过接合引线连接至载体的相应发射极或基极接触点上。
这种半导体芯片通常内置于SMD(表面安装的器件)壳体中，其上提供有半导体芯片的壳体接触点限定了壳体的集电极接触点。发射极和基极通过接合引线接合至壳体的剩余接触点或相邻半导体芯片。芯片以及接合引线由壳体保护。
图4示意性地示出了根据本发明的半导体元件2的这个实施例的侧视图，所述半导体元件2位于衬底例如电路板3上SMD壳体1中。半导体器件2附连至引线框架4。引线连接9利用接合引线92设置于器件2上的内连接金属化部和引线框架的连接插脚4上的外连接金属化部之间。在这种情况下，半导体芯片上的接合引线的电流连接部分通过球接合91连接而接合引线的另一电流连接部分通过引线框架的连接插脚4的接触表面上的楔接合连接。
连接金属化部所用的接触表面由沿着芯片表面延伸的绝缘涂层中的接触窗口限定。
这种绝缘涂层的材料可以使用例如一层热氧化物、荧光体玻璃、LTO或TEOS，或者可以施加这些材料的多层涂层，其中接触孔使用干或湿化学蚀刻进行蚀刻。
根据本发明，内连接金属化部包括带有开放栅格结构的增强系统。
增强系统由设置于开放栅格结构中的涂层形成。
涂层可优选地由众所周知的用于制造半导体器件所用的绝缘和钝化层的电介质材料形成。
根据半导体材料的良好粘合剂性能的需要以及需要的电介质性能进行选择用于绝缘涂层的材料以便实现金属化部的相互绝缘。对于材料，使用半导体材料与氧和/或氮的化合物，例如热氧化物、荧光体玻璃、LTO、TEOS或这些材料的多层涂层。还可以适当地使用铝与氧和/或氮的化合物，如铝一又二分之一氧化物。该层另外还可由硅特别是半导体芯片的硅材料组成。
特别优选的是形成的增强系统具有热氧化物4的开放栅格结构。
在制造过程期间，热氧化物在不同的工序中自动地例如用作掩模氧化物、表面保护、扩散源、中间体氧化物以及在离子注入期间用作封盖层。
热氧化物通过半导体表面的转换形成，其制造对半导体表面上的杂质不敏感并且显示出优良的结合强度。
开放栅格结构由热氧化物形成或由绝缘涂层所用的另一种材料形成，呈凸台或支承点的形式，将各个栅格开口彼此分离。栅格开口可具体实现为例如凹槽，特别是平行等距条纹的开放结构，而且可具体实现为蜿曲或封闭带状结构，优选地作为圆环或矩形环，或各个支承点所用的孔身结构。
栅格开口可替代地为管状，带有圆形或优选地为多边形特别是矩形的基极。
图3中示出了开放栅格结构的多个实施例。
增强系统可具有适合于吸收在金属化部处起始的应力的任何高度。这意味着其必须足够厚以便对于应力具有足够大的阻尼效应，从而使得这些应力不会损害半导体表面。增强系统优选地具有超过大约500nm的厚度。此外，增强系统的厚度不应使其产生脆性。厚度优选地位于10nm和10μm之间的范围。
层的高度h与栅格凸台的宽度b的比值优选地位于1∶25至1∶50的范围内。栅格凸台的面积和栅格开口的面积之间的比值优选地处于30至95％的范围内，非常优选地处于＞50％的范围内，更优选地处于＞70％的范围内。
增强系统可完全地设置于半导体的表面上方。增强系统可替代地完全地或部分地设置于半导体的表面下方。
金属化部被施加于半导体芯片的由于增强系统的原因剩余的接触面积上。因此，金属化部和半导体芯片之间的连接不会延伸贯穿半导体芯片的表面，因此减小了包括芯片表面、金属化部、增强系统和接合引线的电流连接部分的接合的刚性。增强系统使得接触表面上的接合引线的机械反作用减小。发生于接触区域中的拉伸应力不再会累加至超过材料强度并自身以裂纹的形式显示的临界值。
金属化部可由任何适当的导电性材料如金属形成。例如，可以使用铝、铜或许多其它合金。
在根据本发明的半导体元件中，内连接金属化部通过接合引线回路9连接到相应外连接金属化部。
引线接合的半导体芯片此外还封装于壳体中，与使用的集成化技术和预期的应用场合无关。
带有包括开放栅格结构的增强系统的半导体元件可以利用以下工序制造：
将掺杂硅半导体衬底掺杂于半导体器件中并构造，
在这个过程的范围内，在退火过程中形成的氧化物利用适合的蚀刻掩模作为栅格结构提供于接触窗口中，
施加并构造金属化部，
在掺杂硅衬底的上部区域中制造完全表面绝缘层，
将半导体芯片芯片接合于载体上，
在半导体芯片和载体之间形成引线接合连接，
封装。
另外，带有包括开放栅格结构的增强系统的半导体元件还可以利用以下工序制造：
将掺杂硅半导体衬底掺杂于半导体器件中并构造，
在掺杂硅衬底的上部区域中制造完全表面绝缘层，
使用开放栅格结构产生掩模穿过绝缘层进行选择蚀刻以便形成带有增强结构的接触窗口，
提供并构造金属化部，
将半导体芯片芯片接合于载体上，
在半导体芯片和载体之间形成引线接合连接，
封装。
为了在平面技术中制造平面双极晶体管，通过在多个连续步骤中从表面专门离子注入掺杂质，而在半导体衬底中形成需要的p-n结。对于起始材料，一般使用200至625μm厚的n或p传导性硅单晶片，其涂有高电阻的、不透掺杂质的二氧化硅或氮化硅的保护层。“窗口”利用蚀刻形成于本保护层中，受体或给体物质穿过该“窗口”注入，例如，受体或给体物质在n传导性硅衬底的情况下为硼，在p传导性硅衬底的情况下为磷，分别向大块材料产生具有p-n结的p和n型传导性区域。这些区域形成平面晶体管的基极区。窗口被另一个SiO2层部分地封闭，而相反的或增大的掺杂质被通过保持自由的或重新蚀刻的开口注入，这些掺杂质导致传导类型颠倒，并且其产生n传导性或p传导性发射极区以及位于每个基极区和发射极区之间的p-n结，或者其构成接触点的高度掺杂的连接区域。
每个注入步骤包括实际的植入和随后的高温下扩散过程，其影响掺杂区域的深度和表面浓度。
为了形成带有增强系统的连接区域，沉积或者通过退火形成隔离层。替代地，在前面的制造步骤中形成的层可用于这个用途。
优选地，接触窗口-绝缘层通过硅的热氧化来制造。
例如，施加热二氧化硅层的方法包括在处于900和1100℃之间的范围中的温度下在氧或者氧-水蒸汽环境中热生长的过程。在这个过程中，氧作为反应气体在热硅表面上方流动。氧与硅结合以便形成二氧化硅，导致在硅表面处形成无定形的、玻璃状层。热氧化过程可以通过加入水蒸汽而分成干法和湿法过程。如果要避免高工作温度，或者为了获得更高的层厚，优选湿式氧化法。
接触窗口-绝缘层按照已知方式利用惯常的光刻工艺构造，并且所述构造过程可以使用掩模进行以便利用蚀刻露出接触窗口。
为了这个目的，光敏薄膜被旋转涂敷于器件的上侧上。所述膜使用电子束光刻、激光束干涉或者紫外射线等等曝光，此后显出理想结构。在所述显现步骤之后，保留的掩模结构保护器件的材料的区域以防随后的蚀刻或铣削过程(例如离子铣削、活性离子蚀刻、湿化学蚀刻、电化蚀刻、光化蚀刻、化学支持的离子束蚀刻或者其组合，等等)，以便将适当的结构转印至器件的材料，此后除去掩模层。
光敏掩模膜可以随后利用溶剂或者氧等离子除去。
凸台或者凹槽的外形结构应当优选地选择成尽可能高以便非常有益。在来自退火过程的栅格结构的情况下，由热氧化物制成的结构的高度通常处于大约100nm至300nm的范围内。可以利用热氧化物获得较大层厚。
在结构尺寸或者直径范围通常从50至几百微米的实际接触窗口内，如此形成于发射极和基极区中的接触窗口具有的典型结构尺寸或者直径处于几分之一微米直到几微米的范围内。
然而，这些尺寸并非必须如此，而是只是举例选择。
利用上文指出的工序，就实现了以下这点，即接触窗口的底部，也就是由于接触窗口而露出的单晶硅衬底的表面，散布有增强系统。
接触窗口中的露出的增强系统的区域用来形成金属基极和发射极接触点所用的金属化部。
已经预先清洁过的这个表面然后例如通过蒸发(电子束蒸发)或喷镀而提供以连续的金属化部。这些提供金属化部的方法为现有技术并且本身已知。用于第一金属化部的材料优选地为铝、铜或银，或者这些金属的合金。为了预防所述材料与下面的半导体材料之间的反应，并且为了改进金属和半导体材料之间的粘合作用并减小其间的过渡电阻值，可以将由钛、铬、钼、钨、铂、钯、银、镍或者这些金属与硅、氮或碳的化合物构成的一个或多个薄膜直接施加于原始的半导体片上。金属化部的层厚处于直至20μm的范围内。
随后，构造内连接金属化部以便使得在继之以蚀刻的惯用光学处理中，形成接触点，其总高度对于发射极部分和基极部分而言是相同的。在接触点之间延伸的区域的除去可以通过湿化学蚀刻或干法蚀刻进行。
金属化部实际上完成了半导体器件的制造。已经可以进行器件的试验。然而，由于片必须被锯开，并且将如此获得的各个芯片胶粘或焊接于壳体中并为其提供合成树脂封装，就需要利用磨回过程产生所需片厚，制备后侧以便包装并保护敏感电路和特别是金属化部免受损伤。为了实现这点，将称为钝化层的保护层施加于片上。
除了在包装，即所谓的组装所用的最终处理步骤期间保护电路之外，这种钝化还用于提供长期保护免受环境影响。特别是，在用于工业或汽车应用场合的电路的情况下，这点很需要，因为合成树脂封装不能完全阻止水分或有害气体渗透。在这些应用领域中，双层氧化物和氮化物证明结果良好，氮化物特别致密并且氧化物用作缓冲以防来自氮化物的高机械应力。
钝化层可由任何适当的绝缘材料制造，如二氧化硅(SiO2)。
这种钝化层在接合垫盘的区域内必须使用最后的光刻掩模过程和蚀刻过程再次除去，以便在接触点的位置处露出位于芯片表面上的保护涂层下方的半导体元件的电接触点。
在平面工艺结束时，半导体片经受锯切过程，其中存在形式各不相同的元件晶体(芯片)，在这些元件晶体(芯片)中装有相应的半导体器件(分立器件或集成电路)。
最后，例如，只要芯片通过胶粘或焊接连接至引线框架即具有连接插脚或引线的载体，半导体元件就准备好。
将半导体芯片附连于载体上通过胶粘或形成合金(晶片接合)来进行，载体例如为十字叉状载体、引线框架或陶瓷载体，其以后形成为壳体的一部分；在通过晶片接合进行附连的情况下，这个过程被称作低共熔接合。
随后，通过将起自半导体器件的接触窗口的金属导体轨迹加宽至可以附连延伸到外部的连接线的接触点或接合点中，就形成外部电触点。
芯片的连接区域(垫盘)随后被利用引线接合连接至相关金属引线框架区域。
发射极和基极区的接触利用引线接合过程进行。
在钉头或球引线接合过程的情况下，电容器放电引起引线的端部熔化于球中，该球被压于接合接触区域上。在这个位置处，球和金属被焊接在一起，再次被抬起并引导至引线框架的连接插脚上的第二接触区。在这个位置处，其经受压力并被剪切，产生接合连接。
除了引线在楔作用下沿引线方向变形之外，楔引线接合过程类似于球接合过程。
在所述引线接合过程之后，利用绝缘压模材料或陶瓷盖将芯片与接合引线和引线框架的毗邻区一起封装起来，以便形成所谓的“包装”，引线框架的连接插脚沿横向伸出该包装之外。
参考数字表
1壳体
2半导体芯片
3衬底
4连接插脚
5基极
6发射极
7金属化部
8增强系统
9接合垫盘
91冶金接触点
92接合引线

Claims (5)

1.一种半导体元件，包括由掺杂硅衬底制成的半导体芯片(2)，所述芯片掺入半导体器件中并且进行构造，并且包括位于接触窗口中的内连接金属化部(7)，并且所述半导体芯片的所述内连接金属化部通过引线接合连接(9)连接到相应外连接金属化部上，其特征在于，内连接金属化部包括具有位于掺杂硅衬底上的开放栅格结构的增强系统(8)。
2.根据权利要求1所述的半导体元件，其特征在于，具有开放栅格结构的增强系统由隔离涂层形成。
3.根据权利要求1所述的半导体元件，其特征在于，形成的栅格结构为开放的凹槽结构。
4.根据权利要求1所述的半导体元件，其特征在于，形成的栅格结构可为开放的管状结构。
5.根据权利要求1所述的半导体元件，其特征在于，由热氧化物构成的栅格结构的面积大于接触窗口的面积的50％。
CNA2004800369010A 2003-12-10 2004-12-01 带有增强内连接金属化部的引线接合的半导体元件 Pending CN1890809A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03104621 2003-12-10
EP03104621.2 2003-12-10

Publications (1)

Publication Number Publication Date
CN1890809A true CN1890809A (zh) 2007-01-03

Family

ID=34673608

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800369010A Pending CN1890809A (zh) 2003-12-10 2004-12-01 带有增强内连接金属化部的引线接合的半导体元件

Country Status (5)

Country Link
US (1) US8013452B2 (zh)
EP (1) EP1695384A2 (zh)
JP (1) JP2007514312A (zh)
CN (1) CN1890809A (zh)
WO (1) WO2005057654A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517915A (zh) * 2013-10-01 2015-04-15 英飞凌科技股份有限公司 布局及其制造方法
US9966277B2 (en) 2013-10-01 2018-05-08 Infineon Technologies Ag Arrangement and method for manufacturing the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010001788A1 (de) 2010-02-10 2011-08-11 Forschungsverbund Berlin e.V., 12489 Skalierbarer Aufbau für laterale Halbleiterbauelemente mit hoher Stromtragfähigkeit
US8866708B2 (en) * 2011-01-21 2014-10-21 Peter Sui Lun Fong Light emitting diode switch device and array
US8759153B2 (en) * 2011-09-06 2014-06-24 Infineon Technologies Ag Method for making a sensor device using a graphene layer
US11248769B2 (en) 2019-04-10 2022-02-15 Peter Sui Lun Fong Optic for touch-sensitive light emitting diode switch

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
US6143396A (en) 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6448650B1 (en) * 1998-05-18 2002-09-10 Texas Instruments Incorporated Fine pitch system and method for reinforcing bond pads in semiconductor devices
JP3431517B2 (ja) * 1998-10-13 2003-07-28 松下電器産業株式会社 半導体装置
GB0018643D0 (en) * 2000-07-31 2000-09-13 Koninkl Philips Electronics Nv Semiconductor devices
KR100416614B1 (ko) * 2002-03-20 2004-02-05 삼성전자주식회사 본딩패드 하부구조를 보강하기 위한 반도체 소자 및 그제조방법
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517915A (zh) * 2013-10-01 2015-04-15 英飞凌科技股份有限公司 布局及其制造方法
US9966277B2 (en) 2013-10-01 2018-05-08 Infineon Technologies Ag Arrangement and method for manufacturing the same

Also Published As

Publication number Publication date
US20080230920A1 (en) 2008-09-25
EP1695384A2 (en) 2006-08-30
WO2005057654A3 (en) 2005-08-04
US8013452B2 (en) 2011-09-06
WO2005057654A2 (en) 2005-06-23
JP2007514312A (ja) 2007-05-31

Similar Documents

Publication Publication Date Title
CN100392807C (zh) 半导体装置的制造方法
TWI395277B (zh) 晶圓水準的晶片級封裝
JP4815905B2 (ja) 半導体装置およびその製造方法
JP5621334B2 (ja) 半導体装置および半導体装置の製造方法
EP1906452B1 (en) Semiconductor device
CN1241021C (zh) 加速度传感器及其制造方法
CN101060088A (zh) 半导体封装结构及其制造方法
CN1841717A (zh) 半导体装置及其制造方法
CN1249536A (zh) 半导体器件
JP2010103300A (ja) 半導体装置及びその製造方法
CN1890789A (zh) 封装元件的工艺和封装的元件
US8955219B2 (en) Method for fabricating a bond
CN107146813A (zh) 半导体装置
CN1213487C (zh) 半导体组件及其制造方法
JP4759791B2 (ja) 光半導体素子とその製造方法
CN1276090A (zh) 半导体装置及其制造方法
US8536701B2 (en) Electronic device packaging structure
CN1890809A (zh) 带有增强内连接金属化部的引线接合的半导体元件
JP3432708B2 (ja) 半導体装置と半導体モジュール
JP6736902B2 (ja) 半導体装置の製造方法
JP2015109292A (ja) 半導体モジュール
CN1750394A (zh) 电子零件、电路基板、电子仪器和电子零件的制造方法
JP2009117755A (ja) 半導体装置
TWI489601B (zh) 電子元件封裝結構
US20100163105A1 (en) Solar cell package type with surface mount technology structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20090206

Address after: Holland Ian Deho Finn

Applicant after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Applicant before: Koninklijke Philips Electronics N.V.

ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20090206

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20070103