CN1249536A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1249536A
CN1249536A CN99111981A CN99111981A CN1249536A CN 1249536 A CN1249536 A CN 1249536A CN 99111981 A CN99111981 A CN 99111981A CN 99111981 A CN99111981 A CN 99111981A CN 1249536 A CN1249536 A CN 1249536A
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China
Prior art keywords
lead
heat radiation
radiation plate
semiconductor chip
semiconductor device
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CN99111981A
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English (en)
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CN1227734C (zh
Inventor
伊藤富士夫
田中宏明
铃木博通
户井田德次
今野贵史
坪崎邦宏
田中茂树
铃木一成
龟冈昭彦
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Hitachi Renesas Semiconductor Inc
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Renesas Semiconductor Inc
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
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Publication of CN1249536A publication Critical patent/CN1249536A/zh
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Publication of CN1227734C publication Critical patent/CN1227734C/zh
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Abstract

半导体器件中,内引线的尖端固定于热辐射板,可使热辐射板得到支持并免去悬置引线。与半导体芯片连接的内引线的尖端具有引线间距p、引线宽度w和引线厚度t,其间的关系为w< t和p≤1.2t。热辐射板具有在径向方向上形成有从热辐射板上的半导体芯片安装区向内引线辐射热量的传热通路的缝隙。采用模塑件密封的半导体器件中,半导体芯片固定于热辐射板上,内引线尖端厚度t’比固定于热辐射板上的内引线其他部分的厚度t薄。

Description

半导体器件
本发明涉及具有引线框的半导体器件。更具体讲,本发明涉及适用于具有由多个引线及热辐射板构成的引线框的半导体器件的技术。
大规模集成电路和半导体器件的电路集成度在结合前所未有的更高级功能和更复杂电路的同时日益提高。功能的提高要求为每个半导体器件提供大量外部端子。而这又牵涉增加半导体芯片上配置的焊盘电极的数量以及引线即半导体器件外部端子的数量。典型的逻辑半导体器件可具有成百的外部端子。所谓的四方扁平封装(QFP)式的半导体器件是一族其中每一个都具有大量外部端子的半导体器件,一般是安装在衬底的一面并称为表面安装半导体器件。四方扁平封装半导体器件适于容纳大量引线是因为封入半导体芯片的封装的四面的每一面都带有多个引线。当安装到衬底上时,这种半导体器件允许有效地利用其周围的空间。
用来装配此种四方扁平封装式半导体器件的引线框在下面的文献中说明:“VLSI Packaging Techniques(Vol.1)”,Nikkei BP(日本)1993年5月31日出版,PP.155-164。特别是在PP.157和159示出这种框架的具体式样。
半导体芯片的精细结构包括数量日益增加的元件,其中每个元件都以前所未有的高速运行。这引起半导体芯片的发热量增加。在“VLSI Packaging Techniques(Vol.2)”,PP.200-203中说明了可以避免这一问题的带有扩展散热器的半导体器件。这种半导体器件为其半导体芯片配设扩展散热器装置以促进器件的热耗散。
为容纳大量引线,引线框需要缩小其引线与引线之间的间隔(即引线间距)及减小引线宽度。
半导体芯片还包括由于半导体器件功能的增加所必需的大量焊盘电极。同时,焊盘电极之间的间隔(即焊盘间距)在这些年中已经减小。一般不同半导体芯片具有不同的焊盘间距,同时需要在一片晶片上得到尽可能多的芯片牵涉到确定尽可能最小的芯片尺寸。这一趋势又要求焊盘电极之间的间距尽可能地最小。
假如焊盘间距缩小并处在与此相关的限制之下,则利用金丝或其他类似材料的细丝将多个引线键合到相应的焊盘电极的过程易于触发邻接细丝之间的短路数量的增加。
在细丝键合之后的树脂模塑中间引线机械强度的下降或细丝间隔的缩小会使细丝由于模塑树脂的流动性而变形。这种称为细丝流变的变形可引起细丝的短路。
另外,在四方扁平封装中,放置引线的区域越靠近位于中心处的半导体芯片就越窄小。引线的厚度和间距受到来源于引线制造精度限制的限制。说得更具体些,与半导体芯片上的焊盘间距相比引线间距不可能做得足够地小。随着半导体芯片的外部尺寸的缩小,就越来越难于使引线尖端靠近芯片。在这种情况下,当需要键合的引线尖端距离焊盘电极较远时就必须将用来键合焊盘与引线的细丝延长。与过去相比,引线延长就多半会引起更多的短路或导致更多的细丝流变。
如今实际的焊盘间距已减小到大约80μm,预期将来所要求的间距将达到60至45μm。当芯片进一步缩小时,键合丝要相应地延长。现在,为保证稳定键合必须保持细丝的长度最大为5或6mm。这就要求进一步减小引线尖端的间距以避免细丝延长。
图1示出本发明的发明人对细丝键合所做的模拟试验结果。对具有不同焊盘间距的256个引脚的半导体芯片上的内引线尖端间距与用来减小稳定键合的细丝长度之间的关联进行了模拟。模拟的结果揭示,为保证稳定键合,对于60μm的焊盘间距需要限制引线尖端间距最大为180μm。
这种引线的微细制造必然导致其机械强度的降低。甚至极其有限大小的外力也会使纤细的引线结构变形。变形的引线会触发短路。
上述问题的通常解决办法是采用防止引线变形的绝缘带来固定内引线。图2为通常结构的绝缘带固定引线框的平面图。图3为采用图2的引线框制造的树脂密封半导体器件剖视图。
作为示例,此引线框由铜合金制作。半导体芯片1(以虚线代表)固定于载片板(tab)2上。环绕安装好的半导体芯片1的整个周边配置有多个引线3。引线3有两类:内引线4和外引线5。内引线4的尖端包围着半导体芯片1。
引线3与挡条6或连杆8作成一个整体而构成引线框的框架。内引线4和外引线5分别在挡条6的内外。载片板2由载片板悬置引线7支持,该载片板悬挂引线7成十字形穿过内引线4配置。内引线4和载片板悬挂引线7固定于矩形绝缘带9。
在半导体器件采用如上所述的引线框的场合,半导体芯片1借助树脂或银膏固定到载片板2上,而内引线4提供键合丝11与芯片1的焊盘电极10相连。在键合之后,借助比如由环氧树脂制作的模塑件12将半导体芯片1、载片板2、内引线4及键合丝11模塑成形。挡条6和连杆8被切掉而互相成为电绝缘。之后,外引线5从模塑件12中伸出并形成比如图3所示的鸥翼状。至此完成半导体器件的制作。
采用如图2及图3所示的这种绝缘带固定的引线框时,内引线4的中间部分由绝缘带9固定以容许柔性使用此引线框。换言之,绝缘带9的位置离开内引线4的尖端。这是一种固定与细丝键合的内引线尖端的无效且不稳定的结构。
另外,某些新近开发的半导体器件由于其功能的增加和性能的提高而使半导体芯片的发热严重。这些器件的半导体芯片装备有热辐射板,如扩展散热器,来促进热耗散。
图4为用于配置有扩展散热器的四方扁平封装(下文称之为HQFP)的引线框的平面图,其中由本发明人所设计的铜箔贴附于半导体芯片用作热辐射板。这种设置方式迄今为止尚未公开过。图5为利用图4的引线框制造的半导体器件的剖视图。
与此前所讨论的引线框及半导体器件相反,这种半导体芯片1(以虚线代表)上固定有热辐射板13。
这种HQFP型半导体器件的构成包括模塑件12和热辐射板13之间的大量接触。因为树脂(即模塑件12)和金属(热辐射板13)之间的粘合强度很薄弱,在模塑件12和热辐射板13之间的界面中所吸收的湿气在回流加热时会蒸发并膨胀,从而引起封装开裂。这种回流加热发生在将表面安装半导体器件安装到衬底上的过程中。图4的半导体器件对付这种回流问题的办法是在热辐射板13的中部设置一个圆孔,这一圆孔可使模塑件12与半导体芯片1接触。然而,这种结构还是不足以克服这一问题。
因此,本发明的一个目的就是提供一种稳定具有大量引线的半导体器件的键合技术。
本发明的另一目的是提供一种防止配置有热辐射板的半导体器件的封装开裂的技术。
在本说明书中公开的本发明的典型技术将在下面简要介绍。
在具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件中,半导体芯片与具有引线宽度为w和引线厚度为t的内引线的尖端连接,其中引线宽度w小于引线厚度t(w<t),并且其中至少内引线的尖端固定于热辐射板上。
在具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件中,半导体芯片与具有引线宽度为w和引线厚度为t的内引线的尖端连接,其中引线宽度w小于引线厚度t,并且其中至少内引线的尖端固定于热辐射板上以支持热辐射板。这种结构可免去通常用来支持热辐射板的悬置引线的需要。
在具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件中,半导体芯片与具有引线间距为p、引线宽度为w和引线厚度为t的内引线的尖端连接,其中引线间距p等于或小于引线厚度t的1.2倍(p≤1.2t),并且其中至少内引线的尖端固定于热辐射板上。
在具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件中,在热辐射板上在径向方向上形成有从热辐射板上的半导体芯片安装区向内引线辐射热量的传热通路的缝隙。
在具有固定于热辐射板上的半导体芯片的半导体器件中,其中内引线尖端(尖端厚度为t′)比内引线其他部分薄(引线厚度为t),并且其中至少内引线的尖端固定于热辐射板上。
在制造具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件的方法中,该方法的构成包括的步骤为:将半导体芯片与具有引线间距为p、引线宽度为w和引线厚度为t的内引线的尖端连接,其中引线宽度w小于引线厚度t(w<t),并且其中引线间距p等于或小于引线厚度t的1.2倍(p≤1.2t);至少将内引线的尖端固定于热辐射板上;并且将内引线连接于半导体芯片的焊盘电极。
在制造具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件的方法中,该方法的构成包括的步骤为:在热辐射板上在径向方向上形成从热辐射板上的半导体芯片安装区向内引线辐射热量的传热通路的缝隙;并且在树脂封装过程中使密封剂穿过热辐射板上的缝隙形成密封。
在制造具有固定于热辐射板上的半导体芯片并且采用密封剂密封的半导体器件的方法中,该方法的构成包括的步骤为:将半导体芯片固定于引线框上的热辐射板上,其中内引线尖端(尖端厚度为t′)比内引线其他部分薄(引线厚度为t);并且将内引线与半导体芯片的焊盘电极连接,其中至少内引线的尖端固定于热辐射板上。
在其构成包括多个引线和一个具有用来固定半导体芯片的半导体芯片安装区的热辐射板的引线框中,半导体芯片与引线之中的内引线的尖端连接,内引线尖端具有的引线间距为p、引线宽度为w和引线厚度为t,其中引线宽度w小于引线厚度t(w<t),其中引线间距p等于或小于引线厚度t的1.2倍(p≤1.2t);并且其中至少将内引线的尖端固定于热辐射板上。
在其构成包括多个引线和一个具有用来固定半导体芯片的半导体芯片安装区的热辐射板的引线框中,在热辐射板上在径向方向上形成有从热辐射板上的半导体芯片安装区向内引线辐射热量的传热通路的缝隙。
在其构成包括多个引线和一个具有用来固定半导体芯片的半导体芯片安装区的热辐射板的引线框中,其中引线之中的内引线尖端(尖端厚度为t′)比内引线其他部分为薄(引线厚度为t),并且其中至少内引线的尖端固定于热辐射板上。
根据本发明,所提供的半导体器件的构成包括:热辐射板,它包含主表面及与主表面相对的背面,并且此热辐射板具有从主表面穿透到背面的贯穿型缝隙;半导体芯片,它具有设置于主平面上的半导体元件和多个电极,此半导体芯片固定于热辐射板上的主表面;多个引线,各引线由内引线和外引线构成,内引线尖端固定于所述热辐射板,内引线尖端与半导体芯片的电极电连接;以及密封热辐射板、半导体芯片和内引线的模塑件;其中贯穿型缝隙是在径向方向上以从热辐射板的半导体芯片安装区的外部向着由内引线的尖端包围的区域辐射的方式设置。
在上述半导体器件中,热辐射板可以是矩形形状,而贯穿型缝隙可作成为向着热辐射板的四个角部延伸的形状。
另外,根据本发明,所提供的半导体器件的构成包括:热辐射板,它包含主表面及与主表面相对的背面,并且此热辐射板具有从主表面穿透到背面的贯穿型缝隙;半导体芯片,它具有设置于主平面上的半导体元件和多个电极,此半导体芯片固定于热辐射板上的主表面;多个引线,各引线由内引线和外引线构成,内引线尖端与半导体芯片的电极电连接;以及密封热辐射板、半导体芯片和内引线的模塑件;其中贯穿型缝隙是在径向方向上以向着热辐射板上的内引线包围的区域辐射的方式设置。
在上述半导体器件中,贯穿型缝隙可制作成为使半导体芯片的背面有一部分是暴露的。
在上述半导体器件中,热辐射板可以是矩形形状,而贯穿型缝隙可作成为向着热辐射板的四个角部延伸的形状。
如上所述及根据本发明,内引线的尖端固定于热辐射板。这种结构可免去安装用来支持承载半导体芯片的载片板的载片板悬置引线的需要。过去通常分配给载片板悬置引线的面积可用于容纳内引线。假如引线间距不变,这种结构可允许内引线尖端配置于比过去更靠近半导体芯片的位置。
本发明的内引线尖端固定于热辐射板上的结构可稳定键合和防止内引线变形。
根据本发明,热辐射板具有在径向方向上制作的形成传热通路的缝隙。这种结构可加强对回流问题的保护,并且同时可减小热辐射特性的降低。
还是根据本发明,内引线尖端比过去薄以改善尖端制作的精度。将内引线尖端固定于热辐射板上可强化对尖端变形的抵抗。
本发明的这些以及其他的目的、特点和优点在参考附图并阅读下面的描述将会得到清楚的了解。
图1为示出关于细丝键合的模拟结果的曲线图;
图2为通常结构的绝缘带固定引线框的平面图;
图3为采用图2的引线框制造的树脂密封半导体器件剖视图。
图4为用于配置有扩展散热器的四方扁平封装(HQFP)的引线框的平面图;
图5为利用图4的引线框制造的树脂密封半导体器件的剖视图;
图6为用作本发明的实施例引线框的平面图;
图7为利用图6的引线框制造的树脂密封半导体器件的剖视图,以图6的A-A′线剖开;
图8A和8B为图6中引线框上的内引线尖端的剖视图;
图9A和9B为图2中引线框上的内引线尖端的剖视图;
图10为不同类型缝隙的热阻的比较曲线图;
图11为示出半导体芯片的内引线和焊盘电极是如何配置的平面图和剖视图的结合图;
图12为示出半导体芯片的内引线和焊盘电极是如何配置的平面图和剖视图的结合图;
图13为示出半导体芯片的内引线和焊盘电极是如何配置的平面图和剖视图的另一结合图;
图14为示出半导体芯片的内引线和焊盘电极是如何配置的平面图和剖视图的另一结合图;
图15A为热辐射板中的缝隙形状不同的的引线框的平面图;
图15B为利用图15A的引线框制造的树脂密封半导体器件的剖视图,以图15A的B-B′线剖开;
图16为热辐射板中的缝隙形状不同的另一引线框的平面图;
图17为热辐射板中的缝隙形状不同的另一引线框的平面图;
图18为热辐射板中的缝隙形状不同的另一引线框的平面图;
图19为热辐射板中的缝隙形状不同的另一引线框的平面图;并且
图20为本实施例的变例的剖视图。
下面参考附图描述本发明的优选实施例。在所有的附图中同样的标号代表同样或相应的部件,并且其描述重复之处不赘述。
(第一实施例)
图6为用作本发明的第一实施例的HQFP类型半导体器件的引线框的平面图。图7为利用图6的引线框制造的树脂密封半导体器件的剖视图,以图6的A-A′线剖开;图8A和8B为图6中引线框上的内引线尖端的剖视图。图8A示出通过刻蚀形成的引线框,而图8B示出通过冲压形成的引线框。
引线框例如由Fe-Ni合金或铜合金制作。半导体芯片1(以虚线代表)的整个周边为多个引线3之中的内引线4的尖端所环绕。引线3与挡条6或连杆8作成一个整体而构成引线框的框架。挡条6的内外部分分别构成内引线4和外引线5。半导体芯片1利用聚酰亚胺型粘合剂14和管芯键合剂17键合固定。内引线4利用粘合剂14固定于热辐射板13。
在采用上述引线框的半导体器件中,半导体芯片1是利用树脂或银膏17固定于热辐射板13上,而内引线4利用键合丝11与半导体芯片1的焊盘电极10连接。在键合之后,半导体芯片1、热辐射板13、内引线4和键合丝11例如由环氧树脂制作的模塑件12密封。挡条6和连杆8被切掉以使引线3互相电绝缘。之后,将从模塑件12延伸的外引线5例如作成鸥翼状或其他适合的形状。至此完成了半导体芯片21的制造。
在刻蚀的引线框上,引线的顶部宽度比引线底部宽度稍大,因此引线的顶部将足够宽可以适应键合,而同时减小了引线宽度w。为制作出这种剖面结构,例如需要改变引线顶部和底部的刻蚀条件。
在引线间距p比较窄的引线尖端上引线厚度t小于引线宽度w。这种引线结构易于在键合时焊丝固定不牢而遭受横向变形。所以在内引线的间距为180μm,即1.2倍于引线厚度或更小时,内引线4最好是固定于热辐射板13之上。
在内引线4固定于热辐射板13上时,引线尖端在细丝键合过程中保持固定。这可以保证细丝键合的可靠性。其好处可通过与示出图2引线框的内引线4的图9A和图9B的剖视图进行比较而得到确证。
现今引线框大约为150μm厚,大约为能够抵抗外引线5的可能变形的最薄厚度。引线间距一般为185μm,引线宽度为100μm,而引线间隔为85μm。在将来,在具有窄引线间距的引线框架上的内引线4的尖端处的引线间距将为180μm或更小。同样可以预期引线宽度将小于引线厚度(w<t)并且内引线间距p等于或小于引线厚度t的1.2倍(p≤1.2t)。在这种场合,根据本发明,内引线4要固定于引线框的热辐射板13以便在细丝键合过程中保持引线尖端固定。这种结构可改进细丝键合的可靠性。
在本发明的引线框上,半导体芯片1固定在由内引线4固定的热辐射板13的半导体芯片安装区。在这种设置中没有通常支持用来安装承载半导体芯片的载片板的载片板悬置引线。过去通常用于载片板悬置引线的面积可利用来容纳内引线4。
在上述设置中,过去通常设置载片板悬置引线的角部也可用来容纳内引线4。假如引线间距不变,这种结构可将内引线4配置于比过去更靠近半导体芯片1的位置。而这又可以缩短在半导体芯片1安装之后需要键合的键合丝的长度。结果,细丝变形减到最小并减少了树脂封装过程中细丝之间的短路。
还可以做到在无需将内引线4的尖端互相靠近的情况下加宽引线间距或增加引线数量。
在用来安装半导体芯片1的区域一边和引线4一边之间的热辐射板13上制作有缝隙15。缝隙15容许模塑件12贯穿热辐射板13使热辐射板13和模塑件12难于分开。使用贯穿热辐射板13的模塑件12可以增加对回流问题的抵抗程度,这归功于两个原因:模塑件保持半导体芯片1的力量增加以及在热辐射板13和模塑件12之间的分离界面也因湿气成分蒸发和膨胀所引起的力分开。要安装的半导体芯片1的尺寸因对其所要求的具体功能的不同而有别。在本实施例中半导体芯片1及缝隙15的尺寸不改变。如需要安装大半导体芯片,芯片的边缘与缝隙15部分叠合,芯片由树脂12固定。
缝隙15的形状使得热辐射板13的传热通路X在径向方向上形成,如箭头X所示。比如,图中以虚线示出的用来进行参考的假设的通常垂直于传热通路X的缝隙16就会阻断沿通路X的传热。图10为不同类型缝隙的热阻的比较曲线图。在图10中缝隙15表示的本发明的缝隙及缝隙16表示的通常的缝隙设置与无缝隙设置的场合进行了比较。可以看出,本发明的缝隙设置15的热阻的增加小于其他设置并可将由热耗散引起的可能损坏降低到最小。
在采用上述的HQFP型半导体器件时,内引线4的尖端或半导体芯片的焊盘电极10可采用交替方式(错开方式)配置。这种错开的配置方式可提供更可靠的细丝键合。
通常,如图11所示(右方为平面图,左方为剖视图),内引线4的尖端或半导体芯片的焊盘电极10是在芯片1的每一边各排一行。而根据本发明,如图12所示(右方为平面图,左方为剖视图),半导体芯片1的邻接焊盘电极10可沿半导体芯片1的各边交替(交错)配置,并使细丝与引线尖端的键合高度不同。这种配置可使细丝与焊盘电极10的键合比过去更为容易。
同样,如图13所示(右方为平面图,左方为剖视图),邻接的内引线4的尖端可交错配置,并使细丝与电极的键合高度不同。另外,如图14所示(右方为平面图,左方为剖视图),邻接的内引线4的尖端以及半导体芯片1的邻接焊盘电极10都可交错配置,并使细丝与引线尖端及电极的键合高度不同。
要在热辐射板13中设置的缝隙15可设计成为如图15A至19中所示的各种形状。
在图15A和图17中所示出的形状示例中是通过加大缝隙15的面积优先考虑对回流问题的抵抗,而在图16的示例中有利于热耗散,因为缝隙15比图15A和17中的窄,从而可相应地加大热耗散的通路。图18所示的形状示例是寻求对回流问题的抵抗和较好热耗散之间的折中的方案。图16中的缝隙15的形状既足以保证充分的热耗散,也可以改进对回流问题的抵抗。图15A和图17中的缝隙形状类似但取向不同。在图15A的形状中,模塑件12通过固定半导体芯片1的四角,即通过采用树脂固定芯片的四角,可提供对回流问题的较高的抵抗。在图17的形状中,在半导体芯片1和热辐射板13之间展宽的接触区可保证更好的热耗散特性。因此,可以根据对半导体器件的具体要求而选择合适的缝隙形状。图15B为采用图15A的引线框而制造的半导体器件的剖视图,以图15A的B-B′线剖开。在图15B中,在图7中已示出的部件采用同一标号,并且其细节不详述。半导体芯片1背面的某些部分不与热辐射板13重叠;这些部分直接由密封树脂12密封。
图19中的形状示例的缝隙15与图15A中的缝隙15的形状相同。差别只在于图19的内引线4的尖端是交错配置以使细丝键合更容易。该种内引线4的配置方式也可用于图16至图18的具有不同形状缝隙的其他示例中。这一点对半导体芯片1的焊盘电极10也适用。比如,其焊盘电极10具有如图12所示的交错配置方式的半导体芯片1可应用于图15A至19的引线框。
图20示出本实施例的变例图,其中内引线的尖端厚度t′大于引线3的其他部分的厚度t。这种引线厚度的局部差异例如可通过局部刻蚀获得。在制作引线时,其厚度为精度的重要因素。就是说引线制作的准确度可通过将内引线4的尖端制作得比从前(即考虑精度的场合)薄而得到保证;其余的引线部分可制作得足够厚以保证其坚固性。当内引线4的尖端为准确度而减薄时,重要的一点是要将引线固定于热辐射板13上以防止其变形。
尽管上述描述包含很多具体情况,但这些都不应解释为对本发明范围的限制,而只是为本发明当前的优选实施例提供示例而已。应当理解,在不脱离本发明的精神和范围的条件下可对本发明进行改变和修改。
比如,尽管上述实施例中示出的固定引线的热辐射板为矩形,这并不构成对本发明的限制。热辐射板也可以是圆形的。这种圆形的热辐射板具有在树脂模塑过程中使树脂流动平滑的优点,这可以减小内部发生空隙的机会。
上述实施例的热辐射板上可设置接地的接地区。这种设置使引线框可随时与地连接,这可进一步扩大本发明的半导体器件的应用范围。
无需在热辐射板上只安装一片半导体芯片。相反,在热辐射板上可安装多片半导体芯片。即本发明也适用于多芯片半导体器件。
尽管上述描述主要是针对构成本发明的技术背景的半导体器件,但该技术背景并不能限制本发明。本发明也可广泛应用于利用引线框安装电子元件的器件中。
上面所公开的本发明的效果可总结如下。
(1)根据本发明内引线的尖端固定于热辐射板。
(2)上述特点(1)提供稳定键合细丝的益处。
(3)上述特点(1)还可防止内引线变形。
(4)根据本发明,内引线的尖端在半导体芯片安装区的各边上以相等间隔配置。这种配置方案可提供的好处是可以将内引线设置于比从前更靠近半导体芯片安装区的位置。
(5)上述特点(4)可缩短键合细丝的长度。
(6)根据本发明,热辐射板上具有在径向方向上形成传热通路的缝隙。这种结构可增加对回流问题的保护。
(7)根据本发明,在热辐射板的径向方向上形成传热通路的缝隙可使热辐射特性的减小最小化。
(8)根据本发明,内引线尖端的厚度比从前薄,这可以改进制作尖端的精度。
(9)根据本发明,内引线尖端的厚度比从前薄并且固定于热辐射板上。这种结构可防止内引线尖端的变形。

Claims (14)

1.一种半导体器件,包括:
热辐射板,具有主表面及与主表面相反的背面,所述热辐射板具有从所述主表面穿透到所述背面的缝隙;
半导体芯片,它具有设置于主平面上的半导体元件和多个电极,所述半导体芯片固定于所述热辐射板的所述主表面;
多个引线,各引线由内引线和外引线构成,内引线尖端固定于所述热辐射板,所述内引线与所述半导体芯片的电极电连接;以及
密封所述热辐射板、所述半导体芯片和所述内引线的模塑件;
其中所述缝隙是在径向方向上以从所述热辐射板的半导体芯片安装区的外部向着由所述内引线的所述尖端包围的区域辐射的方式设置。
2.如权利要求1的半导体器件,其中所述内引线的尖端引线宽度w小于所述内引线的引线厚度t。
3.如权利要求2的半导体器件,其中所述内引线的尖端引线间距p等于或小于所述内引线的引线厚度t的1.2倍。
4.如权利要求2的半导体器件,其中固定于所述热辐射板的所述内引线的尖端引线厚度t′小于所述内引线的所述引线厚度t。
5.如权利要求1的半导体器件,其中所述缝隙的制作方式使得在所述热辐射板的径向方向上形成传热通路。
6.如权利要求1的半导体器件,其中所述电极的焊盘在所述半导体芯片上交错配置。
7.如权利要求1的半导体器件,其中所述内引线的所述尖端是交错配置的。
8.如权利要求1的半导体器件,其中所述热辐射板的形状为矩形并且所述缝隙的制作是向着所述热辐射板的四角延伸。
9.一种半导体器件,包括:
热辐射板,具有主表面及与主表面相反的背面,所述热辐射板具有从所述主表面穿透到所述背面的缝隙;
半导体芯片,它具有设置于主平面上的半导体元件和多个电极,所述半导体芯片固定于所述热辐射板上的所述主表面;
多个引线,各引线具有内引线和外引线,内引线尖端固定于所述热辐射板,所述内引线与所述半导体芯片的电极电连接;以及
密封所述热辐射板、所述半导体芯片和所述内引线的模塑件;
其中所述缝隙是在径向方向上向着由在所述热辐射板上的所述内引线包围的区域辐射的方式设置。
10.如权利要求9的半导体器件,其中所述缝隙的制作使得所述半导体芯片的所述背面部分暴露。
11.如权利要求9的半导体器件,其中所述缝隙的制作方式使得传热通路在所述热辐射板的径向方向上形成。
12.如权利要求9的半导体器件,其中所述热辐射板的形状为矩形并且所述缝隙的制作是向着所述热辐射板的四角延伸。
13.如权利要求9的半导体器件,其中所述电极的焊盘是在所述半导体芯片上交错配置的。
14.如权利要求9的半导体器件,其中所述内引线的所述尖端是交错配置的。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1328788C (zh) * 2003-06-09 2007-07-25 精工爱普生株式会社 半导体装置、半导体模块及其制法、电子设备、电子仪器
CN110265381A (zh) * 2018-03-12 2019-09-20 颀邦科技股份有限公司 半导体封装结构及其线路基板

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058735A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd リードフレーム、半導体装置及び半導体装置の製造方法
TW445608B (en) * 2000-05-19 2001-07-11 Siliconware Precision Industries Co Ltd Semiconductor package and manufacturing method thereof of lead frame without flashing
JP5183583B2 (ja) * 2000-12-28 2013-04-17 ルネサスエレクトロニクス株式会社 半導体装置
JP2002334975A (ja) * 2001-05-08 2002-11-22 Nec Corp 半導体装置の支持構造、ccd半導体装置、その製造方法、及び、ccd半導体装置用パッケージ
JP2002368156A (ja) * 2001-06-11 2002-12-20 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
CN100508175C (zh) * 2002-06-05 2009-07-01 株式会社瑞萨科技 半导体器件
JP4027185B2 (ja) 2002-08-30 2007-12-26 キヤノン株式会社 記録装置
US7132734B2 (en) * 2003-01-06 2006-11-07 Micron Technology, Inc. Microelectronic component assemblies and microelectronic component lead frame structures
US7183485B2 (en) * 2003-03-11 2007-02-27 Micron Technology, Inc. Microelectronic component assemblies having lead frames adapted to reduce package bow
AU2003261857A1 (en) * 2003-08-29 2005-03-29 Renesas Technology Corp. Semiconductor device manufacturing method
US7085699B2 (en) * 2003-12-23 2006-08-01 Texas Instruments Incorporated Wire bonding simulation
JP4307362B2 (ja) * 2004-11-10 2009-08-05 パナソニック株式会社 半導体装置、リードフレーム及びリードフレームの製造方法
US7826873B2 (en) * 2006-06-08 2010-11-02 Flextronics Ap, Llc Contactless energy transmission converter
US8609978B2 (en) * 2007-02-14 2013-12-17 Flextronics Ap, Llc Leadframe based photo voltaic electronic assembly
JP4901776B2 (ja) * 2008-02-04 2012-03-21 パナソニック株式会社 リードフレームとそれを用いた半導体装置及びその生産方法
US8450841B2 (en) * 2011-08-01 2013-05-28 Freescale Semiconductor, Inc. Bonded wire semiconductor device
JP5167516B1 (ja) 2011-11-30 2013-03-21 株式会社フジクラ 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体
JP2013149779A (ja) * 2012-01-19 2013-08-01 Semiconductor Components Industries Llc 半導体装置
US9496214B2 (en) * 2013-05-22 2016-11-15 Toyota Motor Engineering & Manufacturing North American, Inc. Power electronics devices having thermal stress reduction elements
US9257374B1 (en) * 2014-12-24 2016-02-09 Nxp B.V. Thin shrink outline package (TSOP)
JP6512229B2 (ja) * 2017-01-24 2019-05-15 トヨタ自動車株式会社 放熱シート

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133655A (en) * 1981-02-10 1982-08-18 Pioneer Electronic Corp Lead frame
US4797126A (en) * 1986-06-24 1989-01-10 Hewlett-Packard Company Adjustable length slotless female contact for connectors
USRE37690E1 (en) * 1987-02-25 2002-05-07 Hitachi, Ltd. Lead frame and semiconductor device
US5150193A (en) * 1987-05-27 1992-09-22 Hitachi, Ltd. Resin-encapsulated semiconductor device having a particular mounting structure
US5397915A (en) * 1991-02-12 1995-03-14 Matsushita Electronics Corporation Semiconductor element mounting die pad including a plurality of extending portions
KR100552353B1 (ko) * 1992-03-27 2006-06-20 가부시키가이샤 히타치초엘에스아이시스템즈 리이드프레임및그것을사용한반도체집적회로장치와그제조방법
JPH06120374A (ja) * 1992-03-31 1994-04-28 Amkor Electron Inc 半導体パッケージ構造、半導体パッケージ方法及び半導体パッケージ用放熱板
US5233222A (en) * 1992-07-27 1993-08-03 Motorola, Inc. Semiconductor device having window-frame flag with tapered edge in opening
US5701034A (en) * 1994-05-03 1997-12-23 Amkor Electronics, Inc. Packaged semiconductor die including heat sink with locking feature
JP2556294B2 (ja) * 1994-05-19 1996-11-20 日本電気株式会社 樹脂封止型半導体装置
JPH07335804A (ja) * 1994-06-14 1995-12-22 Dainippon Printing Co Ltd リードフレーム及びリードフレームの製造方法
KR0128164B1 (ko) * 1994-06-21 1998-04-02 황인길 반도체 패키지용 범용 히트스프레더
JPH0878605A (ja) * 1994-09-01 1996-03-22 Hitachi Ltd リードフレームおよびそれを用いた半導体集積回路装置
JP2767404B2 (ja) * 1994-12-14 1998-06-18 アナムインダストリアル株式会社 半導体パッケージのリードフレーム構造
KR0170023B1 (ko) * 1994-12-16 1999-02-01 황인길 반도체 패키지
US5530281A (en) * 1994-12-21 1996-06-25 Vlsi Technology, Inc. Wirebond lead system with improved wire separation
JP2611748B2 (ja) * 1995-01-25 1997-05-21 日本電気株式会社 樹脂封止型半導体装置
JPH08204100A (ja) * 1995-01-27 1996-08-09 Matsushita Electric Ind Co Ltd 放熱板付きリードフレームの製造方法
JPH08236683A (ja) * 1995-02-28 1996-09-13 Nec Corp リードフレーム
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US5729049A (en) * 1996-03-19 1998-03-17 Micron Technology, Inc. Tape under frame for conventional-type IC package assembly
JPH09260575A (ja) * 1996-03-22 1997-10-03 Mitsubishi Electric Corp 半導体装置及びリードフレーム
US6400569B1 (en) * 1997-07-18 2002-06-04 Composidie, Inc. Heat dissipation in lead frames
JP2000058735A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd リードフレーム、半導体装置及び半導体装置の製造方法
JP2000188366A (ja) * 1998-12-24 2000-07-04 Hitachi Ltd 半導体装置
KR100350046B1 (ko) * 1999-04-14 2002-08-24 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 방열판이 부착된 반도체패키지

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1328788C (zh) * 2003-06-09 2007-07-25 精工爱普生株式会社 半导体装置、半导体模块及其制法、电子设备、电子仪器
CN110265381A (zh) * 2018-03-12 2019-09-20 颀邦科技股份有限公司 半导体封装结构及其线路基板
CN110265381B (zh) * 2018-03-12 2020-12-18 颀邦科技股份有限公司 半导体封装结构及其线路基板

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KR20000017123A (ko) 2000-03-25
KR100596100B1 (ko) 2006-07-05
KR20040083027A (ko) 2004-09-30
US20020137262A1 (en) 2002-09-26
KR20040083028A (ko) 2004-09-30
CN1227734C (zh) 2005-11-16
KR100590634B1 (ko) 2006-06-19
SG81289A1 (en) 2001-06-19
US6396142B1 (en) 2002-05-28
MY124680A (en) 2006-06-30
TW421871B (en) 2001-02-11
US20020192871A1 (en) 2002-12-19
US20040126932A1 (en) 2004-07-01
US20020137261A1 (en) 2002-09-26

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