CN1249798C - 混合集成电路装置的制造方法 - Google Patents
混合集成电路装置的制造方法 Download PDFInfo
- Publication number
- CN1249798C CN1249798C CNB021251444A CN02125144A CN1249798C CN 1249798 C CN1249798 C CN 1249798C CN B021251444 A CNB021251444 A CN B021251444A CN 02125144 A CN02125144 A CN 02125144A CN 1249798 C CN1249798 C CN 1249798C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- substrate
- mould
- circuit apparatus
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 139
- 229920005989 resin Polymers 0.000 claims description 60
- 239000011347 resin Substances 0.000 claims description 60
- 229920001187 thermosetting polymer Polymers 0.000 claims description 23
- 238000009434 installation Methods 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000012423 maintenance Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 9
- 238000000465 moulding Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 25
- 239000002184 metal Substances 0.000 description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 23
- 239000011889 copper foil Substances 0.000 description 16
- 229920005992 thermoplastic resin Polymers 0.000 description 14
- 239000007924 injection Substances 0.000 description 13
- 238000002347 injection Methods 0.000 description 13
- 229910052759 nickel Inorganic materials 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- 238000004382 potting Methods 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 7
- 238000005755 formation reaction Methods 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 230000033228 biological regulation Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000008188 pellet Substances 0.000 description 4
- 230000000699 topical effect Effects 0.000 description 4
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 206010055001 Hypodontia Diseases 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 206010002583 anodontia Diseases 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 208000002925 dental caries Diseases 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000005213 hypodontia Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 201000006680 tooth agenesis Diseases 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种混合集成电路装置的制造方法,在模装工序中在模腔内要固定混合集成电路衬底的水平方向的位置。本发明通过使保持一定间隔的特定导线39a、39b与第一连结部53连接的部分与设于模型上的导销46a、46b接触,可固定混合集成电路衬底31的位置。由于特定导线39a、39b的间隔与混合集成电路衬底31的端子数无关,故即使端子数不同也可共用模型。
Description
技术领域
本发明涉及混合集成电路装置的制造方法,涉及在混合集成电路衬底上利用传递模形成树脂封装体的混合集成电路装置的制造方法。
背景技术
通常,用于混合集成电路装置的封装方法主要有两种。
第一方法是采用象在安装有半导体元件等电路元件的混合集成电路衬底之上盖盖子那样形状的装置、即通常被称作箱体构件的装置进行封装。该结构有时采用中空结构或在其中另外注入树脂的结构。
第二方法是作为半导体IC的模装方法采用注入模法。例如特开平11-330317号公报所示。该注入模法通常采用热塑性树脂,例如将加热到300℃的树脂利用高的注入压力注入并一度充填在模型内来封装树脂。与传递模相比,由于不需要将树脂充填在模型内后树脂的聚合时间,故具有可缩短作业时间的优点。
下面参照图9至图12说明使用注入模的现有混合集成电路装置及其制造方法。
首先,如图9所示,作为金属衬底这里采用铝(以下称Al)衬底1来说明。
该Al衬底1表面被阳极氧化,其上整个面上形成有绝缘性好的树脂2。但是,若考虑到耐压,则也可省去该氧化物。
树脂封装体10由支承部件10a和热塑性树脂形成。即通过注入模模装用热塑性树脂覆盖了载置于支承部件10a上的衬底1。然后,支承部件10a和热塑性树脂的接触部利用注入的高热的热塑性树脂溶化支承部件10a的接触部,实现全模装结构。
这里,热塑性树脂采用的是被称作PPS(聚亚苯基硫醚)的树脂。
热塑性树脂的注入温度非常高,约为300℃,存在高温的树脂使焊料12溶化产生焊料不良的问题。因此,预先罐封热硬性树脂(例如环氧树脂),覆盖焊料的结部、金属细线7、有源元件5及无源元件6,形成外敷层9。由此,防止在热塑性树脂成型时注入树脂压使尤其是细线(约30~80μm)倒下或断线。
树脂封装体10分两阶段形成。第一阶段为了确保在衬底1背面和模型之间设置间隙并在其间用高注入压力充填树脂时衬板1背面的厚度,在衬板1背面载置支承部件10a。第二阶段通过注入模由热塑性树脂覆盖载置于支承部件10a上的衬底1。然后,支承部件10a和热塑性树脂的接触部由注入的高热的热塑性树脂溶化支承部件10a的接触部,实现全模装结构。这里作为支承部件10a的热塑性树脂最好是与衬底1热膨胀系数同等的树脂。
下面,参照图10~图12说明使用注入模的现有混合集成电路装置的制造方法。
图10是工序流程图,包括准备金属衬底的工序、绝缘层形成工序、铜箔压装工序、局部镀镍工序、铜箔蚀刻工序、装片工序、引线接合工序、罐封工序、导线连接工序、支承部件安装工序、注入模工序、导线切断工序等各工序。
图11及图12表示各工序的剖面图。另外,不需图示也清楚的工序则省略附图。
首先,在图11(A)及图11(B)中,表示准备金属衬底的工序、绝缘层形成工序、铜箔压装工序、局部镀镍工序及铜箔蚀刻工序。
在准备金属衬底的工序中,作为衬底的作用根据散热性、衬底强度及衬底屏蔽性等而准备。而且,在本实施例中,使用散热性好的例如厚1.5mm左右的Al衬底1。
其次,在铝衬底1上,还在整个面上形成绝缘性好的树脂2。在绝缘性树脂2上压装构成混合集成电路的铜的导电箔3。在铜箔3上,根据其与例如电连接作为取出电极的铜箔3和有源元件5的金属细线7的粘接性,在整个面上实施镀镍4。
然后,利用公知的网印等形成镀镍4a及导电路3a。
其次,图11(C)表示装片工序及引线接合工序。
在前工序形成的导电路3a上通过焊剂12等导电糊安装有源元件5及无源元件6,实现规定的电路。
图12(A)、图12(B)表示罐封工序、导线连接工序及支承部件安装工序。
如图12(A)所示,在罐封工序中,在其后的注入模工序之前,预先用热硬性树脂(例如环氧树脂)罐封焊料的结部、金属细线7、有源元件5及无源元件6,形成外敷层9。
接着,准备用于将来自上述混合集成电路的信号输出及输入的外部导线8。然后,通过形成于衬底1外周部的外部连接端子11及焊料12连接外部导线8。
然后,如图12(B)所示,在连接了外部导线8等的混合集成电路衬底1上载置支承部件10a,将衬底1载置在支承部件10a上,从而可确保下工序所述的注入模模装时衬底1背面的树脂封装体10的厚度。
图12(C)表示注入模工序及导线切断工序。
如图所示,在衬底1上用热硬性树脂罐封并形成外敷层9之后,利用注入模形成树脂封装体10。此时,支承部件10a和热塑性树脂的接触部利用注入的高热的热塑性树脂使支承部件10a的接触部溶化,形成全模装结构的树脂封装体10。
最后,根据使用目的切断外部导线8,调节外部导线8的长度。
利用上述工序,完成图9所示的混合集成电路装置。
另外,半导体芯片中通常实施传递模法。在该传递模形成的混合集成电路装置中,例如是在铜构成的导线架上固定安装半导体元件。而且,半导体元件和导线是通过金(以下称Au)线电连接。这是由于Al细线容易折曲,接合时需要超声波,故接合时间较长,因此不能采用。因此,目前,将由一张金属板构成、金属板上形成电路并且由Al细线引线接合的金属衬底直接传递模模装的混合集成电路装置不存在。
发明内容
在注入模型的混合集成电路装置中,需要防止模装时的注入压力使金属细线7折曲或断线,防止注入时的温度使焊料12流动。因此,在图9所示的现有结构中采用罐封形成的外敷层9来对应上述问题。
但是,在用热硬性树脂(例如环氧树脂)罐封并形成外敷层9后,进行注入模模装,故存在耗费热硬性树脂的材料成本及操作成本的问题。
在现有的使用导线架的、传递模形成的混合集成电路装置中,将半导体元件等固定安装在隔离岛上,故半导体元件等产生的热自固定安装区域发散,但散热区域有限,存在散热性差的问题。
如上所述,在树脂封装体的引线接合中,采用了抗树脂注入压能力强的Au线,故采用Al线的传递模目前也未实施。而且,Al细线由于用超声波接合进行,收缩的部分弱,并且,弹性系数低,不能抗树脂的注入压等原因,会迅速弯曲。
在由传递模全部封装混合集成电路衬底的情况下,需要在模型内进行混合集成电路衬底的水平及厚度方向的位置固定,但是,当将固定销与混合集成电路衬底的背面接触进行定位时,存在封装后该衬底背面露出导致耐压劣化的问题。
本发明的目的在于提供一种在传递模工序中将混合集成电路衬底在模型内固定在规定位置的装置。
为了解决上述问题,本发明的半导体集成电路装置的制造方法包括下述工序:准备至少表面进行过绝缘处理的混合集成电路衬底;在所述衬底上形成导电图形;在所述导电图形上固定安装半导体元件或无源元件;将导线电连接在所述衬底上;利用传递模在所述衬底的至少表面上模装热硬性树脂。
在本发明中,模装工序的特征在于,使用焊料接合在混合集成电路衬底的导线架的特定导线的间隔一定,并使所述特定导线与设于导线中断的连结部连接的部分和设于模型上的导销接触。由此,进行所述导线架的定位,进而可进行混合集成电路衬底的定位,故可解决现有问题。并且,通过进行混合集成电路衬底的定位,可用散热性良好的树脂对混合集成电路衬底的背面进行一定厚度的覆盖,可提高混合集成电路装置的散热性。
附图说明
图1是本发明的混合集成电路装置的(A)平面图,(B)剖面图;
图2是本发明的混合集成电路装置的(A)剖面图,(B)平面图;
图3是本发明混合集成电路装置的制造方法的流程图;
图4是说明本发明混合集成电路装置的制造方法的图;
图5是说明本发明混合集成电路装置的制造方法的图;
图6是说明本发明混合集成电路装置的制造方法的图;
图7是说明本发明混合集成电路装置的制造方法的图;
图8是说明本发明混合集成电路装置的制造方法的图;
图9是现有混合集成电路装置的剖面图;
图10是现有混合集成电路装置的制造方法的流程图;
图11是说明现有混合集成电路装置的制造方法的图;
图12是说明现有混合集成电路装置的制造方法的图;
具体实施方式
下面,参照图1及图2说明本发明实施例1的混合集成电路装置。
首先,参照图2说明本混合集成电路装置的结构。如图2(A)所示,混合集成电路装置31考虑到固定安装在衬底31上的半导体元件等产生的热,采用散热性好的衬底。在本实施例中,就使用铝衬底31的情况进行说明。另外,虽然在本实施例中衬底31采用了铝(以下称Al)衬底,但不必特别限定。例如采用印刷电路板、陶瓷衬底、金属衬底等作为衬底31也可实现本实施例。而且,金属衬底可以用铜衬底、铁衬底、铁镍衬底或AlN(氮化铝)衬底等。
Al衬底31表面被阳极氧化,其上在整个面上还形成绝缘性良好的例如环氧树脂构成的绝缘树脂32。不过,若不考虑耐压,则也可不设该金属氧化物。
在该树脂32上,形成有铜箔33(参照图5)构成的导电路33a,Al衬底31上除电连接部位外例如由环氧系树脂形成外敷层,以保护导电路33a。导电路33a上通过焊料40安装有功率晶体管、小信号晶体管或IC等有源元件35、片状电阻、片状电容器等无源元件36,实现规定的电路。这里,也可以局部不采用焊料,而用银糊等电连接。在半导体元件等有源元件8面朝上安装的情况下,通过金属细线37连接。金属细线37在功率系半导体元件的情况下例如使用约150~500μmφ的Al线。通常将其称作粗线。在半功率系或小信号系半导体元件的情况下使用例如约30~80μmφ的Al线。通常将其称作细线。在设于Al衬底31外周部的外部连接用端子38上通过焊料40连接有铜或铁镍等导电性部件构成的外部导线39。
本发明的特征在于,在混合集成电路衬底31上的有源元件35、无源元件36及Al细线37等上直接形成树脂封装体。
也就是说,在树脂封装体41中,传递模使用的热硬性树脂粘度低且硬化温度低于上述连接装置所用的焊料40等的熔点例如183℃。由此,如图9所示,可除去现有混合集成电路装置中利用热硬性树脂(例如环氧树脂)的罐封形成的外敷层9。
其结果,尤其是将小信号系的IC等与导电路33a电连接的、例如约40μm左右的直径的金属细线等,即使直接填充传递模模装时的热硬性树脂,也不会躺倒、断线或折曲。尤其对Al细线而言,可防止折曲是要点。
下面如图2(B)所示,外部导线39向树脂封装体41的外部导出,外部导线39根据使用目的而调节长度。树脂封装体41上在与导出外部导线39的侧边相对的一侧,在两处作为压销痕形成有孔42。孔42是在上述传递模模装时压销47(参照图6)固定衬底31所产生的,在树脂封装体41形成后仍存在。
如图1(A)所示,孔42形成于衬底31的外周部43即衬底31上未形成电路等的部分。另外,孔42在衬底31的外周部43形成于绝缘树脂32上,故形成品质和耐湿性方面没有问题的结构。外周部43是为了在一个个冲压衬底31时确保与电路区域的距离而设置的边界。
如图1(A)、(B)所示,在Al衬底31上交错地形成有导电路33a,该导电路33a上通过焊料40等安装有功率晶体管、小信号晶体管或IC等有源元件35、片状电阻、片状电容器等无源元件36,通过外部连接用端子38连接有外部导线39,实现规定的电路。
如图所示,衬底31上以小的空间形成有复杂的电路。本发明的混合集成电路装置的特征在于,在Al衬底31整个面上形成绝缘树脂32后,在树脂32上形成复杂的电路,然后,在衬底31上粘接外部导线39,利用传递模直接一体形成树脂封装体41。
以往,在利用传递模形成混合集成电路装置的情况下,例如由铜构成的导线架利用蚀刻、冲孔或冲压等进行加工,形成配线、隔离岛等,故不能形成象混合集成电路的导电图形那样复杂的电路。传递模形成的导线架,在形成图1(A)那样的配线时,为了防止导线的弯曲需要在不同的部位用吊线固定。这样,在使用通常的导线架的混合集成电路中最多只安装几个有源元件,形成具有图2(A)那样的导电图形的混合集成电路受到了限制。
也就是说,通过采用本发明的混合集成电路装置的结构,可利用传递模形成具有复杂电路的衬底31。在本发明中,衬底31是使用导热系数高的衬底进行传递模模装的,故可发散衬底31整体产生的热。因此,与传递模模装的现有导线架构成的混合集成电路装置相比,由于直接模装金属衬底31,故该衬底作为大的散热片起作用,散热性好,可改善电路特性。
下面,参照图3~图8说明本发明的混合集成电路装置的制造方法。另外,图4至图8中,不需图示即清楚的工序省略附图。
图3是工序流程图,包括:准备金属衬底的工序;绝缘层形成工序;铜箔压装工序;局部镀镍工序,铜箔蚀刻工序;装片工序;引线接合工序;导线连接工序;传递模工序;导线切断工序等各工序。由该流程图可知,虽然目前是通过注入模形成树脂封装体,但本发明实现了由传递模形成树脂封装体的工序。
如图4(A)所示,本发明的第一工序是准备金属衬底、形成绝缘层、压装铜箔和进行镀镍的工序。
在准备金属衬底的工序中,作为衬底的作用要考虑散热性、衬底强度、衬底模装性等而准备。此时,尤其是当将功率晶体管、大规模LSI、数字信号处理电路等集成在一个小型混合IC时,由于热集中,故散热性受到重视。在本实施例中,使用散热性好的、例如厚1.5mm左右的Al衬底31。在本实施例中,衬底31使用Al衬底,但是不必特别限定。
例如使用印刷电路板、陶瓷衬底、金属衬底等作为衬底31也可实现本实施例。金属衬底可考虑铜衬底、铁镍衬底或由导电性好的金属构成的化合物等。
接着,衬底31表面被阳极氧化,生成氧化物,其上整个面还形成绝缘性好的例如由环氧树脂构成的树脂32。不过,若不考虑耐压,则也可省去该金属氧化物。然后,在绝缘性树脂32上压装构成混合集成电路的铜的导电箔33。在铜箔33上考虑到与例如将作为取出电极的铜箔33和有源元件35电连接的金属细线37的粘接性,在整个面上形成镀镍34。
如图4(B)所示,本发明的第二工序是用蚀刻形成局部镀镍和进行铜箔蚀刻的工序。
在镀镍34上,利用公知的网印等仅在需要镀镍34的部分残留抗蚀剂,形成选择掩模。然后,利用蚀刻在例如形成取出电极的部位形成镀镍34a。然后,除去抗蚀剂,再次利用公知的网印等仅在作为铜箔33构成的导电图形33a需要的部分残留抗蚀剂形成选择掩模。然后通过蚀刻,在绝缘性树脂32上形成铜箔33的导电图形33a。然后,在导电图形33a上例如利用网印由环氧树脂形成树脂外敷层。当然,进行电连接的部位不形成树脂外敷层。
如图4(C)所示,本发明第三工序是进行装片和引线接合的工序。
在前工序形成的导电图形33a上通过焊剂40等导电性糊剂安装功率晶体管、小信号晶体管或IC等有源元件35、片状电阻、片状电容器等无源元件36,实现规定的电路。这里,也可以局部不采用焊料,而用银糊等电连接。在安装功率晶体管、半功率晶体管等有源元件35时,考虑到散热性,在有源元件35和导电路33a之间设置散热片。
其次,在半导体元件等有源元件35面朝上安装的情况下,通过接合由金属细线37电连接。如上所述电连接有源元件35和导电路33a的金属细线37考虑到和铜箔33构成的导电路33a的粘接性,经镀镍34a进行引线接合。
这里,金属细线37特别使用Al细线37,Al细线37在空气中难于进行正球状连接,故使用针脚式接合法。但是,针脚式接合法中针脚部容易因树脂的应力而破坏,且与Au细线相比,弹性系数小,具有容易受树脂压力而被压倒的特征。因此,使用Al细线37时,尤其是形成树脂封装体41时要注意。这一点将后述。
如图5(A)、(B)所示,本发明第四工序是进行导线连接的工序。
如图5(A)所示,准备用于将来自上述混合集成电路的信号输出及输入的外部导线39。外部导线39为了用作输出输入端子由导电性的Cu、Fe-Ni等材质构成,并且,根据电流容量等决定外部导线39的宽度和厚度。在本发明的实施例中,外部导线39的强度、弹性是需要的,这一点在下道工序即传递模模装工序会详细说明。这里故要准备例如0.4~0.5mm左右厚的Fe-Ne外部导线39。然后,将外部导线39经焊料40和衬底31外周部形成的外部连接用端子38连接。此时,连接装置不限于焊料,也可以由点焊等进行连接。
这里,如图5(B)所示,本发明的特征在于,外部导线39相对于衬底31的安装面稍稍成一角度连接。图5中,衬底背面和外部导线39的背面间以所成的角度为10度左右的方式连接。连接外部导线39和外部连接用电极38的焊料40的熔点高于下道工序即传递模模装工序所用的热硬性树脂的硬化温度设定得较低。
本发明的第五工序是作为本发明特征的工序,如图6及图7所示,是利用传递模进行模装的工序。利用传递模模装,用热硬性树脂49总括封装混合集成电路衬底31。
为了利用传递模模装总括封装混合集成电路衬底31,混合集成电路衬底31如图6(B)所示在模腔70内必须定位。但是,在本发明中,由于是将混合集成电路衬底包括背面总括进行树脂模装,故不能使混合集成电路衬底31直接接触下模。因此,如上所述,使导线架39具有角度。如图6(B)所示,形成由压销47在混合集成电路衬底31的背面设置空间并进行固定的结构。同样,采用了即使销的个数不同也能共同使用的导线架。
具体地说,最初,如图6(A)所示,将用焊料粘接了导线架39的混合集成电路衬底31搬送到模型44及45。
然后,参照图7,通过使导线架39的特定部分与导销46接触,进行混合集成电路衬底31的水平方向(这里指纸面的纵向及横向)的定位。然后参照图6(B),通过用压销47按压混合集成电路衬底31的外周部43固定混合集成电路衬底31厚度方向的位置。
具体地说,导线架是在第一连结部39d和第二连结部39c两处连结多个导线39作为框体而保持的。自混合集成电路衬底31导出的导线的数量根据混合集成电路衬底31表面上形成的电气回路的规模而变化。但是,为了进行导线架39水平方向的定位,必须设置与导销46接触的特定的导线39a和39b,其间隔格局衬底尺寸是一定的。因此,根据衬底表面上形成的电气回路的规模导线的个数变化,这种情况下,增减与导销接触的导线以外的导线个数。这样,采用导线架根据衬底表面上形成的电气回路的规模使任意部位的导线缺齿的结构。
如图5(B)所示,导线架39不平行于混合集成电路衬底31,是向上方倾斜连接的。如后所述,可利用导线架39的弹性进行混合集成电路衬底31的厚度方向的定位。
导销46如图6(A)、图6(B)及图7(A)所示,是设于下模44的凸起物。参照图7(A),导销46由与特定导线39a及39b和第一连结部39d连接的部分接触的导销46a及46b、以及自外侧与第一连结部接触的导销46c及46d形成。也就是说,通过使这四个导销与导线架39的特定部分接触,固定导线架39的图面的方向。因此,混合集成电路衬底31也在图面方向固定。
即使在传递模模装输出及输入端子数不同的混合集成电路衬底时,由于特定导线39a及39b间隔一定,其中的导线被去掉,故也可共用模型及导销46。
如图6(A)、(B)所示,上模45设有压销47,导线架39如上所述用焊料向上倾斜地接合在混合集成电路衬底31上。因此,在上模45和下模44嵌合时,混合集成电路衬底31由压销47向下压,使其与下模44的底面平行。这样,模腔70内的混合集成电路衬底31完成厚度方向的位置固定。
如图7(B)所示,将自浇口49注入模腔70内的热硬性树脂以首先与衬底31的侧面接触的方式注入。然后,如箭头49所示注入的热硬性树脂自衬底31沿箭头49a向衬底31的上部方向及下部方向分流。此时,向衬底31的上部的流入宽度56和向衬底31的下部方向的流入宽度55形成大致相等的宽度,故热硬性树脂向衬底31下部的流入也可顺畅地进行。并且,尤其是由于树脂先充填混合集成电路衬底31的背面,故混合集成电路衬底31不会向下倾斜。另外,热硬性树脂的注入速度及注入压力也因曾于衬底31侧面接触而降低,可抑制Al细线37的折曲、断线等的影响。
由此,在本工序中可在模腔70内进行混合集成电路衬底31的定位后总括进行传递模模装,也没有热硬性树脂的注入压引起的混合集成电路衬底31的移动。因此,可用导热性好的热硬性树脂以一定厚度封装混合集成电路衬底31的背面,故可制造耐压性号且散热性优良的混合集成电路装置。
另外,由于连接功率晶体管、小信号晶体管及IC等有源元件35、片状电阻、片状电容器等无源元件36及外部导线39的焊料40的熔点高于热硬性树脂的熔点,故即使不用现有混合集成电路装置的罐封树脂9(参照图9)进行保护,也不会被传递模模装时的热量再熔融,不会使固定位置偏移。
另外,导线架的第二连结部39c具有防止进行传递模模装时热硬性树脂向模型外流出的作用。因此,在传递模模装刚结束时,如图8所示,封装的树脂连续到第二连结部39c。
如图8所示,本发明第六工序是进行导线切断的工序。
在前工序即传递模模装工序自模型44、45以外部导线的厚度流出的树脂由形成于外部导线39的第二连结部39c挡住,直接硬化。也就是说,自外部导线39的第二连结部39c起树脂封装体41侧的导线间充填了流出树脂50,自外部导线39的第二连结部起前端的导线间未充填树脂。
然后,冲切第二连结部39c同时除去流出树脂50,根据使用目的调节外部导线39的长度,例如,在虚线51的位置切断外部导线39,使其一个个导线独立,可作为输入输出端子起作用。
利用上述工序,完成图1所示的混合集成电路装置。
如上所述,本发明的混合集成电路装置的制造方法的特征在于,在传递模模装工序中,通过使特定导线与设于模型上的导销接触进行混合集成电路装置在模型内的定位。这样,在本发明的混合集成电路装置的制造方法中,可省略现有混合集成电路装置的制造方法中的支承部件的载置,并且,可大幅度提高完成的混合集成电路装置的散热性。
对本发明的混合集成电路装置及其制造方法,上面就全模装型混合集成电路装置进行了说明,但并不限于上述实施例。例如也可形成混合集成电路装置的背面整面露出的混合集成电路装置。这种情况下,在上述效果之外,还可得到散热性的效果。
并且,在本实施例中,是就外部导线自衬底的一个侧面导出的单侧导线的情况进行的说明,并不限于该结构,两侧导线,四个方向导线的情况下,在上述效果之外,还可在使衬底稳定的状态下实现传递模模装工序。另外,只要不脱离本发明的要旨的范围,就可进行种种变更。
另外,在不将导线39a作为电信号用端子使用时,如图7a所示,也可去掉自第二连结部39c向衬底31侧的导线。
如上所述,本发明的混合集成电路装置的制造方法可得到如下所述的优异效果。
在模装工序中,通过使特定导线和连结部连接的部分与设于模型上的导销接触,可在模腔内将与导线架连接的混合集成电路衬底定位后,用热硬性树脂总括进行传递模模装。由此,可以一定的厚度用导热性好的热硬性树脂封装混合集成电路衬底的背面,可制作散热性好的混合集成电路装置。另外,通过使与导销接触的导线的间隔一定,而与混合集成电路衬底的端子数无关,即使在传递模模装端子数不同的混合集成电路衬底时,也可共用模型。
另外,通过在导线架与上下模型接触的部分设置连结部,可防止在模装工序中热硬性树脂自导线间的缝隙流出到模型外部。通过使该连结部的长度与混合集成电路衬底的端子数无关地一定,即使在传递模模装端子数不同的混合集成电路衬底时也可共用模型。
Claims (8)
1、一种混合集成电路装置的制造方法,其特征在于,包括下述工序:准备通过导电图形电连接有电路元件的混合集成电路衬底;将作为输入或输出端子向外部延伸的导电装置用焊料固定位于所述混合集成电路装置的周边部的所述导电图形构成的端子上;通过用模装的上下模型夹持所述导电装置进行定位,来固定所述混合集成电路衬底的位置;利用使用了热硬性树脂的传递模模装总括模装所述混合集成电路衬底。
2、如权利要求1所述的混合集成电路装置的制造方法,其特征在于,所述导电装置是多个导线。
3、如权利要求2所述的混合集成电路装置的制造方法,其特征在于,所述导线的一端固定在所述混合集成电路装置的表面,所述导线的另一端向外方延伸设置,通过设置两个连结部,与多个所述导线交叉,从而所述导线作为一体的导线架保持。
4、如权利要求3所述的混合集成电路装置的制造方法,其特征在于,所述导线架在所述导线向外部导出侧的终端部具有第一连结部,在所述模装时与上下模型接触的部分具有第二连结部。
5、如权利要求3所述的混合集成电路装置的制造方法,其特征在于,在所述模装工序中,通过使所述导线架的纵向的侧边和横向的侧边与设于模型上的导销接触,固定所述混合集成电路衬底的位置。
6、如权利要求4所述的混合集成电路装置的制造方法,其特征在于,所述第二连结部在所述模装工序结束后除去。
7、如权利要求5所述的混合集成电路装置的制造方法,其特征在于,与所述导销接触的所述导线架的所述导线的间隔与所述混合集成电路衬底导出的导线的个数无关,是一定的。
8、如权利要求3所述的混合集成电路装置的制造方法,其特征在于,所述导线架自所述混合集成电路衬底的相对的两边或四边导出。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001196987A JP4614586B2 (ja) | 2001-06-28 | 2001-06-28 | 混成集積回路装置の製造方法 |
JP196987/2001 | 2001-06-28 | ||
JP196987/01 | 2001-06-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1395301A CN1395301A (zh) | 2003-02-05 |
CN1249798C true CN1249798C (zh) | 2006-04-05 |
Family
ID=19034691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021251444A Expired - Fee Related CN1249798C (zh) | 2001-06-28 | 2002-06-28 | 混合集成电路装置的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6593169B2 (zh) |
JP (1) | JP4614586B2 (zh) |
CN (1) | CN1249798C (zh) |
TW (1) | TW538661B (zh) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3896029B2 (ja) | 2002-04-24 | 2007-03-22 | 三洋電機株式会社 | 混成集積回路装置の製造方法 |
JP2004241729A (ja) * | 2003-02-07 | 2004-08-26 | Matsushita Electric Ind Co Ltd | 発光光源、照明装置、表示装置及び発光光源の製造方法 |
JP4413054B2 (ja) * | 2004-03-29 | 2010-02-10 | 三洋電機株式会社 | 混成集積回路装置の製造方法 |
JP4969113B2 (ja) | 2006-02-22 | 2012-07-04 | オンセミコンダクター・トレーディング・リミテッド | 回路装置の製造方法 |
US7557421B1 (en) * | 2006-07-20 | 2009-07-07 | Rf Micro Devices, Inc. | Hybrid radio frequency integrated circuit using gallium nitride epitaxy layers grown on a donor substrate |
JP2008270455A (ja) * | 2007-04-19 | 2008-11-06 | Hitachi Ltd | パワー半導体モジュール |
JP4356768B2 (ja) * | 2007-05-18 | 2009-11-04 | 株式会社デンソー | 電子装置及びその成形金型 |
US9093420B2 (en) | 2012-04-18 | 2015-07-28 | Rf Micro Devices, Inc. | Methods for fabricating high voltage field effect transistor finger terminations |
US9124221B2 (en) | 2012-07-16 | 2015-09-01 | Rf Micro Devices, Inc. | Wide bandwidth radio frequency amplier having dual gate transistors |
US9917080B2 (en) | 2012-08-24 | 2018-03-13 | Qorvo US. Inc. | Semiconductor device with electrical overstress (EOS) protection |
US9142620B2 (en) | 2012-08-24 | 2015-09-22 | Rf Micro Devices, Inc. | Power device packaging having backmetals couple the plurality of bond pads to the die backside |
US9202874B2 (en) | 2012-08-24 | 2015-12-01 | Rf Micro Devices, Inc. | Gallium nitride (GaN) device with leakage current-based over-voltage protection |
US9147632B2 (en) | 2012-08-24 | 2015-09-29 | Rf Micro Devices, Inc. | Semiconductor device having improved heat dissipation |
US8988097B2 (en) | 2012-08-24 | 2015-03-24 | Rf Micro Devices, Inc. | Method for on-wafer high voltage testing of semiconductor devices |
WO2014035794A1 (en) | 2012-08-27 | 2014-03-06 | Rf Micro Devices, Inc | Lateral semiconductor device with vertical breakdown region |
US9070761B2 (en) | 2012-08-27 | 2015-06-30 | Rf Micro Devices, Inc. | Field effect transistor (FET) having fingers with rippled edges |
US9325281B2 (en) | 2012-10-30 | 2016-04-26 | Rf Micro Devices, Inc. | Power amplifier controller |
US9980702B2 (en) | 2012-12-31 | 2018-05-29 | Volcano Corporation | Wirebonding fixture and casting mold |
US20140187957A1 (en) | 2012-12-31 | 2014-07-03 | Volcano Corporation | Ultrasonic Transducer Electrode Assembly |
JP6065978B2 (ja) | 2013-07-04 | 2017-01-25 | 三菱電機株式会社 | 半導体装置の製造方法、半導体装置 |
US9455327B2 (en) | 2014-06-06 | 2016-09-27 | Qorvo Us, Inc. | Schottky gated transistor with interfacial layer |
US9536803B2 (en) | 2014-09-05 | 2017-01-03 | Qorvo Us, Inc. | Integrated power module with improved isolation and thermal conductivity |
US9397017B2 (en) | 2014-11-06 | 2016-07-19 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9408301B2 (en) | 2014-11-06 | 2016-08-02 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US11437304B2 (en) | 2014-11-06 | 2022-09-06 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US10615158B2 (en) | 2015-02-04 | 2020-04-07 | Qorvo Us, Inc. | Transition frequency multiplier semiconductor device |
US10062684B2 (en) | 2015-02-04 | 2018-08-28 | Qorvo Us, Inc. | Transition frequency multiplier semiconductor device |
CN108321151A (zh) * | 2018-01-24 | 2018-07-24 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装组件及其制造方法 |
CN113284871B (zh) * | 2020-02-19 | 2024-05-17 | 珠海格力电器股份有限公司 | 一种dbc基板框架结构及其成型治具、成型方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5096852A (en) * | 1988-06-02 | 1992-03-17 | Burr-Brown Corporation | Method of making plastic encapsulated multichip hybrid integrated circuits |
JPH06224241A (ja) * | 1993-01-25 | 1994-08-12 | Toyota Autom Loom Works Ltd | 樹脂封止回路装置の成形方法 |
DE69735588T2 (de) * | 1996-05-27 | 2007-01-11 | Dai Nippon Printing Co., Ltd. | Herstellung eines bauteils für eine halbleiterschaltung |
WO1998035382A1 (en) * | 1997-02-10 | 1998-08-13 | Matsushita Electronics Corporation | Resin sealed semiconductor device and method for manufacturing the same |
US5918112A (en) * | 1997-07-24 | 1999-06-29 | Motorola, Inc. | Semiconductor component and method of fabrication |
US6448665B1 (en) * | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
JP3097842B2 (ja) * | 1997-11-26 | 2000-10-10 | サンケン電気株式会社 | 樹脂封止型半導体装置用リードフレーム |
JP2000294692A (ja) * | 1999-04-06 | 2000-10-20 | Hitachi Ltd | 樹脂封止型電子装置及びその製造方法並びにそれを使用した内燃機関用点火コイル装置 |
-
2001
- 2001-06-28 JP JP2001196987A patent/JP4614586B2/ja not_active Expired - Lifetime
-
2002
- 2002-06-25 TW TW91113851A patent/TW538661B/zh not_active IP Right Cessation
- 2002-06-27 US US10/183,757 patent/US6593169B2/en not_active Expired - Lifetime
- 2002-06-28 CN CNB021251444A patent/CN1249798C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2003017518A (ja) | 2003-01-17 |
TW538661B (en) | 2003-06-21 |
US6593169B2 (en) | 2003-07-15 |
US20030003630A1 (en) | 2003-01-02 |
JP4614586B2 (ja) | 2011-01-19 |
CN1395301A (zh) | 2003-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1249798C (zh) | 混合集成电路装置的制造方法 | |
CN104282641B (zh) | 半导体装置 | |
KR101391924B1 (ko) | 반도체 패키지 | |
US9035453B2 (en) | Semiconductor device | |
CN1395309A (zh) | 混合集成电路装置及其制造方法 | |
KR100342589B1 (ko) | 반도체 전력 모듈 및 그 제조 방법 | |
US9202798B2 (en) | Power module package and method for manufacturing the same | |
CN100378972C (zh) | 散热器及使用该散热器的封装体 | |
CN1395308A (zh) | 混合集成电路装置及其制造方法 | |
CN1264923A (zh) | 半导体器件及其制造方法 | |
CN105006453A (zh) | 封装结构 | |
CN1227734C (zh) | 半导体器件 | |
KR102004785B1 (ko) | 반도체모듈 패키지 및 그 제조 방법 | |
US20020070441A1 (en) | Chip array with two-sided cooling | |
JP4146785B2 (ja) | 電力用半導体装置 | |
CN1835222A (zh) | 半导体器件及其制造方法 | |
CN1638105A (zh) | 半导体器件 | |
JP2008263210A (ja) | 電力用半導体装置 | |
JP2009194327A (ja) | 電力用半導体装置 | |
KR20150060036A (ko) | 전력 반도체 모듈 및 그 제조 방법 | |
CN1674278A (zh) | 电路装置 | |
KR102199360B1 (ko) | 반도체 패키지 | |
CN1528014A (zh) | 芯片引线框架 | |
CN110914975A (zh) | 功率半导体模块 | |
JP2002329815A (ja) | 半導体装置と、その製造方法、及びその製造装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060405 Termination date: 20210628 |
|
CF01 | Termination of patent right due to non-payment of annual fee |