CN107146813A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107146813A
CN107146813A CN201710117505.XA CN201710117505A CN107146813A CN 107146813 A CN107146813 A CN 107146813A CN 201710117505 A CN201710117505 A CN 201710117505A CN 107146813 A CN107146813 A CN 107146813A
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electrode
contact hole
interarea
diffusion zone
semiconductor device
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CN107146813B (zh
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藤井秀纪
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Mitsubishi Electric Corp
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Abstract

得到一种能够实现高可靠性的半导体装置。在主单元区域，在半导体衬底(1)的主面形成有第1扩散区域(2)，在终端区域，在主面形成有第2扩散区域(3)。绝缘膜(5、6)形成于半导体衬底(1)的主面之上，在第1及第2扩散区域(2、3)之上分别具有第1及第2接触孔(7、8)。相同材质的第1及第2电极(9、10)分别形成于第1及第2接触孔(7、8)内。半绝缘性膜(11)将第2电极(10)覆盖。第1电极(9)不将第1接触孔(7)完全填埋。第2电极(10)将第2接触孔(8)完全填埋。第3电极(14)形成于第1电极(9)之上，将第1接触孔(7)完全填埋。

Description

半导体装置
技术领域
本发明涉及一种具有功率半导体用二极管构造的半导体装置。
背景技术
就用于功率半导体的二极管而言，由于在纵向上流过大电流，因此由厚的AlSi电极将主单元区域(main cell region)的接触孔填埋。另外，终端构造采用FLR(FieldLimiting Ring；场限环)构造，在GR(Guard Ring；保护环)和各FLR(Field Limiting Ring)形成FP(Field Plate；场板)电极，使耗尽层容易延伸(例如参照专利文献1)。并且，为了使电位稳定，在终端区域整个面形成有半绝缘性的保护膜。
近年来，在主单元区域流过电流的区域的接合方法从WB(Wire Bonding；导线接合)逐渐变化为DLB(Direct Lead Bonding；直接引线接合)。因此，在主电极之上形成用于进行焊接的电极的情况不断增多。
专利文献1：日本特开平09－023016号公报
近年来，就功率半导体而言，为了缩小无效区域，也需要对终端区域进行微细化。但是，由于电极的膜厚大，因此不能形成微细图案。另外，即使能够形成微细且高台阶的高纵横比的图案，也会由于来自外部的封装体的应力，发生电极倾倒或者使电极台阶部处的保护膜产生裂纹，可靠性劣化。另一方面，如果使主单元区域的电极过薄，则会出现由局部电流集中所导致的破坏、由接触端部的覆盖率变差而导致的断线、以及在形成用于对外部电极进行焊接的电极时对Si衬底造成损伤。由此，存在不能实现高可靠性这一问题。
发明内容
本发明就是为了解决上述课题而提出的，其目的在于得到一种能够实现高可靠性的半导体装置。
本发明所涉及的半导体装置的特征在于，具有：半导体衬底，其具有主面；第1扩散区域，其在主单元区域形成于所述主面；第2扩散区域，其在所述主单元区域的外侧的终端区域形成于所述主面；绝缘膜，其形成于所述主面之上，在所述第1及第2扩散区域之上分别具有第1及第2接触孔；第1电极，其形成于所述第1接触孔内，与所述第1扩散区域连接；第2电极，其形成于所述第2接触孔内，与所述第2扩散区域连接；半绝缘性膜，其将所述第2电极覆盖；以及第3电极，其形成于所述第1电极之上，第1及第2电极是相同的材质，所述第1电极不将所述第1接触孔完全填埋，所述第2电极将所述第2接触孔完全填埋，所述第3电极将所述第1接触孔完全填埋。
发明的效果
在本发明中，第1电极不将第1接触孔完全填埋，第2电极将第2接触孔完全填埋。因此，在同时形成了相同材质的第1及第2电极的情况下，能够降低终端区域的电极的台阶，抑制电极倾倒以及电极台阶部处的保护膜的裂纹的发生。另外，由于第3电极将第1接触孔完全填埋，因此还不会发生电流集中。由此，能够实现高可靠性。
附图说明
图1是表示本发明的实施方式1所涉及的半导体装置的剖视图。
图2是表示对比例所涉及的半导体装置的剖视图。
图3是表示本发明的实施方式2所涉及的半导体装置的剖视图。
标号的说明
1 Si衬底(半导体衬底)，2 p型阳极区域(第1扩散区域)，3 p型环形区域(第2扩散区域)，5 SiO2氧化膜(绝缘膜)，6 TEOS氧化膜(绝缘膜)，7第1接触孔，8第2接触孔，9 AlSi电极(第1电极)，10 AlSi电极(第2电极)，11 SiN半绝缘性膜(半绝缘性膜)，14 Ni电极(第3电极)
具体实施方式
参照附图，对本发明的实施方式所涉及的半导体装置进行说明。对相同或者相对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1
图1是表示本发明的实施方式1所涉及的半导体装置的剖视图。在主单元区域，在Si衬底1的主面形成有p型阳极区域2，在主单元区域的外侧的终端区域，在Si衬底1的主面形成有多个p型环形区域3及n+型环形区域4。SiO2氧化膜5及TEOS氧化膜6形成于Si衬底1的主面之上。SiO2氧化膜5及TEOS氧化膜6在p型阳极区域2及p型环形区域3之上分别具有第1及第2接触孔7、8。
AlSi电极9形成于第1接触孔7内，与p型阳极区域2连接。多个AlSi电极10分别形成于多个第2接触孔8内，分别与多个p型环形区域3连接。作为保护膜，SiN半绝缘性膜11及SiN绝缘膜12将多个AlSi电极10覆盖。聚酰亚胺13将除焊接用电极形成部以外的整个面覆盖。作为用于对外部电极进行焊接的焊接用电极，Ni电极14及Au电极15依次形成于AlSi电极9之上。在Si衬底1的背面形成有n+型阴极层16。
在这里，AlSi电极9、10是相同的材质，是同时形成的。但是，AlSi电极9不将第1接触孔7完全填埋，而AlSi电极10将第2接触孔8完全填埋。即，第1接触孔7处的AlSi电极9的厚度比第1接触孔7的深度小，但第2接触孔8处的AlSi电极10的厚度比第2接触孔8的深度大。并且，Ni电极14将第1接触孔7完全填埋。即，第1接触孔7处的AlSi电极9及Ni电极14的合计厚度比第1接触孔7的深度大。
接下来，对本实施方式所涉及的半导体装置的制造方法进行说明。首先，在Si衬底1之上热形成厚度为的SiO2氧化膜5，在通过照相制版和蚀刻而形成图案后，进行1E13～1E16[1/cm2]的硼注入和驱动(900℃～1200℃：30min～120min)，同时形成主单元区域和终端区域的p型阳极区域2及p型环形区域3。
然后，在通过照相制版和蚀刻而形成图案后，进行1E14～1E16[1/cm2]的As注入和驱动(900℃～1200℃：30min～120min)，形成终端区域的最外周的n+型环形区域4。
然后，堆积厚度为的TEOS氧化膜6，进行图案化而形成第1及第2接触孔7、8。然后，以不将主单元区域的第1接触孔7完全填埋、而将终端区域的第2接触孔填埋的厚度对AlSi膜进行溅射或者蒸镀。对AlSi膜进行图案化而形成场板(Field Plate)和AlSi电极9、10。
然后，依次对/折射率为2.2～2.7的SiN半绝缘性膜11和/折射率为1.8～2.2的SiN绝缘膜12进行成膜而作为保护膜，去除主单元区域的保护膜。
然后，对整个面涂敷几μm的聚酰亚胺13，仅去除电极形成区域的聚酰亚胺13。然后，从背面起将Si衬底1研磨为所期望的厚度，通过离子注入(注入1E13～1E16[1/cm2]的磷或者砷)和热处理(激光退火等)而形成n+型阴极层16。最后，通过镀敷或者溅射/蒸镀而形成几μm的Ni电极14及Au电极15。
接下来，与对比例进行比较而说明本实施方式的效果。图2是表示对比例所涉及的半导体装置的剖视图。在对比例中，AlSi电极9、10以将第1及第2接触孔7、8完全填埋的方式形成得较厚。因此，由于来自外部的封装体的应力而发生电极倾倒或者使电极台阶部处的保护膜产生裂纹，可靠性劣化。
与此相对，在本实施方式中，AlSi电极9不将第1接触孔7完全填埋，AlSi电极10将第2接触孔8完全填埋。因此，在同时形成相同材质的AlSi电极9、10的情况下，能够降低终端区域的电极的台阶，抑制电极倾倒以及电极台阶部处的保护膜的裂纹的发生。另外，由于Ni电极14将第1接触孔7完全填埋，因此还不会发生电流集中。由此，能够实现高可靠性。
实施方式2
图3是表示本发明的实施方式2所涉及的半导体装置的剖视图。与实施方式1不同，AlSi电极10不将第2接触孔8完全填埋，SiN半绝缘性膜11将第2接触孔8完全填埋。由此，即使终端区域的接触覆盖率变差而导致断线，也被SiN半绝缘性膜11填埋而成为相同电位。因此，能够使反向偏置时的电位由FLR和FP分担，使耐压得以稳定化。其他结构及效果与实施方式1相同。
此外，在实施方式1、2中，也可以在AlSi电极9、10之下形成TiN或者TiW等阻挡金属。由此，能够抑制形成用于对外部电极进行焊接的电极时的损伤，降低泄漏电流。另外，也可以取代AlSi电极9、10而形成TiN或者TiW等阻挡金属。由此，能够使电极厚度小，因此能够实现微细化。另外，实施方式1、2的pin二极管构造在导电型颠倒的情况下也是成立的。
另外，不限于Si衬底1，也可以使用由与硅相比带隙更大的宽带隙半导体形成的半导体衬底。宽带隙半导体例如是碳化硅、氮化镓类材料或者金刚石。由于由上述宽带隙半导体形成的功率半导体元件的耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化后的元件，从而组装了该元件的半导体模块也能够小型化。另外，由于元件的耐热性高，因此能够将散热器的散热鳍片小型化，能够对水冷部进行空冷化，因而能够将半导体模块进一步小型化。另外，由于元件的电力损耗低，且效率高，因此能够将半导体模块高效化。

Claims (5)

1.一种半导体装置，其特征在于，具有：
半导体衬底，其具有主面；
第1扩散区域，其在主单元区域形成于所述主面；
第2扩散区域，其在所述主单元区域的外侧的终端区域形成于所述主面；
绝缘膜，其形成于所述主面之上，在所述第1及第2扩散区域之上分别具有第1及第2接触孔；
第1电极，其形成于所述第1接触孔内，与所述第1扩散区域连接；
第2电极，其形成于所述第2接触孔内，与所述第2扩散区域连接；
半绝缘性膜，其将所述第2电极覆盖；以及
第3电极，其形成于所述第1电极之上，
第1及第2电极是相同的材质，
所述第1电极不将所述第1接触孔完全填埋，
所述第2电极将所述第2接触孔完全填埋，
所述第3电极将所述第1接触孔完全填埋。
2.一种半导体装置，其特征在于，具有：
半导体衬底，其具有主面；
第1扩散区域，其在主单元区域形成于所述主面；
第2扩散区域，其在所述主单元区域的外侧的终端区域形成于所述主面；
绝缘膜，其形成于所述主面之上，在所述第1及第2扩散区域之上分别具有第1及第2接触孔；
第1电极，其形成于所述第1接触孔内，与所述第1扩散区域连接；
第2电极，其形成于所述第2接触孔内，与所述第2扩散区域连接；
半绝缘性膜，其将所述第2电极覆盖；以及
第3电极，其形成于所述第1电极之上，
第1及第2电极是相同的材质，
所述第1电极不将所述第1接触孔完全填埋，
所述第2电极不将所述第2接触孔完全填埋，
所述半绝缘性膜将所述第2接触孔完全填埋，
所述第3电极将所述第1接触孔完全填埋。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述第1及第2电极具有Al类电极。
4.根据权利要求3所述的半导体装置，其特征在于，
所述第1及第2电极还具有在所述Al类电极之下形成的阻挡金属。
5.根据权利要求1或2所述的半导体装置，其特征在于，
所述第1及第2电极是阻挡金属。
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