JP6575398B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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JP6575398B2
JP6575398B2 JP2016039067A JP2016039067A JP6575398B2 JP 6575398 B2 JP6575398 B2 JP 6575398B2 JP 2016039067 A JP2016039067 A JP 2016039067A JP 2016039067 A JP2016039067 A JP 2016039067A JP 6575398 B2 JP6575398 B2 JP 6575398B2
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electrode
contact hole
insulating film
thickness
region
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JP2017157670A (ja
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藤井　秀紀
秀紀 藤井
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Mitsubishi Electric Corp
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Description

本発明は、パワー半導体用のダイオード構造を有する半導体装置に関する。
パワー半導体用のダイオードでは、縦方向に大電流を流すため、メインセル領域のコンタクトホールを厚いＡｌＳｉ電極で埋め込んでいる。また、終端構造はＦＬＲ（Field Limiting Ring）構造を採用しており、ＧＲ（Guard Ring）と各ＦＬＲ（Field Limiting Ring）にＦＰ（Field Plate）電極を形成し、空乏層を伸びやすくしている（例えば、特許文献１参照）。更に、電位を安定させるため、半絶縁性の保護膜が終端領域全面に形成されている。
近年、メインセル領域に電流を流す領域の接合方法が、ＷＢ（Wire Bonding）からＤＬＢ（Direct Lead Bonding）に変化してきている。このため、メイン電極の上に半田付けをするための電極が形成されることが増えてきている。
特開平０９−０２３０１６号公報
近年、パワー半導体においても、無効領域を縮小するために、終端領域を微細化する必要性が出てきている。しかし、電極の膜厚が厚いため、微細パターンを形成できない。また、微細で高段差の高アスペクトなパターンを形成できても、外部のパッケージからの応力により電極倒れ又は電極段差部での保護膜のクラックが発生し、信頼性が劣化する。一方、メインセル領域の電極を薄くし過ぎると、局所的な電流集中による破壊、コンタクト端部のカバレッジが悪くなることによる断線、及び外部電極を半田付けするための電極を形成する際にＳｉ基板にダメージが入る。よって、高信頼性を実現できないという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は高信頼性を実現することができる半導体装置を得るものである。
本発明に係る半導体装置は、主面を有する半導体基板と、メインセル領域において前記主面に形成された第１の拡散領域と、前記メインセル領域の外側の終端領域において前記主面に形成された第２の拡散領域と、前記主面上に形成され、前記第１及び第２の拡散領域上にそれぞれ第１及び第２のコンタクトホールを有する第１の絶縁膜と、前記第１のコンタクトホール内に形成され、前記第１の拡散領域に接続された第１の電極と、前記第２のコンタクトホール内に形成され、前記第２の拡散領域に接続された第２の電極と、前記第２の電極を覆う半絶縁性膜と、半絶縁性膜上に形成された第２の絶縁膜と、第２の絶縁膜を覆うポリイミドと、前記第１の電極上に形成された第３の電極とを備え、第１及び第２の電極は同じ材質であり、第１のコンタクトホールにおける第１の電極の厚みは第１のコンタクトホールの深さより薄く、第１のコンタクトホールにおける第１の電極の厚み及び前記第３の電極の厚みの合計は第１のコンタクトホールの深さより厚く、第２のコンタクトホールにおける第２の電極の厚みは第２のコンタクトホールの深さより厚いことを特徴とする。
本発明では、第１のコンタクトホールにおける第１の電極の厚みは第１のコンタクトホールの深さより薄く、第１のコンタクトホールにおける第１の電極の厚み及び前記第３の電極の厚みの合計は第１のコンタクトホールの深さより厚く、第２のコンタクトホールにおける第２の電極の厚みは第２のコンタクトホールの深さより厚い。このため、同じ材質である第１及び第２の電極を同時に形成した場合に終端領域の電極の段差が低減され、電極倒れ及び電極段差部での保護膜のクラックの発生を抑制できる。また、第３の電極が第１のコンタクトホールを完全に埋め込むため、電流集中も起こらない。よって、高信頼性を実現できる。
本発明の実施の形態１に係る半導体装置を示す断面図である。 比較例に係る半導体装置を示す断面図である。 本発明の実施の形態２に係る半導体装置を示す断面図である。
本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。メインセル領域においてＳｉ基板１の主面にｐ型アノード領域２が形成され、メインセル領域の外側の終端領域においてＳｉ基板１の主面に複数のｐ型リング領域３及びｎ＋型リング領域４が形成されている。ＳｉＯ２酸化膜５及びＴＥＯＳ酸化膜６がＳｉ基板１の主面上に形成されている。ＳｉＯ２酸化膜５及びＴＥＯＳ酸化膜６は、ｐ型アノード領域２及びｐ型リング領域３上にそれぞれ第１及び第２のコンタクトホール７，８を有する。
ＡｌＳｉ電極９が、第１のコンタクトホール７内に形成され、ｐ型アノード領域２に接続されている。複数のＡｌＳｉ電極１０が、複数の第２のコンタクトホール８内にそれぞれ形成され、それぞれ複数のｐ型リング領域３に接続されている。保護膜としてＳｉＮ半絶縁性膜１１及びＳｉＮ絶縁膜１２が複数のＡｌＳｉ電極１０を覆っている。ポリイミド１３が半田付け用電極形成部以外の全面を覆っている。外部電極を半田付けするための半田付け用電極としてＮｉ電極１４及びＡｕ電極１５がＡｌＳｉ電極９上に順に形成されている。Ｓｉ基板１の裏面にｎ＋型カソード層１６が形成されている。
ここで、ＡｌＳｉ電極９，１０は同じ材質であり同時に形成されている。ただし、ＡｌＳｉ電極９は第１のコンタクトホール７を完全には埋め込まないが、ＡｌＳｉ電極１０は第２のコンタクトホール８を完全に埋め込む。即ち、第１のコンタクトホール７におけるＡｌＳｉ電極９の厚みは第１のコンタクトホール７の深さよりも小さいが、第２のコンタクトホール８におけるＡｌＳｉ電極１０の厚みは第２のコンタクトホール８の深さよりも大きい。そして、Ｎｉ電極１４は第１のコンタクトホール７を完全に埋め込む。即ち、第１のコンタクトホール７におけるＡｌＳｉ電極９及びＮｉ電極１４の合計厚みは第１のコンタクトホール７の深さよりも大きい。
続いて、本実施の形態に係る半導体装置の製造方法を説明する。まず、Ｓｉ基板１上に厚さ３０００Å〜１００００ÅのＳｉＯ２酸化膜５を熱形成し、写真製版とエッチングでパターン形成後、１Ｅ１３〜１Ｅ１６［１／ｃｍ２］のボロン注入とドライブ（９００℃〜１２００℃：３０ｍｉｎ〜１２０ｍｉｎ）を行い、メインセル領域と終端領域のｐ型アノード領域２及びｐ型リング領域３を同時に形成する。
次に、写真製版とエッチングでパターン形成後、１Ｅ１４〜１Ｅ１６［１／ｃｍ２］のＡｓ注入とドライブ（９００℃〜１２００℃：３０ｍｉｎ〜１２０ｍｉｎ）を行い、終端領域の最外周のｎ＋型リング領域４を形成する。
次に、厚さ５０００Å〜１００００ÅのＴＥＯＳ酸化膜６を堆積し、パターンニングして第１及び第２のコンタクトホール７，８を形成する。次に、ＡｌＳｉ膜をメインセル領域の第１のコンタクトホール７が完全には埋め込まれず、終端領域の第２のコンタクトホールが埋め込まれる厚みでスパッタ又は蒸着する。ＡｌＳｉ膜をパターンニングしてフィールドプレート（Field Plate）とＡｌＳｉ電極９，１０を形成する。
次に、保護膜として、２０００Å〜１００００Å／屈折率２．２〜２．７のＳｉＮ半絶縁性膜１１と、２０００Å〜１００００Å／屈折率１．８〜２．２のＳｉＮ絶縁膜１２とを順に成膜し、メインセル領域の保護膜を除去する。
次に、ポリイミド１３を数μｍ全面塗布し、電極形成領域のみ除去する。次に、Ｓｉ基板１を裏面から所望の厚みに研磨し、イオン注入（リン又はヒ素を１Ｅ１３〜１Ｅ１６［１／ｃｍ２］注入し）と熱処理（Laser Annealなど）によりｎ＋型カソード層１６を形成する。最後に、Ｎｉ電極１４及びＡｕ電極１５をめっき又はスパッタ／蒸着で数μｍ形成する。
続いて、本実施の形態の効果を比較例と比較して説明する。図２は、比較例に係る半導体装置を示す断面図である。比較例では、ＡｌＳｉ電極９，１０が第１及び第２のコンタクトホール７，８を完全に埋め込むように厚く形成されている。このため、外部のパッケージからの応力により電極倒れ又は電極段差部での保護膜のクラックが発生し、信頼性が劣化する。
これに対して、本実施の形態では、ＡｌＳｉ電極９は第１のコンタクトホール７を完全には埋め込まず、ＡｌＳｉ電極１０が第２のコンタクトホール８を完全に埋め込む。このため、同じ材質であるＡｌＳｉ電極９，１０を同時に形成した場合に終端領域の電極の段差が低減され、電極倒れ及び電極段差部での保護膜のクラックの発生を抑制できる。また、Ｎｉ電極１４が第１のコンタクトホール７を完全に埋め込むため、電流集中も起こらない。よって、高信頼性を実現できる。
実施の形態２．
図３は、本発明の実施の形態２に係る半導体装置を示す断面図である。実施の形態１とは異なり、ＡｌＳｉ電極１０が第２のコンタクトホール８を完全には埋め込まず、ＳｉＮＳｉＮ半絶縁性膜１１が第２のコンタクトホール８を完全に埋め込む。これにより、終端領域のコンタクトカバレッジが悪くなることで断線したとしても、ＳｉＮ半絶縁性膜１１で埋め込まれて同電位となる。このため、逆バイアス時の電位がＦＬＲとＦＰで分担され、耐圧を安定化することができる。その他の構成及び効果は実施の形態１と同様である。
なお、実施の形態１，２において、ＡｌＳｉ電極９，１０の下にＴｉＮ又はＴｉＷなどのバリアメタルを形成してもよい。これにより、外部電極を半田付けするための電極形成時のダメージを抑制し、リーク電流を低減することができる。また、ＡｌＳｉ電極９，１０の代わりにＴｉＮ又はＴｉＷなどのバリアメタルを形成してもよい。これにより、電極厚みを薄くすることができるため、微細化が可能となる。また、実施の形態１，２のｐｉｎダイオード構造は逆導電型の場合でも成立する。
また、Ｓｉ基板１に限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成された半導体基板を用いてもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成されたパワー半導体素子は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ半導体モジュールも小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。
１ Ｓｉ基板（半導体基板）、２ ｐ型アノード領域（第１の拡散領域）、３ ｐ型リング領域（第２の拡散領域）、５ ＳｉＯ２酸化膜（絶縁膜）、６ ＴＥＯＳ酸化膜（絶縁膜）、７ 第１のコンタクトホール、８ 第２のコンタクトホール、９ ＡｌＳｉ電極（第１の電極）、１０ ＡｌＳｉ電極（第２の電極）、１１ ＳｉＮ半絶縁性膜（半絶縁性膜）、１４ Ｎｉ電極（第３の電極）

Claims (5)

  1. 主面を有する半導体基板と、
    メインセル領域において前記主面に形成された第１の拡散領域と、
    前記メインセル領域の外側の終端領域において前記主面に形成された第２の拡散領域と、
    前記主面上に形成され、前記第１及び第２の拡散領域上にそれぞれ第１及び第２のコンタクトホールを有する第１の絶縁膜と、
    前記第１のコンタクトホール内に形成され、前記第１の拡散領域に接続された第１の電極と、
    前記第２のコンタクトホール内に形成され、前記第２の拡散領域に接続された第２の電極と、
    前記第２の電極を覆う半絶縁性膜と、
    前記半絶縁性膜上に形成された第２の絶縁膜と、
    前記第２の絶縁膜を覆うポリイミドと、
    前記第１の電極上に形成された第３の電極とを備え、
    第１及び第２の電極は同じ材質であり、
    前記第１のコンタクトホールにおける前記第１の電極の厚みは前記第１のコンタクトホールの深さより薄く、
    前記第１のコンタクトホールにおける前記第１の電極の厚み及び前記第３の電極の厚みの合計は前記第１のコンタクトホールの深さより厚く、
    前記第２のコンタクトホールにおける前記第２の電極の厚みは前記第２のコンタクトホールの深さより厚いことを特徴とする半導体装置。
  2. 主面を有する半導体基板と、
    メインセル領域において前記主面に形成された第１の拡散領域と、
    前記メインセル領域の外側の終端領域において前記主面に形成された第２の拡散領域と、
    前記主面上に形成され、前記第１及び第２の拡散領域上にそれぞれ第１及び第２のコンタクトホールを有する第１の絶縁膜と、
    前記第１のコンタクトホール内に形成され、前記第１の拡散領域に接続された第１の電極と、
    前記第２のコンタクトホール内に形成され、前記第２の拡散領域に接続された第２の電極と、
    前記第２の電極を覆う半絶縁性膜と、
    前記半絶縁性膜上に形成された第２の絶縁膜と、
    前記第２の絶縁膜を覆うポリイミドと、
    前記第１の電極上に形成された第３の電極とを備え、
    第１及び第２の電極は同じ材質であり、
    前記第１のコンタクトホールにおける前記第１の電極の厚みは前記第１のコンタクトホールの深さより薄く、
    前記第１のコンタクトホールにおける前記第１の電極の厚み及び前記第３の電極の厚みの合計は前記第１のコンタクトホールの深さより厚く、
    前記第２のコンタクトホールにおける前記第２の電極の厚みは前記第２のコンタクトホールの深さより浅く、
    前記第２のコンタクトホールにおける前記第２の電極の厚み及び前記半絶縁性膜の厚みの合計は前記第１のコンタクトホールの深さより厚いことを特徴とする半導体装置。
  3. 前記第１及び第２の電極はＡｌ系電極を有することを特徴とする請求項１又は２に記載の半導体装置。
  4. 前記第１及び第２の電極は、前記Ａｌ系電極の下に形成されたバリアメタルを更に有することを特徴とする請求項３に記載の半導体装置。
  5. 前記第１及び第２の電極はバリアメタルであることを特徴とする請求項１又は２に記載の半導体装置。
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