CN110310927B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110310927B
CN110310927B CN201910222300.7A CN201910222300A CN110310927B CN 110310927 B CN110310927 B CN 110310927B CN 201910222300 A CN201910222300 A CN 201910222300A CN 110310927 B CN110310927 B CN 110310927B
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insulating film
semiconductor substrate
semiconductor
openings
semiconductor device
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CN110310927A (zh
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森本升
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Mitsubishi Electric Corp
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Abstract

得到能够防止从装置端部向装置内部的水分浸入的半导体装置。半导体衬底(1)具有设置有器件的单元区域(2)、以及在单元区域(2)的周围设置的末端区域(3)。第1绝缘膜(7)在末端区域(3)设置于半导体衬底(1)之上,具有多个开口(8b、8c、8d)。多个金属电极(10、11)设置于末端区域(3),经由多个开口(8b、8c)与半导体衬底(1)连接。与第1绝缘膜(7)相比吸湿率低的第2绝缘膜(12)将第1绝缘膜(7)及多个金属电极(10、11)覆盖。在从多个金属电极(10、11)中的最外周的电极(11)至半导体衬底(1)的端部为止的区域,第2绝缘膜(12)与半导体衬底(1)直接接触。

Description

半导体装置
技术领域
本发明涉及在装置表面设置有保护膜的半导体装置。
背景技术
以半导体装置的保护为目的,在装置表面设置由无机材料或有机材料构成的保护膜。作为无机保护膜使用了硅氧化膜或硅氮化膜。特别地,由于硅氮化膜对水分的透过性小,因此用作防止来自外部的水分的侵入的最表面的保护膜。
在对半导体封装体进行了模拟高温高湿环境的THB试验(Temperature HumidityBias Test)的情况下,有时由于水分的侵入而使器件产生故障。如果水分侵入到封装体内,则有时水分在封装材料中扩散而到达半导体装置。有时该水分从装置端部侵入至装置内部,铝电极受到腐蚀,器件产生故障。如果在保护环的铝电极产生腐蚀,则不能保持耐压而导致泄露故障及耐压故障。相对于此,提出了在半导体衬底的表面作为保护膜层叠了硅氧化膜和硅氮化膜的半导体装置(例如,参照专利文献1)。
专利文献1:日本专利第4710224号公报
在现有技术中,能够防止从装置表面向装置内部的垂直方向的水分浸入。但是,不能够防止从装置端部通过硅氧化膜或通过硅氧化膜和硅氮化膜的界面向装置内部的水平方向的水分浸入。
发明内容
本发明就是为了解决上述课题而提出的,其目的在于得到能够防止从装置端部向装置内部的水分浸入的半导体装置。
本发明涉及的半导体装置的特征在于具备:半导体衬底,其具有设置有器件的单元区域、以及在所述单元区域的周围设置的末端区域;第1绝缘膜,其在所述末端区域设置于所述半导体衬底之上,具有多个开口;多个金属电极,它们设置于所述末端区域,经由所述多个开口与所述半导体衬底连接;以及第2绝缘膜,其覆盖所述第1绝缘膜及所述多个金属电极,与所述第1绝缘膜相比吸湿率低,在从所述多个金属电极中的最外周的电极至所述半导体衬底的端部为止的区域,所述第2绝缘膜与所述半导体衬底直接接触。
发明的效果
在本发明中,在从最外周的电极至半导体衬底的端部为止的区域,吸湿率低的第2绝缘膜与半导体衬底直接接触。由此,能够防止从装置端部向装置内部的水分浸入。
附图说明
图1是表示实施方式1涉及的半导体装置的俯视图。
图2是沿图1的I-II的剖视图。
图3是表示对比例涉及的半导体装置的剖视图。
图4是表示实施方式1涉及的半导体装置的变形例1的剖视图。
图5是表示实施方式1涉及的半导体装置的变形例2的剖视图。
图6是表示实施方式2涉及的半导体装置的剖视图。
图7是表示实施方式2涉及的半导体装置的变形例的剖视图。
图8是表示实施方式3涉及的半导体装置的剖视图。
标号的说明
1半导体衬底,2单元区域,3末端区域,5p型保护环层,6n型沟道截断层,7绝缘膜(第1绝缘膜),8a、8b、8c、8d开口,10保护环电极(金属电极),11沟道截断电极(金属电极),12绝缘膜(第2绝缘膜),16绝缘膜(第2绝缘膜),17绝缘膜(第3绝缘膜),17a第1部分,17b第2部分
具体实施方式
参照附图对实施方式涉及的半导体装置进行说明。对相同或对应的结构要素标注相同标号,有时省略重复说明。
实施方式1
图1是表示实施方式1涉及的半导体装置的俯视图。半导体衬底1具有设置有器件的单元区域2、在单元区域2的周围设置的末端区域3。器件为pin二极管,但并不限于此,也可以是IGBT(Insulated Gate Bipolar Transistor)。在单元区域2,在器件的导通状态下流过主电流。末端区域3在导通状态下不流过电流,在断开状态的施加反向偏置时使耗尽层在器件横向上延伸而保持耐压。
图2是沿图1的I-II的剖视图。在单元区域2,在n-型的半导体衬底1的表面设置有p型阳极层4。在末端区域3,在半导体衬底1的表面设置有多个p型保护环层5,与p型保护环层5相比在外侧,在半导体衬底1的表面设置有n型沟道截断层6。
绝缘膜7设置于半导体衬底1之上。绝缘膜7例如是硅氧化膜,通过热氧化、CVD或涂敷而形成。另外,绝缘膜7也可以是BPSG或PSG等添加有B或P等的硅氧化膜。
在绝缘膜7通过光刻及蚀刻设置有多个开口8a、8b、8c、8d。开口8a设置于p型阳极层4之上,开口8b设置于p型保护环层5之上,开口8c、8d设置于n型沟道截断层6之上。开口8d配置于开口8c的外侧,环状地包围开口8c。
阳极电极9经由开口8a与p型阳极层4连接。保护环电极10经由开口8b与p型保护环层5连接。沟道截断电极11经由开口8c与n型沟道截断层6连接。该沟道截断电极11是在衬底表面形成的多个电极中的最外周的电极。
阳极电极9、保护环电极10及沟道截断电极11由铝构成。例如,在通过溅射法等对铝膜进行成膜后,通过光刻及蚀刻而加工为这些电极。此外,电极构造可以为铝单体,也可以将阻挡金属材料层叠于铝。
在器件的断开状态下,在p型保护环层5之下的n-型漂移层内部设置沿左右方向延伸的耗尽层。另外,由于通过与p型保护环层5连接的保护环电极10能够将末端区域3的电位稳定化,因此能够抑制半导体装置的耐压降低。
与绝缘膜7相比吸湿率低的绝缘膜12覆盖了绝缘膜7、阳极电极9、保护环电极10及沟道截断电极11。绝缘膜12为最表面的钝化膜,例如由硅氮化膜构成。在从最外周的沟道截断电极11至半导体衬底1的端部为止的区域,绝缘膜12经由开口8d与半导体衬底1直接接触。
为了将阳极电极9与外部电连接,与绝缘膜7同样地通过光刻及蚀刻而在阳极电极9的上方在绝缘膜12设置有开口。此外,也可以在最表面设置聚酰亚胺(PI)、聚苯并恶唑(PBO)等有机保护膜。在该情况下,与绝缘膜12同样地在阳极电极9的上方设置开口。通过有机保护膜能够防止由封装树脂中的填料对芯片造成的损伤。
在通过切割将晶片分离为芯片时,需要防止切割时的裂纹向装置内部的传播和切割机的堵塞。因此,在成为切割区域的半导体衬底1的最外周部分没有形成硅氮化膜、金属膜、聚酰亚胺。但是,仅形成作为硅氧化膜的绝缘膜7以使得在干蚀刻时不会碰到半导体衬底1的表面。在半导体衬底1的背面整个面设置有n型阴极层13。阴极电极14连接于n型阴极层13。
接着,与对比例进行比较而说明本实施方式的效果。图3是表示对比例涉及的半导体装置的剖视图。在对比例中,绝缘膜12没有与半导体衬底1接触。因此,水分从装置端部通过绝缘膜7或通过绝缘膜7和绝缘膜12的界面而浸入装置内部。其结果,装置内部的铝电极受到腐蚀而导致功能受损。
相对于此,在本实施方式中,在从最外周的沟道截断电极11至半导体衬底1的端部为止的区域,吸湿率低的绝缘膜12与半导体衬底1直接接触。通过将绝缘膜7分割,在它们之间配置吸湿率低的绝缘膜12,从而能够防止从装置端部向装置内部的水分浸入。其结果,能够提供可靠性高的半导体装置。另外,由于仅对末端区域3处的绝缘膜7的开口数量进行变更就能够改善耐吸湿性,因此不会产生工序的追加,不会增加制造成本。
图4是表示实施方式1涉及的半导体装置的变形例1的剖视图。在从最外周的沟道截断电极11至半导体衬底1的端部为止的区域,在绝缘膜7将开口8c、8d汇总为一个而设置得大,由吸湿性低的绝缘膜12将开口8c、8d覆盖。由此,能够进一步改善耐吸湿性。但是,在与切割线对应的半导体衬底1的端部留有绝缘膜7。
图5是表示实施方式1涉及的半导体装置的变形例2的剖视图。在绝缘膜12之上形成有由聚酰亚胺等有机绝缘膜构成的第3绝缘膜15。在该情况下,也同样地能够改善开口8d处的水分阻挡耐性。
实施方式2
图6是表示实施方式2涉及的半导体装置的剖视图。在实施方式1中绝缘膜12与半导体衬底1接触,但在本实施方式中绝缘膜16设置于开口8a、8b、8c的侧壁。绝缘膜16例如是硅氮化膜,与绝缘膜7相比吸湿率低。
作为制造方法,首先,在绝缘膜7形成开口8a、8b、8c,然后通过CVD在整个面形成绝缘膜16。然后,通过蚀刻法将在绝缘膜7之上及开口8a、8b、8c的底面成膜的绝缘膜16去除。由此,能够仅在开口8a、8b、8c的侧壁余留绝缘膜16。
此外,在绝缘膜7的所有开口的侧壁设置有绝缘膜16。但是,并不限于此,仅在最外周的开口8c的侧壁设置绝缘膜16也能够防止从装置端部向装置内部的水分浸入。在该情况下,在所有开口形成绝缘膜16后,仅在最外周的开口8c覆盖掩模而进行各向同性蚀刻即可。另外,在开口的尺寸大的情况下,即使在开口的侧壁设置绝缘膜16,也不会在半导体衬底1和金属电极之间发生导通不良。
图7是表示实施方式2涉及的半导体装置的变形例的剖视图。设置有多个用于将沟道截断电极11和半导体衬底1连接的开口8c。通过在该多个开口8c的侧壁设置吸湿率低的绝缘膜16,从而能够进一步抑制向装置内部的水分浸入。
实施方式3
图8是表示实施方式3涉及的半导体装置的剖视图。在实施方式1中绝缘膜12与半导体衬底1接触,但在本实施方式中在绝缘膜7、12之上设置有绝缘膜17。为了将阳极电极9与外部电连接,与绝缘膜12同样地在阳极电极9的上方,在绝缘膜17设置有开口。
绝缘膜17由以芯片保护为目的而通常所使用的聚酰亚胺等有机材料构成,与绝缘膜7相比吸湿率高。因此,绝缘膜7的水分被绝缘膜17吸湿。另外,绝缘膜17具有彼此分离的第1部分17a和第2部分17b。第1部分17a设置于绝缘膜12之上。第2部分17b设置于从最外周的沟道截断电极11至半导体衬底1的端部为止的区域,不经由绝缘膜12而直接与绝缘膜7接触。因此,能够抑制水分通过绝缘膜7内或绝缘膜7、12的界面而传播至装置内部。另外,通过对绝缘膜17进行分割,从而能够抑制水分通过绝缘膜17而传播至装置内部。
此外,半导体衬底1并不限于由硅设置,也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料、或金刚石。由于由上述宽带隙半导体形成的半导体装置的耐压性、容许电流密度高,因此能够小型化。通过使用该小型化的半导体装置,从而组装有该半导体装置的半导体模块也能够小型化、高集成化。另外,由于半导体装置的耐热性高,因此能够将散热器的散热鳍片小型化,能够将水冷部空冷化,因此能够进一步将半导体模块小型化。另外,由于半导体装置的功率损耗低且高效,因此能够使半导体模块高效化。

Claims (6)

1.一种半导体装置,其特征在于,具备:
半导体衬底,其具有设置有器件的单元区域、以及在所述单元区域的周围设置的末端区域;
第1绝缘膜,其在所述末端区域设置于所述半导体衬底之上,具有多个开口;
多个金属电极,它们设置于所述末端区域,经由所述多个开口与所述半导体衬底连接;以及
第2绝缘膜,其覆盖所述第1绝缘膜及所述多个金属电极,与所述第1绝缘膜相比吸湿率低,
在从所述多个金属电极中的最外周的电极至所述半导体衬底的端部为止的区域,所述第2绝缘膜在所述多个开口中的一者与所述半导体衬底直接接触,该接触遍及所述开口的整个宽度。
2.一种半导体装置,其特征在于,具备:
半导体衬底,其具有设置有器件的单元区域、以及在所述单元区域的周围设置的末端区域;
第1绝缘膜,其在所述末端区域设置于所述半导体衬底之上,具有多个开口;
多个金属电极,它们设置于所述末端区域,经由所述多个开口与所述半导体衬底连接;以及
第2绝缘膜,其设置于与所述多个金属电极中的至少最外周的电极对应的所述开口的侧壁,与所述第1绝缘膜相比吸湿率低。
3.一种半导体装置,其特征在于,具备:
半导体衬底,其具有设置有器件的单元区域、以及在所述单元区域的周围设置的末端区域;
第1绝缘膜,其在所述末端区域设置于所述半导体衬底之上,具有多个开口;
多个金属电极,它们设置于所述末端区域,经由所述多个开口与所述半导体衬底连接;
第2绝缘膜,其覆盖所述第1绝缘膜及所述多个金属电极,与所述第1绝缘膜相比吸湿率低;以及
第3绝缘膜,其与所述第1绝缘膜相比吸湿率高,
所述第3绝缘膜具有第1部分和第2部分,该第1部分设置于所述第2绝缘膜之上,该第2部分设置于从所述多个金属电极中的最外周的电极至所述半导体衬底的端部为止的区域,与所述第1部分分离,不经由所述第2绝缘膜而直接与所述第1绝缘膜接触。
4.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
在所述末端区域,在所述半导体衬底的表面设置有p型保护环层,与所述p型保护环层相比在外侧,在所述半导体衬底的表面设置有n型沟道截断层,
所述多个金属电极具有:保护环电极,其与所述p型保护环层连接;以及沟道截断电极,其为所述最外周的电极,与所述n型沟道截断层连接。
5.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
所述半导体衬底由宽带隙半导体形成。
6.根据权利要求4所述的半导体装置,其特征在于,
所述半导体衬底由宽带隙半导体形成。
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JP2021136423A (ja) * 2020-02-28 2021-09-13 富士電機株式会社 半導体装置
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US11600724B2 (en) * 2020-09-24 2023-03-07 Wolfspeed, Inc. Edge termination structures for semiconductor devices
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CN116646384B (zh) * 2023-07-27 2024-03-26 深圳芯能半导体技术有限公司 一种具沟槽场截止结构的igbt芯片及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030181045A1 (en) * 1999-11-26 2003-09-25 Minn Eun-Young Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film
CN102280493A (zh) * 2010-05-26 2011-12-14 三菱电机株式会社 半导体装置
CN106206753A (zh) * 2015-06-01 2016-12-07 通用汽车环球科技运作有限责任公司 包括半导体结构的半导体器件及该半导体器件的制造方法
CN107146813A (zh) * 2016-03-01 2017-09-08 三菱电机株式会社 半导体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4710224B2 (ja) 2003-12-24 2011-06-29 ソニー株式会社 電界効果型トランジスタ及びその製造方法
JP2008053559A (ja) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP5765251B2 (ja) * 2012-01-24 2015-08-19 三菱電機株式会社 半導体装置及びその製造方法
CN105940495B (zh) * 2014-01-29 2019-11-08 三菱电机株式会社 电力用半导体装置
JP6165271B2 (ja) * 2014-01-29 2017-07-19 三菱電機株式会社 電力用半導体装置
JP2016120999A (ja) 2014-12-25 2016-07-07 株式会社椿本チエイン 搬送装置
US10290711B2 (en) * 2015-01-27 2019-05-14 Mitsubishi Electric Corporation Semiconductor device
JP6754120B2 (ja) 2016-10-06 2020-09-09 アイラボ株式会社 プログラム、情報記憶媒体及び文字分割装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030181045A1 (en) * 1999-11-26 2003-09-25 Minn Eun-Young Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film
CN102280493A (zh) * 2010-05-26 2011-12-14 三菱电机株式会社 半导体装置
CN106206753A (zh) * 2015-06-01 2016-12-07 通用汽车环球科技运作有限责任公司 包括半导体结构的半导体器件及该半导体器件的制造方法
CN107146813A (zh) * 2016-03-01 2017-09-08 三菱电机株式会社 半导体装置

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