JP7334678B2 - 半導体装置 - Google Patents
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- JP7334678B2 JP7334678B2 JP2020097745A JP2020097745A JP7334678B2 JP 7334678 B2 JP7334678 B2 JP 7334678B2 JP 2020097745 A JP2020097745 A JP 2020097745A JP 2020097745 A JP2020097745 A JP 2020097745A JP 7334678 B2 JP7334678 B2 JP 7334678B2
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- 239000004065 semiconductor Substances 0.000 title claims description 87
- 239000010410 layer Substances 0.000 claims description 63
- 238000009792 diffusion process Methods 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 43
- 230000001629 suppression Effects 0.000 claims description 40
- 230000015556 catabolic process Effects 0.000 claims description 34
- 230000005684 electric field Effects 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 description 7
- 238000005259 measurement Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000010248 power generation Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Description
図1は、実施の形態1に係る半導体装置を示す上面図である。素子領域1にはダイオードが設けられている。素子領域1の外周に終端領域2とVFモニター領域3が設けられている。VFモニター領域3は、長方形の半導体装置の四隅に設けられている。図2は、VFモニター領域の周辺を拡大した上面図である。なお、図1には1つの半導体装置しか示されていないが、複数の半導体装置がウエハ上に設けられ、ダイシングライン4により互いに区切られている。
VSub=ECSub×W・・・(数式1)
V=EC×D・・・(数式2)
ここで、VSubは半導体基板5内部のアバランシェブレークダウン電圧、ECSubは半導体基板5の絶縁破壊電界強度、Wは空乏層の幅である。数式2のVは放電電圧、ECは二電極間に存在する空気などの物体の絶縁破壊電界強度、Dは二電極間の距離である。
D2<(ECIns/ECSub)×2t+(ECbet/ECSub)×(D1-2t)・・・(数式3)
D3<(ECIns/ECSub)×2t+(ECbet/ECSub)×(D1-2t)・・・(数式4)
ここで、ECbetはモニター電極9の内端部とチャネルストッパ電極11の外端部の間に存在する絶縁膜14以外の物質の絶縁破壊電界強度、ECInsは絶縁膜14の絶縁破壊電界強度、tは絶縁膜14の厚みである。
図6は、実施の形態2に係る半導体装置を示す断面図である。本実施の形態では、実施の形態1の第1空乏化抑制領域7及び第2空乏化抑制領域8の代わりに第1トレンチ16及び第2トレンチ17が設けられている。
Claims (8)
- 半導体素子が設けられた素子領域を有する第1導電型の半導体基板と、
前記素子領域の外周において前記半導体基板の表層に設けられた第2導電型の拡散層と、
前記素子領域の外周において前記半導体基板の表層に設けられ、前記拡散層よりも前記半導体基板の内側に前記拡散層から離れて配置された第1導電型の第1空乏化抑制領域と、
前記第1空乏化抑制領域に電気的に接続されたチャネルストッパ電極と、
前記拡散層に電気的に接続され、前記チャネルストッパ電極から離れているモニター電極と、
前記チャネルストッパ電極の外端部と前記モニター電極の内端部を覆う絶縁膜とを備え、
前記モニター電極の前記内端部が前記拡散層と前記第1空乏化抑制領域の間に位置し、
前記チャネルストッパ電極の前記外端部と前記モニター電極の前記内端部の間隔は第1の距離であり、
前記拡散層と前記第1空乏化抑制領域の間隔は第2の距離であり、
前記チャネルストッパ電極と前記モニター電極の間の放電電圧が前記拡散層と前記半導体基板のPN接合部のアバランシェブレークダウン電圧よりも大きくなるように前記第1の距離及び前記第2の距離が設定されていることを特徴とする半導体装置。 - 前記素子領域の外周において前記半導体基板の表層に設けられ、前記拡散層よりも前記半導体基板の外側に前記拡散層から離れて配置された第1導電型の第2空乏化抑制領域を更に備え、
前記モニター電極の外端部が前記拡散層と前記第2空乏化抑制領域の間に位置し、
前記拡散層と前記第2空乏化抑制領域の間隔は第3の距離であり、
前記放電電圧が前記アバランシェブレークダウン電圧よりも大きくなるように前記第3の距離が設定されていることを特徴とする請求項1に記載の半導体装置。 - 半導体素子が設けられた素子領域を有する第1導電型の半導体基板と、
前記素子領域の外周において前記半導体基板の表層に設けられた第2導電型の拡散層と、
前記素子領域の外周において前記半導体基板の表層に設けられ、前記拡散層よりも前記半導体基板の内側に前記拡散層から離れて配置された第1トレンチと、
前記第1トレンチに電気的に接続されたチャネルストッパ電極と、
前記拡散層に電気的に接続され、前記チャネルストッパ電極から離れているモニター電極と、
前記チャネルストッパ電極の外端部と前記モニター電極の内端部を覆う絶縁膜とを備え、
前記モニター電極の前記内端部が前記拡散層と前記第1トレンチの間に位置し、
前記チャネルストッパ電極の前記外端部と前記モニター電極の前記内端部の間隔は第1の距離であり、
前記拡散層と前記第1トレンチの間隔は第2の距離であり、
前記チャネルストッパ電極と前記モニター電極の間の放電電圧が前記拡散層と前記半導体基板のPN接合部のアバランシェブレークダウン電圧よりも大きくなるように前記第1の距離及び前記第2の距離が設定されていることを特徴とする半導体装置。 - 前記素子領域の外周において前記半導体基板の表層に設けられ、前記拡散層よりも前記半導体基板の外側に前記拡散層から離れて配置された第2トレンチを更に備え、
前記モニター電極の外端部が前記拡散層と前記第2トレンチの間に位置し、
前記拡散層と前記第2トレンチの間隔は第3の距離であり、
前記放電電圧が前記アバランシェブレークダウン電圧よりも大きくなるように前記第3の距離が設定されていることを特徴とする請求項3に記載の半導体装置。 - 前記第1の距離をD1、前記第2の距離をD2、前記絶縁膜の絶縁破壊電界強度をECIns、前記半導体基板の絶縁破壊電界強度をECSub、前記絶縁膜の厚みをt、前記チャネルストッパ電極の前記外端部と前記モニター電極の前記内端部の間に存在する前記絶縁膜以外の物質の絶縁破壊電界強度をECbetとして、
D2<(ECIns/ECSub)×2t+(ECbet/ECSub)×(D1-2t)
を満たすことを特徴とする請求項1~4の何れか1項に記載の半導体装置。 - 前記第1の距離をD1、前記第3の距離をD3、前記絶縁膜の絶縁破壊電界強度をECIns、前記半導体基板の絶縁破壊電界強度をECSub、前記絶縁膜の厚みをt、前記チャネルストッパ電極の前記外端部と前記モニター電極の前記内端部の間に存在する前記絶縁膜以外の物質の絶縁破壊電界強度をECbetとして、
D3<(ECIns/ECSub)×2t+(ECbet/ECSub)×(D1-2t)
を満たすことを特徴とする請求項2又は4に記載の半導体装置。 - 前記拡散層の不純物濃度は前記半導体基板の不純物濃度よりも低いことを特徴とする請求項1~6の何れか1項に記載の半導体装置。
- 前記半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1~7の何れか1項に記載の半導体装置。
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JP2020097745A JP7334678B2 (ja) | 2020-06-04 | 2020-06-04 | 半導体装置 |
US17/108,070 US11527449B2 (en) | 2020-06-04 | 2020-12-01 | Semiconductor apparatus |
DE102021102057.3A DE102021102057A1 (de) | 2020-06-04 | 2021-01-29 | Halbleitereinrichtung |
CN202110592345.0A CN113764508B (zh) | 2020-06-04 | 2021-05-28 | 半导体装置 |
US17/937,846 US20230028753A1 (en) | 2020-06-04 | 2022-10-04 | Semiconductor apparatus |
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JP2021190663A (ja) | 2021-12-13 |
US20230028753A1 (en) | 2023-01-26 |
US11527449B2 (en) | 2022-12-13 |
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