CN111081770A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN111081770A
CN111081770A CN201910967906.3A CN201910967906A CN111081770A CN 111081770 A CN111081770 A CN 111081770A CN 201910967906 A CN201910967906 A CN 201910967906A CN 111081770 A CN111081770 A CN 111081770A
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gate electrode
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semiconductor device
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CN111081770B (zh
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上马场龙
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于，就在1个半导体衬底同时设置了晶体管区域和二极管区域的半导体装置而言，提供能够在二极管动作时实现良好的电气特性的半导体装置。半导体装置的特征在于，具备在具有正面和背面的半导体衬底设置的IGBT区域和二极管区域，该IGBT区域具备：第2导电型的基极层，其形成于该正面侧；以及第1沟槽部，其贯通该基极层而设置，该第1沟槽部具有：第1栅极电极，其下端与该基极层的下端相比位于上方；第2栅极电极，其设置于该第1栅极电极的正下方；以及绝缘膜，其设置于该第1栅极电极的侧面、该第1栅极电极和该第2栅极电极之间以及与该第2栅极电极接触的位置。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
在家电产品、电动汽车、或铁路等广泛的领域中使用的逆变器装置大多是对感应电动机等电感性负载进行驱动。逆变器装置能够使用多个半导体装置而构成，该半导体装置例如是IGBT(Insulated Gate Bipolar Transistor)或MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)等开关元件、以及续流二极管(以下，有时简称为二极管)等。逆变器装置谋求高效率且省电，因此市场上要求半导体装置的高性能化和低成本化。
为了电力用半导体装置的高性能化和低成本化，开发了沟槽MOS栅极构造、半导体衬底的薄板化、以及反向导通型IGBT(RC-IGBT：Reverse Conducting IGBT)等。RC-IGBT是将IGBT和二极管内置于同一半导体衬底而一体化得到的。
在专利文献1中公开了具有沟槽栅极构造的半导体装置。该半导体装置具备：第1导电型的半导体衬底；第1导电型的积蓄层，其形成于该半导体衬底的正面侧，杂质浓度比该半导体衬底的杂质浓度高；以及沟槽部，其形成于该半导体衬底的正面。该沟槽部具有：第1导电部；第2导电部，其位于该第1导电部的下方，与该积蓄层的深度方向的中心位置相比形成于下方；以及绝缘膜，其将该第1导电部的侧面以及该第2导电部的周围覆盖，该沟槽部具有以下两种构造中的至少一者，即，该绝缘膜将该第1导电部与该第2导电部之间绝缘的分隔构造，或者，与该第1导电部的侧面相比在该第2导电部的侧面该绝缘膜形成得更厚的厚膜构造。
专利文献1：日本特开2017-147431号公报
能够在RC-IGBT的IGBT区域，在半导体衬底的正面侧设置沟槽栅极、栅极电极、p+型扩散层、p型基极层、n+型发射极层以及发射极电极。并且，能够在半导体衬底的背面侧设置n型缓冲层、p型集电极层以及集电极(collector)电极(electrode)。
能够在RC-IGBT的二极管区域，在半导体衬底的正面侧设置杂质浓度低的p-型阳极层和阳极电极。阳极电极能够与发射极电极是共通的。并且，能够在半导体衬底的背面侧设置n型缓冲层、n+型阴极层以及阴极电极。阴极电极能够与集电极电极是共通的。在IGBT区域和二极管区域，在正面侧的结构和背面侧的结构之间存在n-型漂移层。
就RC-IGBT而言，IGBT和二极管配置于同一衬底，因此相邻的IGBT和二极管相互影响。例如，在使二极管动作时，如果向IGBT的栅极电极施加正的偏置电压，则在p型基极层之中形成反转层即n型沟道层。由此，n+型阴极层、n型缓冲层、n-型漂移层、n型沟道层以及n+型发射极层电连接，进行MOSFET动作。如此，在二极管动作时，电子载流子不在漂移层积蓄而是流入IGBT区域。由此，不会正常地进行双极动作而是引起骤回，因此二极管的输出特性劣化，或导通电压恶化。
就例如专利文献1所提出的构造而言，在二极管动作时，在向第1导电部施加了正偏置的情况下，电子载流子通过IGBT的沟道路径而被排出，有可能不会正常地进行双极动作。
发明内容
本发明就是为了解决上述这样的课题而提出的，其目的在于，就在1个半导体衬底同时设置了晶体管区域和二极管区域的半导体装置而言，提供能够在二极管动作时实现良好的电气特性的半导体装置。
本发明涉及的半导体装置的特征在于，具备：IGBT区域，其从具有第1导电型的漂移层的半导体衬底的正面延伸到背面；以及二极管区域，其从该半导体衬底的该正面延伸到该背面，与该IGBT区域相邻，该IGBT区域具备：第2导电型的基极层，其形成于该正面侧；以及第1沟槽部，其贯通该基极层而设置，该第1沟槽部具有：第1栅极电极，其下端与该基极层的下端相比位于上方；第2栅极电极，其设置于该第1栅极电极的正下方；以及绝缘膜，其设置于该第1栅极电极的侧面、该第1栅极电极和该第2栅极电极之间以及与该第2栅极电极接触的位置，该二极管区域具备：第2导电型的阳极层，其形成于该正面侧；以及第2沟槽部，其形成于该正面侧，具有哑栅极电极。
本发明的其它特征在下面得以明确。
发明的效果
根据本发明，在晶体管区域的1个沟槽部设置第1栅极电极以及在第1栅极电极的正下方与第1栅极电极绝缘地设置的第2栅极电极，使第1栅极电极的下端与基极层的下端相比位于上方。如果向第2栅极电极施加负的偏置电压，则在漂移层形成p型反转层即保护层，在使二极管为导通状态时，在向第1栅极电极施加了正的偏置电压的状态下，能够防止或者抑制电子载流子流入至晶体管区域。
附图说明
图1是实施方式1涉及的半导体装置的剖面图。
图2是从正面侧观察半导体装置的俯视图。
图3是从背面侧观察半导体装置的俯视图。
图4是图2的B-B′线处的剖面图。
图5是表示骤回现象的图。
图6是施加了电压的半导体装置的剖面图。
图7是施加了电压的半导体装置的剖面图。
图8是表示二极管的MOS特性的模拟结果的图。
图9是实施方式2涉及的半导体装置的俯视图。
图10是半导体装置的局部剖面图。
图11是实施方式3涉及的半导体装置的剖面图。
图12是实施方式4涉及的半导体装置的剖面图。
标号的说明
10半导体装置，11 IGBT区域，12二极管区域，13漂移层，14基极层，19第1沟槽部，28第2沟槽部，36第1栅极电极，37第2栅极电极，39载流子积蓄层，41沟道层，42保护层，50第1电极焊盘，52第2电极焊盘。
具体实施方式
下面，一边参照附图一边对实施方式进行说明。附图是示意性地示出的，因此尺寸以及位置的相互关系可以变更。在下面的说明中，对相同或者相应的结构要素标注相同的标号，有时省略重复的说明。在下面的说明中，有时会使用“上”、“下”、“侧”、“底”、“表(正)”或者“背”等表示特定的位置以及方向的术语，但这些术语是为了使实施方式的内容容易理解，出于方便而使用的，并不对实际实施时的方向进行限定。对于半导体的导电型，使第1导电型为n型，使第2导电型为p型而进行说明。但是，也可以使它们相反，使第1导电型为p型，使第2导电型为n型。n+型意味着与n型相比施主杂质的浓度高，n-型意味着与n型相比施主杂质的浓度低。同样地，p+型意味着与p型相比受主杂质的浓度高，p-型意味着与p型相比受主杂质的浓度低。
实施方式1.
图1是实施方式1涉及的半导体装置10的剖面图。该半导体装置10是RC-IGBT。半导体装置10具备半导体衬底40。半导体衬底40具备第1主面即正面40A以及与第1主面相对的第2主面即背面40B。半导体衬底40具有第1导电型的漂移层13。在1个半导体衬底40设置有IGBT区域11和二极管区域12。IGBT区域11从半导体衬底40的正面40A延伸到背面40B。二极管区域12也从半导体衬底40的正面40A延伸到背面40B。IGBT区域11和二极管区域12相邻。
图2是从正面40A侧观察半导体装置10的俯视图。在IGBT区域11存在n+型发射极层16、p+型扩散层15以及第1沟槽部19。发射极层16和扩散层15以岛状设置有多个。第1沟槽部19以直线型设置有多个。在二极管区域12存在p-型阳极层29以及第2沟槽部28。第2沟槽部28以直线型设置有多个。此外，穿过图2的发射极层16的A-A′线处的剖面图是图1。
图3是从背面40B侧观察半导体装置10的俯视图。在IGBT区域11存在p型集电极层25。在二极管区域12存在n+型阴极层30。
对IGBT区域11的结构例进行说明。在IGBT区域11，如图2所示存在p+型扩散层15和n+型发射极层16，并且如图1所示存在n-型漂移层13、p型基极层14以及第1沟槽部19。基极层14设置于n-型漂移层13的上表面。即，在正面40A侧存在p型基极层14。在该基极层14的上表面选择性地形成有p+型扩散层15或者n+型发射极层16。n+型发射极层16能够在俯视观察时包围p+型扩散层15而形成。
第1沟槽部19贯通基极层14而设置。第1沟槽部19如图1所示，具备第1栅极电极36、第2栅极电极37以及绝缘膜18。第1栅极电极36和第2栅极电极37在1个沟槽分设于上下。能够使第1栅极电极36和第2栅极电极37例如为多晶硅等导电材料。第1栅极电极36隔着绝缘膜18而与基极层14相对。绝缘膜18的材料例如是SiO2。在第1栅极电极36的正下方设置有第2栅极电极37。第1栅极电极36的下端与基极层14的下端相比位于上方。例如，也可以使第2栅极电极37的上端的部分隔着绝缘膜18而与基极层14相对。
绝缘膜18能够设置于第1栅极电极36的侧面、第1栅极电极36和第2栅极电极37之间以及与第2栅极电极37接触的位置。绝缘膜18例如具备：第1部分18a，其设置于第1栅极电极36的侧面；第2部分18b，其设置于第1栅极电极36和第2栅极电极37之间；以及第3部分18c，其与第2栅极电极37接触，将第2栅极电极37的侧面和下端部覆盖。
第1沟槽部19在俯视观察时在形成了n+型发射极层16的部分，如图1所示贯通发射极层16和基极层14而到达漂移层13，但在俯视观察时在形成了p+型扩散层15的部分，贯通扩散层15和基极层14而到达漂移层13。图4是穿过图2的扩散层15的B-B′线处的剖面图。图4中图示了第1沟槽部19贯通扩散层15和基极层14而到达漂移层13。
作为IGBT区域11的表面构造，例如形成有图1所示的发射极电极20、层间绝缘膜21以及阻挡金属23。层间绝缘膜21覆盖第1沟槽部19，由此实现第1栅极电极36和发射极电极20的绝缘。在层间绝缘膜21形成有接触孔22。通过接触孔22，p+型扩散层15和n+型发射极层16的一部分从层间绝缘膜21露出。并且，在层间绝缘膜21之上和接触孔22的内部形成有阻挡金属23。阻挡金属23在接触孔22处与扩散层15以及发射极层16的上表面接触。阻挡金属23通过与硅半导体接触，从而硅化物化，降低与发射极层16以及扩散层15的接触电阻。
为了实现设计规则的细微化，能够在阻挡金属23之上形成钨插塞。在对接触孔22使用钨插塞的情况下，阻挡金属23可以设为过渡金属以得到上述效果。例如阻挡金属23能够设为具有钛或者氮化钛的多层构造。在阻挡金属23或者阻挡金属23和钨插塞之上形成发射极电极20。发射极电极20能够由例如铝或者铝合金而形成。发射极电极20经由阻挡金属23而与n+型发射极层16接触，经由阻挡金属23而与p+型扩散层15接触。
作为IGBT区域11的背面构造，能够形成n型缓冲层24、p型集电极层25以及集电极电极26。缓冲层24设置于漂移层13的下表面，集电极层25设置于缓冲层24的下表面。
具有这样的IGBT区域11的RC-IGBT即半导体装置10能够通过具有p型基极层14、p+型扩散层15、绝缘膜18以及第1栅极电极36的沟槽MOS栅极构造而实现高沟道密度。并且，能够通过使n-型漂移层13变薄而实现低损耗化。如果使n-型漂移层13变薄，则需要在IGBT的断开时从p型基极层14与n-型漂移层13的pn结延伸的耗尽层的阻挡件。作为这样的阻挡件而设置与n-型漂移层13相比杂质浓度高的n型缓冲层24。此外，缓冲层24的有无是根据制品用途而决定的，能够根据制品用途而省略。
在IGBT的导通时，由n-型漂移层13、p型基极层14、n+型发射极层16、绝缘膜18以及第1栅极电极36形成n沟槽MOSFET，在p型集电极层25、n型缓冲层24、n-型漂移层13、p型基极层14、p+型扩散层15的路径中流过电流。即，n-型漂移层13、p型基极层14、n+型发射极层16、绝缘膜18以及第1栅极电极36是沟槽MOS栅极构造，这样的沟槽MOS栅极构造形成有多个。此外，p+型扩散层15具有清除在断开时产生的载流子，以及降低与发射极电极20的接触电阻的效果。以上是IGBT区域11的结构。
接下来，对二极管区域12的结构例进行说明。半导体衬底40在二极管区域12具备n-型漂移层13、第2沟槽部28以及p-型阳极层29。该漂移层13存在于IGBT区域11和二极管区域12两者。在二极管区域12，在漂移层13之上形成有阳极层29。即，在正面40A侧存在p-型阳极层29。形成有从阳极层29的上表面贯通阳极层29而到达漂移层13的多个第2沟槽部28。第2沟槽部28具备哑栅极绝缘膜28a以及与哑栅极绝缘膜28a接触的哑栅极电极28b。哑栅极电极28b例如能够设为多晶硅等导电材料。这样，在正面40A侧设置有第2沟槽部28。
作为二极管区域12的表面构造而设置有发射极电极20。发射极电极20是在IGBT区域11和二极管区域12共通地使用的电极。发射极电极20的材料例如是铝或者铝合金。通过在IGBT区域11和二极管区域12共用发射极电极20，从而能够在使用了半导体装置10的装配工艺中，使导线键合或者焊料润湿性的条件在IGBT区域11与二极管区域12相同。p-型阳极层29的p型杂质浓度低，因而能够得到良好的二极管特性。但是，如果使p-型阳极层29与阻挡金属23接触，则成为肖特基结，接触电阻变大。因此，根据一个例子，不在二极管区域12设置阻挡金属23。在使阻挡金属23与阳极层29接触的情况下，如果使p-型阳极层29的p型杂质浓度变高，则能够实现欧姆接触。
作为二极管区域12的背面构造，设置有n型缓冲层24、n+型阴极层30以及集电极电极26。n型缓冲层24和集电极电极26能够在IGBT区域11和二极管区域12共通地使用。
对二极管的导通时的动作进行说明。如果向发射极电极20与集电极电极26之间施加正的电压，则从p-型阳极层29向漂移层13注入空穴载流子，从n+型阴极层30向漂移层13注入电子载流子。并且，如果施加电压变为大于或等于电压降，则二极管成为导通状态。如果二极管成为导通状态，则在发射极电极20、p-型阳极层29、n-型漂移层13、n+型阴极层30、集电极电极26的路径中流过电流。
接下来，对二极管的断开时的动作进行说明。通常，二极管在从导通向断开切换时进行恢复动作。恢复动作是指在电流暂时流过二极管的负电压侧之后，返回至断开状态的动作，将该期间称为逆恢复时间。并且，将在逆恢复时间内产生的负电流的峰值称为恢复电流，将产生的损耗称为恢复损耗。
考虑在IGBT区域11没有绝缘膜18的第2部分18b，在1个第1沟槽部设置了1个栅极电极(后面，称为一体型栅极电极)的情况。在这种情况下，如果在二极管的导通动作时向该一体型栅极电极施加正的偏置电压，则在p型基极层14形成n型沟道层，阴极层30、缓冲层24、漂移层13、沟道层以及n+型发射极层16电连接。这与单极器件的MOSFET动作类似，从阴极层30向漂移层13提供的电子载流子经由沟道层而向IGBT区域11流入。并且，如果电子载流子不在漂移层13积蓄而是向IGBT区域11大量地流入，则二极管不会正常地导通而是引起骤回。
图5是表示这样的骤回的图。横轴是Vak(阳极阴极间电压)或者Vec(发射极集电极间电压)，纵轴是Ia(阳极电流)或者Iec(发射极集电极电流)。由虚线示出的波形C2是在二极管的导通动作时向一体型栅极电极施加了正的偏置电压的情况下的二极管输出波形的模拟结果。正的偏置电压是指使栅极-发射极间电压Vge为15V。由实线示出的波形C1是在二极管的导通动作时未向一体型栅极电极施加正的偏置电压的情况下的二极管输出波形的模拟结果。根据图5，可知通过向一体型栅极电极施加正的偏置电压，从而在低电压时通过MOSFET动作而流过电流。
就实施方式1涉及的半导体装置10而言，第1沟槽部19具有分离的上下2层的栅极电极。具体地说，在1个第1沟槽部19设置分离的第1栅极电极36和第2栅极电极37。通过绝缘膜18的第2部分18b而将第1栅极电极36和第2栅极电极37绝缘。即，第1栅极电极36和第2栅极电极37电绝缘，因而能够使它们为不同电压。例如，还能够向第1栅极电极36输入栅极驱动电压，使第2栅极电极37为栅极电位、发射极电位或者浮置电位。
通过向第2栅极电极37施加负的偏置电压，从而能够使漂移层13与沟道层的连接切断或者高电阻化。通过使漂移层13与沟道层的连接切断或者高电阻化，从而能够防止二极管的正向动作时的骤回，以及VF值向变大的方向移位。在将±15V电源用于向第1栅极电极36和第2栅极电极37施加电压的情况下，第1栅极电极36与第2栅极电极37的电位差为最大即30V，绝缘膜18应为能够耐受30V电位差的程度的膜厚。如果使以SiO2为材料的绝缘膜的绝缘破坏电场强度为10×106V/cm，则相对于30V需要大于或等于0.03μm的膜厚。因此，在使绝缘膜18的材料为SiO2的情况下，使第2部分18b的厚度例如大于或等于0.03μm。换言之，在第1栅极电极36与第2栅极电极37之间，能够使绝缘膜的膜厚大于或等于0.03μm。
图6是表示向第1栅极电极36施加了正电压，向第2栅极电极37施加了负电压的状态的半导体装置的剖面图。在这种情况下，在第1栅极电极36的周围隔着绝缘膜18的第1部分18a而形成n型沟道层41，在第2栅极电极37的周围隔着绝缘膜18的第3部分18c而形成p型保护层42。通过形成p型保护层42，从而能够使漂移层13与沟道层41的电连接切断或者高电阻化。将第1栅极电极36的下端与基极层14的下端相比设置于上方这一做法会使得在漂移层13与沟道层41之间提供保护层42变得容易。根据需要，通过例如将第2栅极电极37的上端与基极层14的下端相比设置于上方，从而能够使向漂移层13与沟道层41之间的保护层42的提供变得可靠。
图7是表示向第1栅极电极36施加了正电压，向第2栅极电极37施加了负电压，同时向发射极电极20施加了正的偏置电压的半导体装置的剖面图。图7示出使二极管进行了导通动作的情况。此时，IGBT区域11的p型基极层14和n型漂移层13的pn二极管导通，空穴载流子43在路径44中流过二极管区域12。
例如，在向第1栅极电极36施加了正的偏置电压，向第2栅极电极37施加了负的偏置电压的情况下，得到由图5的波形C1表示的正常的双极动作。另一方面，在向第1栅极电极36施加了正的偏置电压，未向第2栅极电极37施加电压的情况下，在低电流区域流过MOS电流，产生由图5的波形C2表示的骤回。这样的不同是由p型保护层42的有无引起的。即，能够通过保护层42而使沟道层41与漂移层13之间的电连接切断或者高电阻化。
图8是表示实施方式1涉及的半导体装置10的二极管的MOS特性(Vge-Ic)的模拟结果的图。对从p型基极层14的下端到第1栅极电极36的下端为止的距离X不同的3个器件实施了模拟。曲线C1示出以X＝0.1μm的半导体装置得到的模拟结果，曲线C2示出以X＝0.2μm的半导体装置得到的模拟结果，曲线C3示出以X＝0.3μm的半导体装置得到的模拟结果。就曲线C1、C2而言，正常地流过集电极电流Ic，但就曲线C3而言，斜率小，动作异常。因此，为了能够进行IGBT的动作，使从p型基极层14的下端到第1栅极电极36的下端为止的距离X例如小于0.3μm。换言之，第1栅极电极36的下端能够形成于与基极层14的下端相比以小于0.3μm的量更靠上方处。
如上所述，根据实施方式1的半导体装置10，即使在二极管动作时向第1栅极电极36施加了正的偏置电压，也会正常地进行双极动作，得到良好的二极管输出特性。
下面，由于实施方式涉及的半导体装置与实施方式1的共通点多，因而以与实施方式1的不同点为中心进行说明。
实施方式2.
图9是实施方式2涉及的半导体装置的俯视图。该半导体装置具备电绝缘的发射极电极20、第1电极焊盘50以及第2电极焊盘52。在半导体装置的外缘以环状设置有终端区域46。
图10是包含图9的第1电极焊盘50和第2电极焊盘52在内的部分处的半导体装置的剖面图。第1电极焊盘50与第1栅极电极36电连接。第2电极焊盘52与第2栅极电极37电连接。第1电极焊盘50和第2电极焊盘52设置于半导体衬底40的上方。上述电极焊盘例如是铝合金。图10示出电绝缘的第1栅极电极36和第2栅极电极37的绕引的一个例子。分离的第1电极焊盘50和第2电极焊盘52能够使第1栅极电极36和第2栅极电极37的电位不同。
例如，通过向第2栅极电极37施加负的偏置电压，从而能够使漂移层13与沟道层的连接切断或者高电阻化。这样的负的偏置电压仅在需要使漂移层13与沟道层的连接切断或者高电阻化时施加，由此能够避免始终施加负的偏置电压。例如，在将IGBT导通时，向第1栅极电极36施加栅极驱动电压而形成沟道层，同时不向第2栅极电极37施加电压。
实施方式3.
图11是实施方式3涉及的半导体装置的剖面图。在IGBT区域11，在基极层14的下方设置有n型载流子积蓄层39。载流子积蓄层39的n型的杂质浓度比漂移层13的n型的杂质浓度高。例如，载流子积蓄层39也可以形成于IGBT区域11的整体。由此，在IGBT导通时，p型基极层14和n-型漂移层13的导通电阻下降，因此能够降低稳态损耗。
实施方式4.
图12是实施方式4涉及的半导体装置的剖面图。第2沟槽部28具有第1哑栅极电极28A以及设置于第1哑栅极电极28A的正下方的第2哑栅极电极28B。第2沟槽部28还具备二极管区域绝缘膜28C。二极管区域绝缘膜28C能够设置于第1哑栅极电极28A的侧面、第1哑栅极电极28A和第2哑栅极电极28B之间以及与第2哑栅极电极28B接触的位置。这样，能够使第2沟槽部28和第1沟槽部19为相同形状以及材料。如此，能够使IGBT和二极管的沟槽以及内部电极通过同一工艺而形成，因此能够降低制造成本。

Claims (10)

1.一种半导体装置，其特征在于，具备：
IGBT区域，其从具有第1导电型的漂移层的半导体衬底的正面延伸到背面；以及
二极管区域，其从所述半导体衬底的所述正面延伸到所述背面，与所述IGBT区域相邻，
所述IGBT区域具备：第2导电型的基极层，其形成于所述正面侧；以及第1沟槽部，其贯通所述基极层而设置，
所述第1沟槽部具有：第1栅极电极，其下端与所述基极层的下端相比位于上方；第2栅极电极，其设置于所述第1栅极电极的正下方；以及绝缘膜，其设置于所述第1栅极电极的侧面、所述第1栅极电极和所述第2栅极电极之间以及与所述第2栅极电极接触的位置，
所述二极管区域具备：第2导电型的阳极层，其形成于所述正面侧；以及第2沟槽部，其形成于所述正面侧，具有哑栅极电极。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第1栅极电极的下端与所述基极层的下端相比形成于以小于0.3μm的量更靠上方处。
3.根据权利要求1或2所述的半导体装置，其特征在于，具备：
第1电极焊盘，其与所述第1栅极电极电连接，设置于所述半导体衬底的上方；以及
第2电极焊盘，其与所述第2栅极电极电连接，设置于所述半导体衬底的上方。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
所述第2栅极电极的上端与所述基极层的下端相比位于上方。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
所述哑栅极电极具有第1哑栅极电极以及设置于所述第1哑栅极电极的正下方的第2哑栅极电极，
所述第2沟槽部具备二极管区域绝缘膜，该二极管区域绝缘膜设置于所述第1哑栅极电极的侧面、所述第1哑栅极电极和所述第2哑栅极电极之间以及与所述第2哑栅极电极接触的位置。
6.根据权利要求1至5中任一项所述的半导体装置，其特征在于，
在所述基极层的下方具备杂质浓度比所述半导体衬底的杂质浓度高的第1导电型的载流子积蓄层。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
在所述第1栅极电极和所述第2栅极电极之间，所述绝缘膜的膜厚大于或等于0.03μm。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，
所述第2栅极电极隔着所述绝缘膜而与所述基极层相对。
9.一种半导体装置，其特征在于，具备：
IGBT区域，其从具有第1导电型的漂移层的半导体衬底的正面延伸到背面；以及
二极管区域，其从所述半导体衬底的所述正面延伸到所述背面，与所述IGBT区域相邻，
所述IGBT区域具备：第2导电型的基极层，其形成于所述正面侧；以及第1沟槽部，其贯通所述基极层而设置，
所述第1沟槽部具有：第1栅极电极；第2栅极电极，其设置于所述第1栅极电极的正下方；以及绝缘膜，其设置于所述第1栅极电极的侧面、所述第1栅极电极和所述第2栅极电极之间以及与所述第2栅极电极接触的位置，所述第2栅极电极的上端与所述基极层的下端相比位于上方。
10.根据权利要求9所述的半导体装置，其特征在于，
所述二极管区域具备：第2导电型的阳极层，其形成于所述正面侧；以及第2沟槽部，其形成于所述正面侧，具有哑栅极电极。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115377213A (zh) * 2022-10-25 2022-11-22 烟台台芯电子科技有限公司 一种沟槽型半导体装置及其制作方法
CN117650166A (zh) * 2023-10-31 2024-03-05 海信家电集团股份有限公司 半导体装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7325301B2 (ja) * 2019-11-01 2023-08-14 三菱電機株式会社 半導体装置およびその製造方法
JP2022015781A (ja) 2020-07-10 2022-01-21 三菱電機株式会社 半導体装置
CN111739936B (zh) * 2020-08-07 2020-11-27 中芯集成电路制造(绍兴)有限公司 一种半导体器件及其形成方法
WO2023157395A1 (ja) * 2022-02-18 2023-08-24 ローム株式会社 半導体装置およびその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102165594A (zh) * 2008-09-29 2011-08-24 飞兆半导体公司 在金属衬底上的半导体异质结构中具有应变沟道的功率mosfet
US20150318385A1 (en) * 2012-12-05 2015-11-05 Toyota Jidosha Kabushiki Kaisha Semiconductor device
JP5831598B2 (ja) * 2010-12-08 2015-12-09 株式会社デンソー 絶縁ゲート型半導体装置
JP2017147431A (ja) * 2016-02-12 2017-08-24 富士電機株式会社 半導体装置

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6870220B2 (en) * 2002-08-23 2005-03-22 Fairchild Semiconductor Corporation Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
AU2003228073A1 (en) 2002-05-31 2003-12-19 Koninklijke Philips Electronics N.V. Trench-gate semiconductor device,corresponding module and apparatus ,and method of operating the device
US7504690B2 (en) * 2002-10-04 2009-03-17 Nxp B.V. Power semiconductor devices
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
CN102738239A (zh) * 2005-05-26 2012-10-17 飞兆半导体公司 沟槽栅场效应晶体管及其制造方法
DE102006036347B4 (de) * 2006-08-03 2012-01-12 Infineon Technologies Austria Ag Halbleiterbauelement mit einer platzsparenden Randstruktur
US9252251B2 (en) * 2006-08-03 2016-02-02 Infineon Technologies Austria Ag Semiconductor component with a space saving edge structure
JP2008311300A (ja) * 2007-06-12 2008-12-25 Toyota Motor Corp パワー半導体装置、パワー半導体装置の製造方法、およびモータ駆動装置
EP2003694B1 (en) * 2007-06-14 2011-11-23 Denso Corporation Semiconductor device
DE102007037858B4 (de) * 2007-08-10 2012-04-19 Infineon Technologies Ag Halbleiterbauelement mit verbessertem dynamischen Verhalten
US7875951B2 (en) * 2007-12-12 2011-01-25 Infineon Technologies Austria Ag Semiconductor with active component and method for manufacture
JP5206541B2 (ja) * 2008-04-01 2013-06-12 株式会社デンソー 半導体装置およびその製造方法
JP4788734B2 (ja) * 2008-05-09 2011-10-05 トヨタ自動車株式会社 半導体装置
US8039877B2 (en) * 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric
JP4957840B2 (ja) * 2010-02-05 2012-06-20 株式会社デンソー 絶縁ゲート型半導体装置
JP6008377B2 (ja) * 2010-03-03 2016-10-19 ルネサスエレクトロニクス株式会社 Ｐチャネル型パワーｍｏｓｆｅｔ
US9252239B2 (en) * 2014-05-31 2016-02-02 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
JP5768395B2 (ja) * 2010-07-27 2015-08-26 株式会社デンソー 半導体装置およびその制御方法
DE102011079747A1 (de) * 2010-07-27 2012-02-02 Denso Corporation Halbleitervorrichtung mit Schaltelement und Freilaufdiode, sowie Steuerverfahren hierfür
US9048282B2 (en) * 2013-03-14 2015-06-02 Alpha And Omega Semiconductor Incorporated Dual-gate trench IGBT with buried floating P-type shield
US8441046B2 (en) 2010-10-31 2013-05-14 Alpha And Omega Semiconductor Incorporated Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances
US9666666B2 (en) * 2015-05-14 2017-05-30 Alpha And Omega Semiconductor Incorporated Dual-gate trench IGBT with buried floating P-type shield
JP5594276B2 (ja) * 2010-12-08 2014-09-24 株式会社デンソー 絶縁ゲート型半導体装置
US8569780B2 (en) * 2011-09-27 2013-10-29 Force Mos Technology Co., Ltd. Semiconductor power device with embedded diodes and resistors using reduced mask processes
JP5488687B2 (ja) * 2011-09-28 2014-05-14 トヨタ自動車株式会社 半導体装置およびその製造方法
JP2013251395A (ja) 2012-05-31 2013-12-12 Denso Corp 半導体装置
JP2014060362A (ja) 2012-09-19 2014-04-03 Toshiba Corp 半導体装置
US8772865B2 (en) * 2012-09-26 2014-07-08 Semiconductor Components Industries, Llc MOS transistor structure
DE112012007249B4 (de) * 2012-12-20 2021-02-04 Denso Corporation Halbleitervorrichtung
US9391149B2 (en) * 2013-06-19 2016-07-12 Infineon Technologies Austria Ag Semiconductor device with self-charging field electrodes
JP6158058B2 (ja) * 2013-12-04 2017-07-05 株式会社東芝 半導体装置
US9543389B2 (en) * 2013-12-11 2017-01-10 Infineon Technologies Ag Semiconductor device with recombination region
JP2016058654A (ja) * 2014-09-11 2016-04-21 株式会社東芝 半導体装置
JP6720569B2 (ja) * 2015-02-25 2020-07-08 株式会社デンソー 半導体装置
CN107636836B (zh) * 2015-12-11 2020-11-27 富士电机株式会社 半导体装置
JP6407455B2 (ja) * 2016-01-19 2018-10-17 三菱電機株式会社 半導体装置
US10439054B2 (en) * 2017-06-29 2019-10-08 Kabushiki Kaisha Toshiba Insulated gate bipolar transistor
US11081554B2 (en) * 2017-10-12 2021-08-03 Semiconductor Components Industries, Llc Insulated gate semiconductor device having trench termination structure and method
JP2019145708A (ja) * 2018-02-22 2019-08-29 株式会社東芝 半導体装置
CN108389901B (zh) * 2018-04-24 2020-07-31 四川大学 一种载流子存储增强型超结igbt

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102165594A (zh) * 2008-09-29 2011-08-24 飞兆半导体公司 在金属衬底上的半导体异质结构中具有应变沟道的功率mosfet
JP5831598B2 (ja) * 2010-12-08 2015-12-09 株式会社デンソー 絶縁ゲート型半導体装置
US20150318385A1 (en) * 2012-12-05 2015-11-05 Toyota Jidosha Kabushiki Kaisha Semiconductor device
JP2017147431A (ja) * 2016-02-12 2017-08-24 富士電機株式会社 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115377213A (zh) * 2022-10-25 2022-11-22 烟台台芯电子科技有限公司 一种沟槽型半导体装置及其制作方法
CN115377213B (zh) * 2022-10-25 2023-02-28 烟台台芯电子科技有限公司 一种沟槽型半导体装置及其制作方法
CN117650166A (zh) * 2023-10-31 2024-03-05 海信家电集团股份有限公司 半导体装置

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