WO2016098199A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2016098199A1 WO2016098199A1 PCT/JP2014/083418 JP2014083418W WO2016098199A1 WO 2016098199 A1 WO2016098199 A1 WO 2016098199A1 JP 2014083418 W JP2014083418 W JP 2014083418W WO 2016098199 A1 WO2016098199 A1 WO 2016098199A1
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Definitions
- the present invention relates to a reverse conducting IGBT (RC (Reverse Conducting) -IGBT) in which an FWD (Free Wheeling Diode) is incorporated in an IGBT (Insulated Gate Bipolar Transistor).
- RC Reverse Conducting
- FWD Free Wheeling Diode
- RC-IGBT can be realized by the combination of IGBT and FWD made of Si, which has been developed so far. And, if the structures of the IGBT region and the FWD region can be optimized, it can be manufactured with a stable yield using the current manufacturing apparatus. However, it is very difficult to simultaneously optimize the structures of the IGBT region and the FWD region and make the respective losses equal to the losses of the separately manufactured IGBT and FWD.
- a small signal pad for connecting a gate and a built-in temperature sensing diode to an external electrode, and a gate wiring for electrically connecting the gate pad and the gate of each cell are formed.
- an FLR (Field Limiting Ring) for holding a withstand voltage is formed in a termination region on the outer periphery of the substrate. In these regions, a p-type well having a high impurity concentration and a deep depth is formed with respect to the p-type base layer of the IGBT and the p-type anode layer of the FWD so as to maintain the withstand voltage.
- the p-type well is electrically connected to the p-type base layer of the IGBT and the p-type anode layer of the FWD.
- the FWD is forward biased, holes are injected from the p-type well, and the conventional RC-IGBT does not have a sufficient interference preventing effect at the time of recovery.
- the present invention has been made to solve the problems as described above, and an object thereof is to obtain a semiconductor device capable of reducing the recovery loss of FWD without deteriorating the loss of the IGBT.
- a semiconductor device comprises an n-type drift layer, a p-type base layer and an n-type emitter layer formed on the surface of the n-type drift layer, and a p-type collector formed on the back surface of the n-type drift layer.
- n-type drift layer having a layer, an n-type drift layer, a p-type anode layer formed on the surface of the n-type drift layer, and an n-type formed on the back surface of the n-type drift layer
- An FWD Free Wheeling Diode having a cathode layer, a p-type well formed on the surface of the n-type drift layer in a wiring region and a termination region, and a wiring formed on the p-type well in the wiring region
- the p-type well is higher in impurity concentration and deeper than the p-type anode layer, and the p-type well is not formed directly on the n-type cathode layer, and the n-type well is Ka Characterized in that apart from directly above the region of over de layer.
- the p-type well is not formed immediately above the n-type cathode layer, and is separated from the region immediately above the n-type cathode layer. This makes it possible to reduce the amount of holes in the n ⁇ -type drift layer in the formation region of the FWD when the FWD is forward biased and current is applied. As a result, the recovery loss of the FWD can be reduced without deteriorating the loss of the IGBT.
- FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along line I-II of FIG. It is a sectional view showing a semiconductor device concerning a comparative example. It is a top view which shows the semiconductor device concerning Embodiment 2 of this invention.
- FIG. 5 is a cross-sectional view taken along line I-II of FIG. 4; It is a top view which shows the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 4 of this invention. It is sectional drawing which shows the semiconductor device concerning Embodiment 5 of this invention.
- FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention.
- FIG. 2 is a cross-sectional view taken along line I-II of FIG.
- This semiconductor device is an RC-IGBT in which an IGBT (Insulated Gate Bipolar Transistor) 1 and an FWD (Free Wheeling Diode) 2 are formed on one semiconductor substrate. Further, in the RC-IGBT, the wiring area 3 exists in areas other than the areas operating as the IGBT 1 and the FWD 2, and the termination area 4 exists in the outer periphery thereof.
- IGBT Insulated Gate Bipolar Transistor
- FWD Free Wheeling Diode
- IGBT1 is, n - -type drift layer 5, n - and p-type base layer 6 and the n + -type emitter layer 7 formed on the surface of the type drift layer 5, n - formed on the back surface of the type drift layer 5 p And a type collector layer 8.
- a collector electrode 9 is connected to the p-type collector layer 8.
- electrons are supplied to the n ⁇ -type drift layer 5 through the channel by applying a voltage to the gate.
- FWD2 is, n - and an n-type cathode layer 11 formed on the rear surface of the type drift layer 5 - -type drift layer 5, n - and p-type anode layer 10 formed on the surface of the type drift layer 5, n .
- a p-type well 12 is formed on the surface of the n ⁇ -type drift layer 5 in the wiring region 3 and the termination region 4 so as to maintain the breakdown voltage.
- a gate wiring 13 and a gate pad 14 are formed as a wiring on the p-type well 12 in the wiring region.
- the gate wiring 13 electrically connects the gate pad 14 and the gate of each cell.
- a small signal pad (not shown) for connecting a temperature sense diode built in the IGBT 1 to an external electrode is also provided.
- an FLR Field Limiting Ring
- These lines do not produce an inversion layer in the p-type well 12 unlike the gate electrode which produces an inversion region.
- the p-type well 12 is higher in impurity concentration and deeper than the p-type anode layer 10.
- the p-type well 12 is not formed immediately above the n-type cathode layer 11 and is separated from the region directly above the n-type cathode layer 11.
- FIG. 3 is a cross-sectional view showing a semiconductor device according to a comparative example.
- a part of the p-type well 12 is formed directly on the n-type cathode layer 11. Therefore, when the FWD 2 is forward biased, holes are injected from the p-type well 12 into the formation region of the FWD 2, and the interference preventing effect at the time of recovery is not sufficient.
- the p-type well 12 is not formed immediately above the n-type cathode layer 11 and is separated from the region immediately above the n-type cathode layer 11. This makes it possible to reduce the amount of holes in the n ⁇ -type drift layer 5 in the formation region of the FWD 2 when the FWD 2 is forward biased and energized. As a result, the recovery loss of the FWD can be reduced without deteriorating the loss of the IGBT.
- the p-type well is used to reduce the recovery loss of the FWD 2 It is preferable that the distance 12 be at least the thickness t or more of the n ⁇ -type drift layer 5 from the region immediately above the n-type cathode layer 11 (w ⁇ t in FIG. 2).
- the n + -type emitter layer 7 is not formed in the region of FWD 2 , and the p-type base layer 6 and the p-type anode layer 10 preferably have the same depth and concentration.
- the IGBT 1 and the FWD 2 can be formed separately only by forming the n + -type emitter layer 7 or not. Further, when forming the surface structure of the RC-IGBT, the number of processes can be reduced by sharing the wafer processes of the IGBT 1 and the FWD 2, and the RC-IGBT with good performance can be manufactured at low cost.
- FIG. 4 is a plan view showing a semiconductor device according to the second embodiment of the present invention.
- FIG. 5 is a cross-sectional view taken along line I-II of FIG. A plurality of trench gates 15 are formed.
- the IGBT 1 is formed in the region between the wiring region 3 and the termination region 4 and the FWD 2. By forming the IGBT 1 in the vicinity of the wiring region 3 and the termination region 4, the recovery loss of the FWD 2 can be reduced without reducing the effective area of the element (the total area of the IGBTs 1 and FWD 2 which can be energized).
- FIG. 6 is a plan view showing a semiconductor device according to the third embodiment of the present invention.
- the IGBTs 1 and the FWDs 2 are repeatedly formed at fixed intervals in a region surrounded by the gate wiring 13 in plan view.
- the IGBTs 1 and FWDs 2 in the RC-IGBT generate heat when current flows.
- the maximum rated temperature of the element is generally 150 to 175 ° C. In order to lower the temperature of the element that has generated heat, it is necessary to cool the radiation fin in contact with the back side of the RC-IGBT by air cooling or water cooling.
- the period in which the current flows in the IGBT 1 and the period in which the current flows in the FWD 2 alternate, and there is a gap between the timings at which the temperatures of the IGBT 1 and the FWD 2 peak. Therefore, by repeatedly forming the IGBT 1 and the FWD 2 at a constant interval, it is possible to dissipate the heat when one of the IGBT 1 and the FWD 2 is energized to the radiation fin of the other region, and to lower the device temperature efficiently. Can. Further, the chip can be reduced by that amount, and the cooling mechanism can be simplified, so that the cost of the element or the inverter incorporating the element can be reduced.
- FIG. 7 is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention.
- the p-type well 12 is deeper than the p-type anode layer 10 and has a lower impurity concentration.
- the amount of holes injected from p-type well 12 can be reduced when FWD 2 is energized, and the recovery loss of FWD 2 can be reduced.
- FIG. 8 is a cross-sectional view showing a semiconductor device according to the fifth embodiment of the present invention.
- the p-type well 12 has the same impurity concentration and depth as the p-type anode layer 10. Thus, even if FWD 2 is formed in the vicinity of p-type well 12, the amount of holes injected from p-type well 12 can be reduced when FWD 2 is energized, and the recovery loss of FWD 2 can be reduced.
- the p-type well 12 and the p-type anode layer 10 are formed by simultaneously injecting and diffusing a p-type impurity. As a result, the number of wafer process steps can be reduced, and a low-cost, high-performance RC-IGBT can be manufactured.
- the semiconductor substrate is not limited to one formed of silicon, and may be formed of a wide band gap semiconductor having a larger band gap than silicon.
- the wide band gap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond.
- a semiconductor device formed of such a wide band gap semiconductor can be miniaturized because of high voltage resistance and allowable current density. By using this miniaturized device, it is possible to miniaturize a semiconductor module incorporating this device. Further, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized, and the water cooling portion can be air cooled, so that the semiconductor module can be further miniaturized. In addition, since the power loss of the element is low and the efficiency is high, the semiconductor module can be highly efficient.
Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す平面図である。図2は図1のI-IIに沿った断面図である。この半導体装置は1つの半導体基板にIGBT(Insulated Gate Bipolar Transistor)1とFWD(Free Wheeling Diode)2が形成されたRC-IGBTである。また、RC-IGBTにはIGBT1やFWD2として動作する領域以外に配線領域3が存在し、それらの外周に終端領域4が存在する。
図4は、本発明の実施の形態2に係る半導体装置を示す平面図である。図5は図4のI-IIに沿った断面図である。複数のトレンチゲート15が形成されている。配線領域3及び終端領域4とFWD2との間の領域にIGBT1が形成されている。配線領域3及び終端領域4の近傍にIGBT1を形成することによって、素子の有効面積(通電可能なIGBT1とFWD2の合計面積)を小さくすることなく、FWD2のリカバリー損失を低減することができる。
図6は、本発明の実施の形態3に係る半導体装置を示す平面図である。平面視においてゲート配線13で囲まれた領域内でIGBT1とFWD2が一定の間隔で繰り返し形成されている。RC-IGBT内のIGBT1とFWD2は電流を通電することで発熱する。素子の最大定格温度は一般的に150~175℃であり、発熱した素子の温度を下げるために、RC-IGBT裏面側に接触した放熱フィンを空冷もしくは水冷方式で冷却する必要がある。通常の使用方法において、IGBT1に電流が流れる期間とFWD2に電流が流れる期間は交互であり、IGBT1とFWD2の温度がピークになるタイミングにはずれがある。そこで、IGBT1とFWD2を一定の間隔で繰り返し形成することで、IGBT1とFWD2の一方の通電時の熱を他方の領域の放熱フィンにも逃がすことが可能となり、効率的に素子の温度を下げることができる。また、その分だけチップを縮小でき、冷却機構も簡素化できるので、素子や素子を内蔵するインバーターのコストを低減することができる。
図7は、本発明の実施の形態4に係る半導体装置を示す断面図である。本実施の形態ではp型ウエル12はp型アノード層10に対して深さが深く不純物濃度が低い。これにより、FWD2をp型ウエル12の近傍に形成してもFWD2の通電時にp型ウエル12から注入されるホールの量を低減することができ、FWD2のリカバリー損失を低減することができる。
図8は、本発明の実施の形態5に係る半導体装置を示す断面図である。本実施の形態ではp型ウエル12はp型アノード層10に対して不純物濃度と深さが同じである。これにより、FWD2をp型ウエル12の近傍に形成してもFWD2の通電時にp型ウエル12から注入されるホールの量を低減することができ、FWD2のリカバリー損失を低減することができる。
Claims (8)
- n型ドリフト層と、前記n型ドリフト層の表面に形成されたp型ベース層及びn型エミッタ層と、前記n型ドリフト層の裏面に形成されたp型コレクタ層とを有するIGBT(Insulated Gate Bipolar Transistor)と、
前記n型ドリフト層と、前記n型ドリフト層の表面に形成されたp型アノード層と、前記n型ドリフト層の裏面に形成されたn型カソード層とを有するFWD(Free Wheeling Diode)と、
配線領域と終端領域において前記n型ドリフト層の表面に形成されたp型ウエルと、
前記配線領域において前記p型ウエル上に形成された配線とを備え、
前記p型ウエルは前記p型アノード層に対して不純物濃度が高くかつ深さが深く、
前記p型ウエルは、前記n型カソード層の直上には形成されておらず、前記n型カソード層の直上領域から離れていることを特徴とする半導体装置。 - 前記p型ウエルは前記n型カソード層の直上領域から少なくとも前記n型ドリフト層の厚み以上離れていることを特徴とする請求項1に記載の半導体装置。
- 前記FWDの形成領域には前記n型エミッタ層は形成されておらず、
前記p型ベース層と前記p型アノード層は深さと濃度が同じであることを特徴とする請求項1又は2に記載の半導体装置。 - 前記配線領域及び前記終端領域と前記FWDの形成領域との間の領域に前記IGBTが形成されていることを特徴とする請求項1~3の何れか1項に記載の半導体装置。
- 平面視において前記IGBTと前記FWDが一定の間隔で繰り返し形成されていることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
- n型ドリフト層と、前記n型ドリフト層の表面に形成されたp型ベース層及びn型エミッタ層と、前記n型ドリフト層の裏面に形成されたp型コレクタ層とを有するIGBTと、
前記n型ドリフト層と、前記n型ドリフト層の表面に形成されたp型アノード層と、前記n型ドリフト層の裏面に形成されたn型カソード層とを有するFWDと、
配線領域と終端領域において前記n型ドリフト層の表面に形成されたp型ウエルと、
前記配線領域において前記p型ウエル上に形成された配線とを備え、
前記p型ウエルは前記p型アノード層に対して深さが深くかつ不純物濃度が低いことを特徴とする半導体装置。 - n型ドリフト層と、前記n型ドリフト層の表面に形成されたp型ベース層及びn型エミッタ層と、前記n型ドリフト層の裏面に形成されたp型コレクタ層とを有するIGBTと、
前記n型ドリフト層と、前記n型ドリフト層の表面に形成されたp型アノード層と、前記n型ドリフト層の裏面に形成されたn型カソード層とを有するFWDと、
配線領域と終端領域において前記n型ドリフト層の表面に形成されたp型ウエルと、
前記配線領域において前記p型ウエル上に形成された配線とを備え、
前記p型ウエルは前記p型アノード層に対して不純物濃度と深さが同じであることを特徴とする半導体装置。 - 前記p型ウエルと前記p型アノード層はP型不純物を同時に注入及び拡散することで形成されることを特徴とする請求項7に記載の半導体装置。
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