CN107112324A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107112324A
CN107112324A CN201480084166.4A CN201480084166A CN107112324A CN 107112324 A CN107112324 A CN 107112324A CN 201480084166 A CN201480084166 A CN 201480084166A CN 107112324 A CN107112324 A CN 107112324A
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layer
drift layer
igbt
fwd
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春口秀树
友松佳史
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Mitsubishi Electric Corp
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Abstract

IGBT(1)具有：n型漂移层(5)；p型基极层(6)及n型发射极层(7)，它们形成在n型漂移层(5)的表面；以及p型集电极层(8)，其形成在n型漂移层(5)的背面。FWD(2)具有：n型漂移层(5)、在n型漂移层(5)的表面形成的p型阳极层(10)、以及在n－型漂移层(5)的背面形成的n型阴极层(11)。在配线区域(3)和终端区域(4)处，在n－型漂移层(5)的表面形成有p型阱(12)。在配线区域(3)处，在p型阱(12)之上形成有配线(13)。相对于p型阳极层(10)，p型阱(12)的杂质浓度高且深度深。p型阱(12)与n型阴极层(11)的正上方区域分离，没有形成于n型阴极层(11)的正上方。

Description

半导体装置
技术领域
本发明涉及在IGBT(Insulated Gate Bipolar Transistor)内置有FWD(FreeWheeling Diode)的反向导通IGBT(RC(Reverse Conducting)-IGBT)。
背景技术
在逆变器、转换器安装的IGBT、FWD的损耗逐年降低。与之相伴地，芯片的电流密度提高，芯片尺寸缩小。但是，近年，IGBT、FWD的损耗正在接近极限值，为了大幅缩小芯片尺寸，还在进行以SiC为材料的功率器件的开发、兼具IGBT和FWD的性能的RC-IGBT等的开发。
以SiC为材料的功率器件能够在高温下使用，期待其损耗也能够大幅地降低。但是，存在诸如SiC晶片材料昂贵、以SiC中的缺陷为要因而产生故障等课题，在市场上广泛普及还需要一段时间。
与之相对地，RC-IGBT能够通过至今已进行了一定开发的以Si为材料的IGBT和FWD的组合而实现。并且，如果IGBT区域和FWD区域的构造能够得到优化，则能够使用目前的制造装置而以稳定的成品率进行制造。但是，对IGBT区域和FWD区域的构造同时进行优化，使它们的损耗与单独制造出的IGBT、FWD的损耗等同是极其困难的。
就通常的FWD而言，为了降低恢复损耗，采用了通过Pt扩散、电子束照射而使Si中的寿命(life time)变短的方法。但是，RC-IGBT存在下述问题，即，如果使Si中的寿命变短，则IGBT的总损耗(导通时的损耗和通断损耗的合计)变差。
为了降低恢复损耗且不使Si中的寿命变短，有效的方法是在对FWD施加正向偏置而进行通电时对来自阳极区域的空穴的注入进行抑制。因此，阳极区域的浓度降低。但是，由于也会从阳极区域以外的芯片表面的P型扩散层注入空穴，因此还需要注意阳极区域以外的P型扩散层的设计。
为了使例如RC-IGBT的恢复损耗降低，提出了下述技术，即，在IGBT的P型基极层的正下方，不形成成为二极管阴极层的背面n+区域(例如，参照专利文献1)。
专利文献1：日本特开平5-152574号公报
发明内容
在衬底的配线区域形成有小信号焊盘、栅极配线，该小信号焊盘用于将栅极、内置的温度传感二极管与外部电极进行导线连接，该栅极配线用于对栅极焊盘和各单元的栅极进行电连接。另外，在衬底的外周的终端区域形成有用于保持耐压的FLR(Field LimitingRing)。在上述这些区域，形成与IGBT的p型基极层、FWD的p型阳极层相比杂质浓度高且深度深的p型阱，以能够保持耐压。该p型阱与IGBT的P型基极层、FWD的p型阳极层电连接。在FWD被正向偏置时，会从p型阱注入空穴，对于现有的RC-IGBT来说，恢复时的防干扰效果并不充分。
本发明就是为了解决上述课题而提出的，其目的在于得到一种能够使FWD的恢复损耗降低而不使IGBT的损耗变差的半导体装置。
本发明涉及的半导体装置的特征在于，具有：IGBT即绝缘栅双极晶体管，其具有n型漂移层、p型基极层、n型发射极层、以及在所述n型漂移层的背面形成的p型集电极层，所述p型基极层及n型发射极层形成在所述n型漂移层的表面；FWD即续流二极管，其具有所述n型漂移层、在所述n型漂移层的表面形成的p型阳极层、以及在所述n型漂移层的背面形成的n型阴极层；p型阱，其在配线区域和终端区域形成于所述n型漂移层的表面；以及配线，其在所述配线区域形成于所述p型阱之上，相对于所述p型阳极层，所述p型阱的杂质浓度高且深度深，所述p型阱与所述n型阴极层的正上方区域分离，没有形成于所述n型阴极层的正上方。
发明的效果
在本发明中，p型阱与n型阴极层的正上方区域分离，没有形成于n型阴极层的正上方。由此，在对FWD施加正向偏置而进行通电时，能够使FWD的形成区域的n－型漂移层的空穴的量减少。其结果，能够使FWD的恢复损耗降低，而不使IGBT的损耗变差。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是沿图1的I—II的剖视图。
图3是表示对比例涉及的半导体装置的剖视图。
图4是表示本发明的实施方式2涉及的半导体装置的俯视图。
图5是沿图4的I—II的剖视图。
图6是表示本发明的实施方式3涉及的半导体装置的俯视图。
图7是表示本发明的实施方式4涉及的半导体装置的剖视图。
图8是表示本发明的实施方式5涉及的半导体装置的剖视图。
具体实施方式
参照附图，对本发明的实施方式涉及的半导体装置进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。图2是沿图1的I－II的剖视图。该半导体装置是在1个半导体衬底形成有IGBT(Insulated Gate BipolarTransistor)1和FWD(Free Wheeling Diode)2的RC-IGBT。另外，在RC-IGBT，除了作为IGBT1、FWD 2而进行动作的区域以外，还存在配线区域3，在上述区域的外周存在终端区域4。
IGBT 1具有：n－型漂移层5；p型基极层6及n+型发射极层7，它们形成在n－型漂移层5的表面；以及p型集电极层8，其形成在n－型漂移层5的背面。集电极电极9与p型集电极层8连接。就IGBT 1的表面侧的MOS构造而言，通过对栅极施加电压，从而经过沟道将电子供给至n－型漂移层5。
FWD 2具有：n－型漂移层5、在n－型漂移层5的表面形成的p型阳极层10、以及在n－型漂移层5的背面形成的n型阴极层11。
在配线区域3和终端区域4处，在n－型漂移层5的表面形成有p型阱12，以能够保持耐压。在配线区域处，在p型阱12之上作为配线而形成有栅极配线13及栅极焊盘14。栅极配线13对栅极焊盘14和各单元的栅极进行电连接。另外，在配线区域还设置有小信号焊盘(未图示)，该小信号焊盘用于将在IGBT 1内置的温度传感二极管与外部电极进行导线连接。另外，在终端区域形成有用于保持耐压的FLR(Field Limiting Ring)。这些配线不同于产生反转区域的栅极电极，不会使p型阱12产生反转层。
相对于p型阳极层10，p型阱12的杂质浓度高且深度深。p型阱12与n型阴极层11的正上方区域分离，没有形成于n型阴极层11的正上方。
下面，与对比例进行比较而说明本实施方式的效果。图3是表示对比例涉及的半导体装置的剖视图。在对比例中，p型阱12的一部分形成于n型阴极层11的正上方。因此，在FWD2被正向偏置时，空穴会从p型阱12注入至FWD 2的形成区域，恢复时的防干扰效果并不充分。
另一方面，在本实施方式中，p型阱12与n型阴极层11的正上方区域分离，没有形成于n型阴极层11的正上方。由此，能够在对FWD 2施加正向偏置而进行通电时，使FWD 2的形成区域的n－型漂移层5的空穴的量减少。其结果，能够使FWD的恢复损耗降低，而不使IGBT的损耗变差。
另外，如果考虑到从表面的p型阱12注入的空穴朝向背面的n型阴极层11而以斜下方45度不断进行扩散，则为了降低FWD 2的恢复损耗，p型阱12优选与n型阴极层11的正上方区域至少分离大于或等于n－型漂移层5的厚度t(图2中的w≥t)。
另外，优选在FWD 2的区域不形成n+型发射极层7，p型基极层6与p型阳极层10的深度和浓度相同。仅通过形成n+型发射极层7与否，即可分开形成IGBT 1和FWD 2。另外，在形成RC-IGBT的表面构造时，能够通过将IGBT 1和FWD 2的晶片工艺共通化而减少工序数，能够以低成本实现性能好的RC-IGBT的制造。
实施方式2.
图4是表示本发明的实施方式2涉及的半导体装置的俯视图。图5是沿图4的I－II的剖视图。形成有多个沟槽栅极15。在配线区域3及终端区域4与FWD 2之间的区域形成有IGBT 1。通过在配线区域3及终端区域4的附近形成IGBT 1，由此能够降低FWD 2的恢复损耗，而不会使元件的有效面积(可通电的IGBT 1和FWD 2的合计面积)变小。
实施方式3.
图6是表示本发明的实施方式3涉及的半导体装置的俯视图。在俯视观察时，在由栅极配线13包围的区域内以固定的间隔而重复形成有IGBT 1和FWD 2。RC-IGBT内的IGBT 1和FWD 2会由于流过电流而发热。元件的最大额定温度通常为150～175℃，为了使发热的元件的温度下降，需要通过空冷或者水冷方式而对与RC-IGBT背面侧接触的散热鳍片进行冷却。在通常的使用方法中，电流流过IGBT 1的期间与电流流过FWD 2的期间是交替的，IGBT1与FWD 2的温度成为峰值的定时是错开的。因此，通过以固定的间隔而重复形成IGBT1和FWD 2，由此能够使IGBT 1和FWD 2中的一者通电时的热量也释放至另一者的区域的散热鳍片，能够高效地使元件的温度下降。另外，能够使芯片相应地缩小，冷却机构也能够进行简化，因此能够使元件、内置有元件的逆变器的成本降低。
实施方式4.
图7是表示本发明的实施方式4涉及的半导体装置的剖视图。在本实施方式中，相对于p型阳极层10，p型阱12的深度深且杂质浓度低。由此，即使在p型阱12的附近形成FWD2，也能够使在FWD 2通电时从p型阱12注入的空穴的量减少，能够降低FWD 2的恢复损耗。
实施方式5.
图8是表示本发明的实施方式5涉及的半导体装置的剖视图。在本实施方式中，p型阱12的杂质浓度、深度与p型阳极层10相同。由此，即使在p型阱12的附近形成FWD 2，也能够使在FWD 2通电时从p型阱12注入的空穴的量减少，能够降低FWD 2的恢复损耗。
另外，p型阱12和p型阳极层10是通过同时将P型杂质进行注入及扩散而形成的。由此，能够减少晶片工艺工序数，能够以低成本制造出性能好的RC-IGBT。
此外，半导体衬底不限于由硅形成，也可以由与硅相比带隙宽的宽带隙半导体形成。宽带隙半导体为例如碳化硅、氮化镓类材料或者金刚石。由这样的宽带隙半导体形成的半导体装置的耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化的装置，能够使安装有该装置的半导体模块也小型化。另外，由于元件的耐热性高，因此能够将散热器的散热鳍片小型化，能够将水冷部进行空冷化，因而能够将半导体模块进一步小型化。另外，元件的电力损耗低并且效率高，因此能够使半导体模块高效率化。
标号的说明
1 IGBT，2 FWD，3配线区域，4终端区域，5 n－型漂移层，6 p型基极层，7 n+型发射极层，8 p型集电极层，10 p型阳极层，11 n型阴极层，12 p型阱，13栅极配线。

Claims (8)

1.一种半导体装置，其特征在于，具有：
IGBT即绝缘栅双极晶体管，其具有n型漂移层、p型基极层、n型发射极层、以及在所述n型漂移层的背面形成的p型集电极层，所述p型基极层及n型发射极层形成在所述n型漂移层的表面；
FWD即续流二极管，其具有所述n型漂移层、在所述n型漂移层的表面形成的p型阳极层、以及在所述n型漂移层的背面形成的n型阴极层；
p型阱，其在配线区域和终端区域形成于所述n型漂移层的表面；以及
配线，其在所述配线区域形成于所述p型阱之上，
相对于所述p型阳极层，所述p型阱的杂质浓度高且深度深，
所述p型阱与所述n型阴极层的正上方区域分离，没有形成于所述n型阴极层的正上方。
2.根据权利要求1所述的半导体装置，其特征在于，
所述p型阱与所述n型阴极层的正上方区域至少分离大于或等于所述n型漂移层的厚度。
3.根据权利要求1或2所述的半导体装置，其特征在于，
在所述FWD的形成区域没有形成所述n型发射极层，
所述p型基极层与所述p型阳极层的深度和浓度相同。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
在所述配线区域及所述终端区域与所述FWD的形成区域之间的区域形成有所述IGBT。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
在俯视观察时，以固定的间隔而重复形成有所述IGBT和所述FWD。
6.一种半导体装置，其特征在于，具有：
IGBT，其具有n型漂移层、p型基极层、n型发射极层、以及在所述n型漂移层的背面形成的p型集电极层，所述p型基极层及n型发射极层形成在所述n型漂移层的表面；
FWD，其具有所述n型漂移层、在所述n型漂移层的表面形成的p型阳极层、以及在所述n型漂移层的背面形成的n型阴极层；
p型阱，其在配线区域和终端区域形成于所述n型漂移层的表面；以及
配线，其在所述配线区域形成于所述p型阱之上，
相对于所述p型阳极层，所述p型阱的深度深且杂质浓度低。
7.一种半导体装置，其特征在于，具有：
IGBT，其具有n型漂移层、p型基极层、n型发射极层、以及在所述n型漂移层的背面形成的p型集电极层，所述p型基极层及n型发射极层形成在所述n型漂移层的表面；
FWD，其具有所述n型漂移层、在所述n型漂移层的表面形成的p型阳极层、以及在所述n型漂移层的背面形成的n型阴极层；
p型阱，其在配线区域和终端区域形成于所述n型漂移层的表面；以及
配线，其在所述配线区域形成于所述p型阱之上，
所述p型阱的杂质浓度、深度与所述p型阳极层相同。
8.根据权利要求7所述的半导体装置，其特征在于，
所述p型阱和所述p型阳极层是通过同时将P型杂质进行注入及扩散而形成的。
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