CN1728379A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1728379A
CN1728379A CNA2005100772120A CN200510077212A CN1728379A CN 1728379 A CN1728379 A CN 1728379A CN A2005100772120 A CNA2005100772120 A CN A2005100772120A CN 200510077212 A CN200510077212 A CN 200510077212A CN 1728379 A CN1728379 A CN 1728379A
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semiconductor chip
semiconductor
mos
zone
interconnection
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CN100521201C (zh
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白石正树
宇野友彰
松浦伸悌
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Renesas Electronics Corp
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Renesas Technology Corp
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Abstract

提供一种电源电压转换效率提高的半导体器件。在具有一个其中用于高端开关的功率MOSFET和用于低端开关的功率MOSFET串联连接的电路的非绝缘DC-DC转换器中,用于低端开关的功率MOSFET和肖特基势垒二极管形成在一个半导体芯片内,该肖特基势垒二极管与该用于低端开关的功率MOSFET并联连接。肖特基势垒二极管的形成区域SDR布置在半导体芯片较短方向上的中心,以及在其两侧上布置用于低端开关的功率MOSFET的形成区域。从半导体芯片主表面上两个长边附近的栅极指向肖特基势垒二极管的形成区域SDR,布置多个栅极指,使得形成区域SDR插入在它们之间。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2004年7月30日提交的日本专利申请No.2004-223664的优先权,据此将其内容通过参考引入本申请。
技术领域
本发明涉及一种半导体器件及其制造技术,并且特别地涉及一种在应用于具有电源电路的半导体器件及其制造方法时有效的技术。
背景技术
DC-DC转换器广泛用作电源电路的一个例子,该DC-DC转换器具有彼此串联连接的高端功率MOSFET(金属氧化物半导体场效应晶体管)和低端功率MOSFET。高端功率MOSFET具有用于控制DC-DC转换器的开关功能,而低端功率MOSFET具有用于同步整流的开关功能。在这两个功率MOSFET彼此同步的同时,通过使这两个功率MOSFET交替地导通/截至,执行电压转换。
在需求增加流入待驱动的CPU(中央处理单元)等中的电流以及减小诸如扼流线圈和输入/输出电容之类无源元件的尺寸的情况下,待用于例如台式个人计算机、服务器和游戏机的电源电路中的非绝缘型DC-DC转换器往往具有较大电流和较高频率。但是,随着电流增加和频率提高的趋势,在特定期间(无电流时间期间),当高端功率MOSFET和低端功率MOSFET二者都截至时,寄生到低端功率MOSFET的体二极管的传导损耗和恢复损耗增加。为了克服这个问题,通过将肖特基势垒二极管(下文将缩写为“SBD”)并联连接到低端功率MOSFET,并且使得电流不流过体二极管而是流过SBD,由此降低二极管的传导损耗和恢复损耗。
例如,在日本未审专利公开No.Hei10(1998)-150140中,有对DC-DC转换器的描述。其中描述的DC-DC转换器具有这样的结构,其中,彼此并联连接的MOSFET和SBD形成在各自的半导体芯片上,并且这两个半导体芯片包含在一个管壳中(参考专利文献1)。
例如,在日本未审专利公开No.2003-124436中,描述的是一种DC-DC转换器,其中,在其上方形成有高端功率MOSFET的半导体芯片和在其上方形成有彼此并联连接的低端功率MOSFET和SBD的半导体芯片,包含在一个管壳中(参考专利文献2)。
在日本未审专利公开No.Hei9(1997)-102602中,描述的是在其上方形成有彼此并联连接的低端功率MOSFET和SBD的半导体芯片,其中SBD形成在低端MOSFET的有源区中(参考专利文献3)。
[专利文献1]日本未审专利公开No.Hei10(1998)-150140
[专利文献2]日本未审专利公开No.2003-124436
[专利文献3]日本未审专利公开No.Hei9(1997)-102602
发明内容
在专利文献1所公开的技术中,当将低端功率MOSFET和SBD形成在各自的半导体芯片上时,无电流时间期间传递到SBD的电流由于连接在低端功率MOSFET和SBD之间的互连的电感的影响而减小。结果,即使连接具有正向电压低于体二极管的正向电压的SBD,对于降低二极管的传导损耗或恢复损耗,也不会带来足够的效果。
目前,与高端功率MOSFET的栅极电阻相比,很少关注低端功率MOSFET的栅极电阻。然而,本发明人已首次发现:当作为如上所述的电流增加和频率提高的结果,低端功率MOSFET的栅极电阻超过预定值时,自导通现象变得非常显著,引起这些损耗的急剧增加。自导通是这样一种现象,即当低端功率MOSFET截止且高端功率MOSFET导通时,连接低端功率MOSFET和高端功率MOSFET之间的互连的电位增加,并且低端功率MOSFET的栅极电压根据低端功率MOSFET的漏—栅电容和源-栅电容的比率而升高,由此引起低端开关故障。基于本发明人的研究,优选还在半导体芯片的主表面上的有源区域中延伸并布置多个金属互连(栅极指),以便于降低低端功率MOSFET的栅极电阻。在专利文献2中,公开了在一个半导体芯片上形成并联连接的低端功率MOSFET和SBD,但没有公开关于由电流增加和频率提高引起的自导通现象的频繁发生、归因于这些现象的损耗增加、克服这些问题的栅极指(gate finger)的构成、以及SBD区域、功率MOSFET区域和栅极指的优选布置。
在专利文献3中,公开了在低端MOSFET的有源区中形成SBD。由于没有公开关于低端功率MOSFET的沟道层和肖特基金属之间的欧姆接触,所以不能得到对欧姆接触的形成方法的描述。也没有对SBD的肖特基接触部分处泄漏电流的增加进行公开。因此,在该文献中不能得到对泄漏电流的减小方法的描述。
本发明的目的在于提供一种能够提高半导体器件的电源电压转换效率的技术。
由这里的说明书和附图,本发明的上述和其它目的及新颖特征将变得显而易见。
接下来将简要描述由本发明所公开的发明的典型发明。
在本发明的一个方面,如此提供有一种半导体器件,该半导体器件包括安装有场效应晶体管和SBD的半导体芯片,其中设置构成该场效应晶体管的多个晶体管单元形成区域,以在其间插入SBD排列区域;以及要与多个晶体管单元的栅极电极电连接的多个金属栅极互连,分别设置在多个晶体管单元形成区域中,使得在多个金属栅极互连之间插入SBD排列区域。
在本发明的另一方面,还提供有一种半导体器件,该半导体器件包括第一电源端子,用于供给第一电位;第二电源端子,用于供给比第一电位低的第二电位;第一和第二场效应晶体管,串联连接在第一和第二电源端子之间;控制电路,电连接到这些第一和第二场效应晶体管的输入,并控制这些第一和第二场效应晶体管的操作;输出互连部分,连接到用于连接第一和第二场效应晶体管的互连;以及SBD,存在于输出互连部分和第二电源端子之间,并与第二场效应晶体管并联连接,其中第二场效应晶体管和SBD形成在一个半导体芯片上;多个晶体管单元形成区域布置在该半导体芯片上,使得在多个晶体管单元形成区域之间插入SBD排列区域;以及要与多个晶体管单元的栅极电极电连接的多个金属栅极互连,分别设置在多个晶体管单元形成区域中,使得在多个金属互连之间插入SBD排列区域。
在本发明的又一个方面,还提供有一种半导体器件,该半导体器件包括第一电源端子,用于供给第一电位;第二电源端子,用于供给比第一电位低的第二电位;第一和第二场效应晶体管,串联连接在第一和第二电源端子之间;控制电路,电连接到这些第一和第二场效应晶体管的输入,并控制这些第一和第二场效应晶体管的操作;输出互连部分,连接到用于连接第一和第二场效应晶体管的互连;以及SBD,存在于输出互连部分和第二电源端子之间,并与第二场效应晶体管并联连接,其中第一场效应晶体管形成在第一半导体芯片上,第二场效应晶体管和SBD形成在第二半导体芯片上;控制电路形成在第三半导体芯片上;构成第二场效应晶体管的多个晶体管单元形成区域布置在第二半导体芯片上,使得在多个晶体管单元形成区域之间插入SBD排列区域;要与多个晶体管单元的栅极电极电连接的多个金属栅极互连,分别设置在多个晶体管单元形成区域中,使得在多个金属栅极互连之间插入SBD排列区域;以及用一个密封剂(sealant)密封第一、第二和第三半导体芯片。
在本发明的又一个方面,还提供有一种半导体器件,该半导体器件具有安装有场效应晶体管和SBD的半导体芯片,其中SBD形成在构成场效应晶体管的多个晶体管单元形成区域中;以及在构成SBD的金属和构成半导体芯片的半导体衬底之间的接触部分处,形成具有杂质浓度低于半导体衬底杂质浓度的半导体区域。
在本发明的又一个方面,还提供有一种半导体器件,该半导体器件具有安装有场效应晶体管和SBD的半导体芯片,其中SBD形成在构成场效应晶体管的多个晶体管单元形成区域中;在构成SBD的金属和多个晶体管单元每一个的沟道层之间的接触部分处,形成具有杂质浓度高于沟道层杂质浓度的第一半导体区域;以及在构成SBD的金属和构成半导体芯片的半导体衬底之间的接触部分处,形成具有杂质浓度低于半导体衬底杂质浓度的第二半导体区域。
接下来将描述由本申请公开的发明的典型发明所能得到的优点。
由于SBD能令人满意地形成在具有场效应晶体管和金属栅极互连的半导体芯片中,所以能减小用于连接场效应晶体管和SBD的互连的电感。这就带来半导体器件的电源电压转换效率的提高。
附图说明
图1是说明根据本发明一个实施方式的半导体器件的一个实施例的电路图;
图2是说明图1所示半导体器件的控制电路的一个实施例的电路图;
图3是对图1所示半导体器件操作中的定时图的一个实施例的说明性视图;
图4是说明由本发明人所研究的半导体器件的半导体芯片结构实施例的说明性视图;
图5是半导体器件的电路的说明性视图;
图6是对在其上方形成有控制电路的半导体芯片的寄生操作的说明;
图7是说明本发明人已经研究的当前使用的半导体芯片的一个实施例的整个平面图,该半导体芯片具有形成在其上方的用于低端开关的场效应晶体管;
图8是示意性表示损耗对图7用于低端开关的场效应晶体管的栅极电阻依赖关系的计算结果的图表;
图9是半导体芯片的整个平面图,在该半导体芯片的上方形成有图1半导体器件的用于低端开关的场效应晶体管和肖特基势垒二极管;
图10是在附加布置键合导线和外部电极之后,图9的半导体芯片的整个平面图;
图11是图9的区域A的放大平面图;
图12是沿图11的Y1-Y1线所取的横截面图;
图13是沿图11的Y2-Y2线所取的横截面图;
图14是图9的肖特基势垒二极管的局部放大横截面图;
图15是图9的用于低端开关的场效应晶体管的单位晶体管单元的放大横截面图;
图16是沿图11的X1-X1线所取的横截面图;
图17是图16的局部放大横截面图;
图18是表示在无电流时间期间传递到肖特基势垒二极管的电流的计算结果的图表;
图19是表示当肖特基势垒二极管和场效应晶体管形成在各自的半导体芯片中时和当它们形成在一个半导体芯片上时,损耗的计算结果的图表;
图20是当透视根据本发明一个实施方式的半导体器件的管壳内部时,该管壳主表面侧的整个平面图;
图21是沿图20的X2-X2线所取的横截面图;
图22是当透视根据本发明另一个实施方式的半导体器件的管壳内部时,该管壳主表面侧的整个平面图;
图23是沿图22的X3-X3线所取的横截面图;
图24是根据本发明又一个实施方式的半导体器件的部分的横截面图,该部分对应于沿图22的X3-X3线所取的部分;
图25是根据本发明又一个实施方式的半导体器件的半导体芯片的整个平面图;
图26是在附加布置键合导线和外部电极之后,图25的半导体芯片的整个平面图;
图27是根据本发明又一个实施方式的半导体器件的半导体芯片的整个平面图;
图28是在附加布置键合导线和外部电极之后,图27的半导体芯片的整个平面图;
图29是表示寄生在本发明人所研究的半导体器件上的电感分量的等效电路图;
图30是半导体器件的电路操作的说明性示图;
图31是在图30的电路操作时器件横截面的说明性视图;
图32是管壳主表面侧上的根据本发明又一个实施方式的半导体器件的整个平面图;
图33是图32的半导体器件的管壳的侧视图;
图34是图32的半导体器件的管壳背面上的整个平面图;
图35是图32的半导体器件的管壳外观的透视图;
图36是当透视图32的半导体器件的管壳内部时,该管壳主表面侧的整个平面图;
图37是沿图36的Y3-Y3线所取的横截面图;
图38是沿图36的X4-X4线所取的横截面图;
图39是第一半导体芯片的主表面侧的整个平面图,该第一半导体芯片构成图36的半导体器件的一部分;
图40是沿图39的X5-X5线所取的横截面图;
图41是图39的第一半导体芯片的局部横截面图;
图42是沿图39的Y4-Y4线所取的横截面图;
图43是第三半导体芯片的局部横截面图,该第三半导体芯片构成图36的半导体器件的一部分;
图44是说明封装图32的半导体器件的一个实施例的平面图;
图45是说明图44的所封装半导体器件的侧视图;
图46是说明包括图32半导体器件的电路系统结构的一个实施例的电路图;
图47是表示图32的半导体器件的制造步骤的流程图;
图48是说明要在图32的半导体器件的制造步骤中使用的引线框单位区域的主表面侧的一个实施例的平面图;
图49是图48的引线框的单位区域的背面上的平面图;
图50是说明在图32的半导体器件的制造步骤中的引线框的单位区域的平面图;
图51是说明根据本发明又一个实施方式的半导体器件的结构实施例的平面图;
图52是沿图51的X6-X6线所取的横截面图;
图53是沿图51的Y5-Y5线所取的横截面图;
图54是根据本发明又一个实施方式的半导体器件的部分的横截面图,该部分对应于沿图51的X6-X6线所取的部分;
图55是图54的半导体器件的部分的横截面图,该部分对应于沿图51的Y5-Y5线所取的部分;
图56是根据本发明又一个实施方式的半导体器件的横截面图;
图57是安装有散热片的图56的半导体器件的横截面图;
图58是根据本发明又一个实施方式的半导体器件的第二半导体芯片的局部横截面图;
图59是表示对图58的半导体器件的损耗的计算结果的图表;
图60是图58的半导体器件的第二半导体芯片的制造实施例的流程图;
图61是在制造步骤期间,图58的第二半导体芯片的局部横截面图;
图62是在图61步骤随后的制造步骤期间第二半导体芯片的局部横截面图;
图63是在图62步骤随后的制造步骤期间第二半导体芯片的局部横截面图;
图64是在图63步骤随后的制造步骤期间第二半导体芯片的局部横截面图;
图65是在图64步骤随后的制造步骤期间第二半导体芯片的局部横截面图;
图66是在图65步骤随后的制造步骤期间第二半导体芯片的局部横截面图;以及
图67是表示由本发明人所研究的第二半导体芯片的制造步骤的流程图。
具体实施方式
在下述实施方式中,为了方便起见,必要时将分成多个部分或多个实施方式进行描述。这些多个部分或多个实施方式彼此不是独立的,而是有这样的关系,即一个部分或实施方式是另一个部分或实施方式部分或整个的修改实施例、细节或补充描述,除非另外特别说明。在下述实施方式中,当对元件数目(包括数目、数值、数量和范围)进行参照时,该数目不限于特定数目,而是可以大于或小于该特定数目,除非另外特别说明或在数目限于该特定数目是原则上明显的情况下。此外在下述实施方式中,除非另外特别说明或在其原则上明显是必要的情况下,不必说,构成元件(包括元件步骤)不都是必要的。类似地,在下述实施方式中,当对构成元件的形状或位置关系进行参照时,除非另外特别说明或在其原则上完全不同的情况下,否则也包含那些基本上相似或类似的形状或位置关系。这也适用于上述数值和范围。在用来描述下述实施方式的所有附图中,具有同样功能的元件将用同样的参考标记来识别,并且将省略对其的重复描述。在这些实施方式中,代表场效应晶体管的MOSFET(金属氧化物半导体场效应晶体管)将被简写为MOS。以下将基于附图详细描述本发明的实施方式。
(实施方式1)
根据实施方式1的半导体器件是一个非绝缘DC-DC转换器,该转换器用在诸如台式个人计算机、膝上型个人计算机、服务器和游戏机之类的电子设备的电源电路中。图1说明了非绝缘DC-DC转换器1的电路图的一个实施例。非绝缘DC-DC转换器1具有诸如控制电路1、驱动电路(第一和第二控制电路)3a,3b、功率MOS(第一和第二场效应晶体管)Q1,Q2、SBD(肖特基势垒二极管)D1、线圈L1以及电容器C1之类的元件。
控制电路2是用于供给控制功率MOS Q1,Q2的电压开启宽度(导通时间)的信号的电路,例如脉冲宽度调制(PWM)电路。这个控制电路2容纳于与功率MOS Q1,Q2不同的管壳中。控制电路2的输出(用于控制信号的端子)电连接到驱动电路3a,3b的输入。驱动电路3a,3b的输出电连接到功率MOS Q1,Q2的栅极。驱动电路3a,3b通过从控制电路2进给的控制信号控制每个功率MOS Q1,Q2的栅极的电位,并由此控制功率MOS Q1,Q2的操作。控制电路3a,3b例如由CMOS反相器形成。图2是驱动电路3a的电路图的一个实施例。驱动电路3a具有这样的电路结构,其中,p沟道功率MOS Q3和n沟道功率MOS Q4互补地串联连接。在驱动电路3a经由功率MOSQ1控制输出信号OUT1的电平的同时,基于用于控制的输入信号IN1控制该驱动电路3a。在图中,G、D和S分别意指栅极、漏极和源极。驱动电路3b的操作与驱动电路3a的操作大致相同,所以省略对它的描述。
如图1所示的功率MOS Q1,Q2串联连接在用于供给输入电源电位(第一电源电位)Vin的端子(第一电源端子)ET1和用于供给参考电位(第二电源电位)GND的端子(第二电源端子)之间。具体地说,功率MOS Q1的源—漏通路布置成串联连接在端子ET1和输出节点(输出端子)N1之间,同时,功率MOS Q2的源—漏通路布置成串联连接在输出节点N1和用于供给接地电位GND的端子之间。输入电源电位Vin例如约为5-12V。参考电位GND例如是比输入电源电位低的电源电位,例如0(零)V,作为接地电位。非绝缘DC-DC转换器1的工作频率(在该频率下功率MOS Q1,Q2导通或截止)例如约为1MHz。
功率MOS Q1是用于高端开关的功率晶体管(高电位端:第一工作电压),并且具有用于将能量存储在线圈L1中的开关功能,该线圈L1将电功率进给到非绝缘DC-DC转换器1的输出(负载电路4的输入)。这个功率MOS Q1由垂直场效应晶体管构成,其沟道形成在半导体芯片的厚度方向上。根据本发明人所作的研究,在用于高端开关的功率MOS Q1中,开关损耗(导通损耗和截止损耗)随着非绝缘DC-DC转换器1的工作频率的增加而变大,并取决于加在MOS Q1上的寄生损耗。通常,考虑到开关损耗,因此期望使用具有沟道沿半导体芯片的主表面(相对于半导体芯片的厚度方向横切的表面)形成的水平场效应晶体管,作为用于高端开关的场效应晶体管,因为在水平场效应晶体管中,栅极电极和漏极区域的重叠面积小于垂直场效应晶体管的该面积,并因此能减小加在栅极和漏极之间的寄生电容(栅极寄生电容)。但是,对于将水平场效应晶体管的操作中的电阻(导通电阻)调整到与垂直场效应晶体管相等的水平而言,水平场效应晶体管的单元面积必须增加到垂直场效应晶体管的单元面积的至少2.5倍那么大,这对于器件的小尺寸化是不利的。另一方面,可以使垂直场效应晶体管每单位面积的沟道宽度大于水平场效应晶体管每单元面积的沟道宽度,并因此可以减小导通电阻。换句话说,通过使用垂直场效应晶体管构成用于高端开关的功率MOSQ1,能实现器件的小尺寸化,从而实现封装的小尺寸化。
功率MOS Q2是用于低端开关的功率晶体管(低电位端:第二工作电压),它是用于非绝缘DC-DC转换器1的整流的晶体管,且具有通过降低晶体管电阻,与来自控制电路2的频率相同步地执行整流的功能。类似于功率MOS Q1,这个功率MOS Q2由具有沟道形成在半导体芯片的厚度方向上的垂直功率MOS构成,例如,这是由于下列原因。图3说明了非绝缘DC-DC转换器1的定时图的一个实施例,其中,“Ton”代表在用于高端开关的功率MOS Q1导通时的脉冲宽度,以及“T”代表脉冲周期。如图3所示,低端功率MOS Q2的导通时间(施加电压期间的时间)比高端功率MOS Q1的导通时间长。在功率MOS Q2中,由于导通电阻引起的损耗变得大于开关损耗,所以使用与水平场效应晶体管相比能够具有增加的每单位面积沟道宽度的垂直场效应晶体管是有利的。换句话说,通过使用垂直场效应晶体管构成用于低端开关的功率MOS Q2,能减小导通电阻,由此即使经过非绝缘DC-DC转换器1的电流增加,也能提高电压转换效率。
输出节点N1用于供给输出电源电位至外部,该节点N1布置在如图1所示的非绝缘DC-DC转换器1的功率MOS Q1的源极和功率MOS Q2的漏极之间的互连中。输出节点N1经由输出互连电连接到线圈L1,并且经由输出互连进一步电连接到负载电路4。在用于连接输出节点N1和线圈L1的输出互连与用于供给参考电位GND的端子之间,SBDD1与功率MOS Q2并联地电连接。这个SBD D1是具有正向电压Vf比功率MOS Q2的寄生二极管Dp的正向电压低的二极管。SBD D1的阳极电连接到用于供给参考电位GND的端子,以及其阴极电连接到用于连接输出节点N1和功率MOS Q2的漏极的输出互连。如上所述SBD D1的连接,使得可以减少在功率MOS Q2截止时的无电流时间期间的电压降低,减小二极管传导损耗以及减小由反向恢复时间(trr)的加快而引起的二极管恢复损耗。
在用于连接线圈L1和负载电路4的输出互连与参考电位GND供给端子之间,电连接电容器C1。作为负载电路4,可以给出上述电子设备的CPU(中央处理单元)或DSP(数字信号处理器)作为一个实施例。图1中的端子ET2,ET3分别是到驱动电路3a,3b的电源电压供给端子。
在这种电路中,使功率MOS Q1,Q2同步的同时,通过交替地导通/截止功率MOS Q1,Q2,执行电源电压的转换。具体地说,当用于高端开关的功率MOS Q1导通时,电流(第一电流)I1从电连接到功率MOS Q1的漏极的端子ET1,经由功率MOS Q1流到输出节点N1。当用于高端开关的功率MOS Q1截止时,电流I2通过线圈L1的反电动势而流动。当这个电流I2流动时,通过导通用于低端开关的功率MOS Q2,能减小电压降。上述电流I1例如是约20A的大电流。
图4说明了通过将低端功率MOS Q2和SBD D1形成在各自的半导体芯片上所得到的非绝缘DC-DC转换器50A的结构的一个实施例。在这个非绝缘DC-DC转换器50A中,用于高端开关的功率MOS Q1、用于低端开关的功率MOS Q2、驱动电路3a,3b、和肖特基势垒二极管D1形成在各自的半导体芯片5a至5d上方。但是,本发明人已经发现这种结构具有下述三个问题。
第一个问题是,由于SBD D1形成在另一个芯片上,所以将另外由SBD D1带来的电压转换效率提高效果的出现受到影响。具体地说,产生这个问题,是因为电连接SBD D1阴极和非绝缘DC-DC转换器50A输出互连的互连与电连接SBD D1阳极和接地互连的互连均不可避免地具有一个长的通路,这就增加了寄生到这些互连的寄生电感LK,La;非绝缘DC-DC转换器50A的无电流时间期间(两个功率MOS Q1,Q2均截止时期)负载电流的传递被寄生电感Lk,La禁止,且电流没有平稳地流到SBD D1,而是流到功率MOS Q2的寄生二极Dp;结果,尽管连接了具有正向电压比体二极管Dp的正向电压低的SBD D1,对于降低二极管传导损耗和由反向恢复时间(trr)的加快而引起的二极管恢复损耗,还是不能得到足够的效果。近年来,在非绝缘DC-DC转换器中,非绝缘DC-DC转换器所必需的驱动电流随着负载电路4的驱动电流的增加而增加,并且另外,从稳定供给恒定电压和小尺寸化线圈L1和电容器C1(通过减少元件数目来减小整个尺寸)的观点出发,非绝缘DC-DC转换器的工作频率在增加,所以由于互连的电感Lk,La而引起的上述问题变得越来越显著。
第二个问题是,由于互连的寄生电感LK,La影响负载电流至SBDD1的传递,而在其上方形成有驱动电路3a,3b的驱动芯片(半导体芯片5c)中所产生的问题。接下来将参照图5和图6,阐述这个问题。图5是非绝缘DC-DC转换器的电路的说明性视图,包括驱动电路3a,3b,以及它们的输出级,而图6是在其上方形成有驱动电路3a的半导体芯片5c的寄生元件的特性的说明性视图。图5的端子ET4是用于供给参考电位GND的端子,而端子ET5是非绝缘DC-DC转换器1的输出端子。端子ET6(BOOT)是用于自举电路(boot strapcircuit)的端子,该自举电路用来控制用于高端开关的功率MOS Q1的栅极。由于功率MOS Q1的源极电位相对于参考电位GND要高(不合理),所以它供给来自端子ET6的电压。“UVL”代表的是保护电路,具有这样的功能,即自动终止非绝缘DC-DC转换器1输出的产生,判断当端子ET5和端子ET6之间的电压没有达到一定的参考电压时可能发生异常操作。“GH”代表用于高端开关的功率MOS Q1的栅极。图6的半导体衬底SUB是半导体芯片5c的衬底部分,并且它由例如p型硅(Si)单晶制成。在这个图中,“NISO”意指n型半导体区域,“PW”意指p型半导体区域(p阱),“CHN”意指n型半导体区域,在该n型半导体区域中要形成p沟道功率MOS Q3的沟道,“CHP”意指p型半导体区域,在该p型半导体区域中要形成n沟道功率MOS Q4的沟道,“PR1”是用于p沟道功率MOS Q3的源·漏的p+型半导体区域,以及“NR1”是用于n沟道功率MOS Q4的源·漏的n+型半导体区域。
在这种结构中,当两个功率MOS Q1和Q2均处于无电流时间时,负载电流通过SBD D1进给。当流到SBD D1的负载电流由于互连的寄生电感Lk,La而变小,并且在施加重负载下负载电流还流到用于低端开关的功率MOS Q2的寄生二极管(体二极管)Dp时,产生下列问题。非绝缘DC-DC转换器50A的输出侧上的端子ET5(VSWH)的电位,由寄生二极管Dp的正向电压Vf降低到负电位,这也就将电连接到功率MOS Q1的驱动芯片(控制IC)的输出降低到负电位,由此在半导体芯片5c中寄生npn型双极晶体管Qp导通,导致驱动芯片的消耗电流增加。另外,当来自端子ET6(BOOT)的电荷的抽取(extraction)量变大,并且端子ET5和ET6之间的电位变得低于特定电位值时,产生保护电路UVL的故障,即终止功率MOS Q1的自动操作。
第三个问题是系统尺寸不可避免的增加,因为肖特基势垒二极管D1形成在另一个管壳中。尤其当通过电连接多个非绝缘DC-DC转换器至一个负载电路4,并且形成在另一个管壳中的肖特基势垒二极管连接到每一个非绝缘DC-DC转换器,来构成整个系统时,整个系统的小尺寸化受到限制。
在实施方式1中,如后面所述,功率MOS Q2和SBD D1形成在一个半导体芯片中。这使得可以急剧地减小寄生到连接功率MOS Q2和SBD D1的互连上的寄生电感La,Lk,由此引起电流在无电流时间期间流到SBD D1,而不是体二极管Dp。简而言之,通过这种结构,SBDD1能够充分呈现它的功能。因此,能减小二极管的传导损耗和恢复损耗,这带来非绝缘DC-DC转换器的电源电压转换效率的提高。另外,由于SBD D1能够充分呈现它的作用,所以可以抑制或防止在其上方形成有驱动电路3a,3b的半导体芯片5c中寄生npn型双极晶体管Qp导通,以及可以抑制或防止半导体芯片5c中的电路的消耗电流的增加。此外,能抑制来自如图5中所示端子ET6的电荷的抽取,所以可以抑制或防止端子ET5和ET6之间的电位变得低于特定的电位值。这就使得可以通过保护电路UVL的操作,抑制或防止功率MOS Q1的终止(故障),由此提高非绝缘DC-DC转换器1的操作可靠性。除了这些优点之外,还能实现系统的小尺寸化,因为SBD D1形成在其上方形成有功率MOS Q2的半导体芯片5b中。
图7是当前使用的半导体芯片51的整个平面图的一个实施例,该芯片51是由本发明人已经研究的芯片,其上方形成有用于低端开关的功率MOS Q2。在图7中,“X”意指第一方向,而“Y”意指与第一方向成直角的第二方向。
在这个半导体芯片51的主表面上方,沿半导体芯片51的外围形成栅极指6a。在半导体芯片51的一个角的附近,宽宽度的键合焊盘(以下简称“焊盘”)6BP与栅极指6a集成,该焊盘6BP用于功率MOS Q2的栅极电极。在半导体芯片51的主表面上的中心处,没有设置栅极指,而是放置焊盘BP50,该焊盘BP50用于功率MOS Q2的源极电极和SBD D1的阳极电极。在半导体芯片51的较长方向(第一方向X)的中心处,布置SBD D1的形成区域SDR,以在较短方向(第二方向Y)上从半导体芯片51的一端侧延伸到另一相对端侧。在这个SBD D1的形成区域SDR的右侧和左侧上,都设有功率MOS Q2的多个单位晶体管单元。
但是,在仅半导体芯片51的主表面外围处具有栅极指6a的这种结构中,功率MOS Q2的栅极电阻不能被减小,这就延迟了开关速度。本发明人已经首次发现,尤其当这种结构应用到非绝缘DC-DC转换器1的功率MOS Q2时,自导通现象变得非常显著,并且在低端功率MOS Q2的栅极电阻超过一定值后,转换器的损耗表现为急剧增加。术语“自导通现象”意指这样的现象,即当低端功率MOS Q2截止且高端功率MOS Q1导通时,连接低端功率MOS Q2和高端功率MOS Q1的互连的电位增加,并且低端功率MOS Q2的栅极电压根据低端功率MOS Q2漏-栅电容与源-栅电容之比而增加,由此产生故障,即低端功率MOS Q2的导通。图8说明了损耗对低端功率MOS Q2的栅极电阻依赖关系的大致计算结果,该结果是在例如下列条件下得到的:用于输入的电源电位Vin为12V,输出电压Vout为1.3V,输出电流Iout为25A,以及工作频率为1MHz。当标示在横坐标轴上的电阻(低端功率MOS Q2的栅极电阻+驱动电路3b的输出级的电阻)超过2.4Ω时,自导通现象开始出现并且损耗增加。由于非绝缘DC-DC转换器1的电流不是很大,以及这个非绝缘DC-DC转换器1的频率低,所以由于自导通现象而引起的损耗增加很小,并且与高端功率MOSQ1的栅极电阻相比,很少关注低端功率MOS Q2的栅极电阻。但是,随着如上所述非绝缘DC-DC转换器1的电流和频率的增加,自导通现象导致的损耗增加已经变成了问题。
在这个实施方式1中,为了降低低端功率MOS Q2的栅极电阻,还在半导体芯片5b的主表面上的有源区域中,设置多个栅极指(金属栅极互连)。通过这个结构,能抑制自导通现象,这也就带来非绝缘DC-DC转换器1的损耗的减小。通过采用这种结构,还可以克服近来对非绝缘DC-DC转换器1的电流和频率增加的要求。
在图9至图17中将说明根据实施方式1的半导体芯片5b的特定实施例,在该芯片5b的上方形成有低端功率MOS Q2和SBD D1。
图9是半导体芯片5b的整个平面图。图9是平面图,但是给栅极指6a,6b和焊盘BP1画上了阴影,以便于图的理解。
半导体芯片5b的平面形状例如是在第一方向X长于在第二方向Y的长方形。在第二方向Y上,半导体芯片5b主表面的中心处,设置SBD D1的形成区域SDR,以在第一方向X上从一端侧延伸到相对端侧。在第二方向Y上,SBD D1的形成区域SDR之上和之下,布置构成功率MOS Q2的多个单位晶体管单元组形成区域,以在其间插入SBD D1形成区域。从另一个观点出发,通过设置SBD D1的形成区域SDR,将在半导体芯片5b的主表面上的多个单位晶体管单元组形成区域,垂直地大致分成两部分。
在实施方式1中,功率MOS Q2的多个单位晶体管单元排列在SBDD1的上侧和下侧上(特别地,半导体芯片5b主表面上的功率MOS Q2的多个单位晶体管单元形成区域被SBD D1的形成区域SDR大致均匀地分成两部分),所以与当SBD D1的形成区域SDR靠近一端设置时的距离相比,能缩短从SBD D1到功率MOS Q2的单位晶体管单元的其中最远的距离。在分割时,形成区域被分成两部分,不是在较长方向(第一方向X)上,而是在较短方向(第二方向Y)上。与图7情形下的距离相比,这使得可以缩短从SBD D1到MOS Q2的单位晶体管单元的其中最远的距离。通过使SBD D1的形成区域SDR沿半导体芯片5b的较长方向(第一方向X)延伸,能使邻近SBD D1的功率MOS Q2的单位晶体管的数目大于图7情形下的该数目。这能够使得在半导体芯片5b中的功率MOS Q2的多个单位晶体管单元上方的SBDD1的功能更有效地呈现,从而带来非绝缘DC-DC转换器1的损耗的减小。
在这个半导体芯片5b的主表面上,类似于图7地布置栅极指(第一金属栅极互连)6a和焊盘6BP,除了在功率MOS Q2的多个单位晶体管单元组形成区域上方形成多个栅极指(第二金属栅极互连)6b之外。栅极指6b均与外围的栅极指6a集成。该栅极指6b在第二方向Y上从半导体芯片5b长侧上的栅极指6a的多个位置,向邻近半导体芯片5b中心处的SBD D1形成区域SDR的位置延伸,以便与栅极指6a一起插入SBD D1的形成区域SDR。通过在功率MOS Q2的多个单位晶体管单元组形成区域上均匀地布置栅极指6b,能减小功率MOS Q2的栅极电阻,并且能抑制自导通现象。这就带来非绝缘DC-DC转换器1的损耗的减小,使得可以克服非绝缘DC-DC转换器1的电流增加和频率升高。而且在这个实施方式1中,由于SBD D1的形成区域SDR在较短方向(第二方向Y)上布置在半导体芯片5b的中心处,所以能使栅极指6b比在SBD D1的形成区域SDR靠近一端布置时要短。换句话说,能使功率MOS Q2的栅极电阻比在SBD D1的形成区域SDR靠近一端布置时要低。由于上述原因,通过在上述位置布置SBD D1的形成区域SDR,SBD D1能形成在其上方形成有功率MOSQ2的半导体芯片上,而不会破坏用于减小功率MOS Q2的栅极电阻的作用。
在半导体芯片5b的主表面上,焊盘BP1在由栅极指6a和6b环绕的区域中形成为一个平面梳状图形。这里说明的焊盘BP1在上部和下部(第二方向)上具有齿。这个焊盘BP1用作功率MOS Q2的源极电极和SBD D1的阳极电极公用的电极。栅极指6a,6b和焊盘6BP及焊盘BP1通过蚀刻构图一个金属形成,但它们彼此是隔离的。
图10是在给图9的半导体芯片5b加上键合导线(以下将简称“导线”)WA和外部电极(端子)7E之后,半导体芯片5b的整个平面图。图10是平面图,但是给栅极指6a,6b和焊盘BP1画上了阴影,以便于图的理解。
在这个图中,平面L形外部电极7E沿半导体芯片5b的一个短边和一个长边布置。这个外部电极7E经由多个导线WA电连接到用于源极和阳极的焊盘BP1。导线WA均由细金属导线制成,该细金属导线由例如金(Au)制成。在这个实施方式1中,通过在半导体芯片5b的较短方向(第二方向Y)的中心处设置SBD D1,能抑制SBD D1和外部电极7E之间距离的增加。这就防止在SBD D1阳极侧上的寄生电感La增加。另外,通过在半导体芯片5b的较短方向(第二方向Y)的中心处设置SBD D1,还能抑制功率MOS Q2和外部电极7E之间距离的增加。这就防止功率MOS Q2的源极侧上的寄生电感和阻抗增加,带来对功率MOS Q2损耗增加的抑制。通过使SBD D1沿半导体芯片5b的较长方向(第一方向X)延伸,可以尽可能多地布置用于SBD D1和功率MOS Q2的导线WA,由此可以减小SBD D1阳极侧和功率MOS Q2源极侧上的寄生电感和阻抗。以这种方式,能减小非绝缘DC-DC转换器1的损耗。
图11是图9的区域A的放大平面图,图12是沿图11的Y1-Y1线所取的横截面图,图13是沿图11的Y2-Y2线所取的横截面图,图14是SBD D1的局部放大横截面图,图15是功率MOS Q2的单位晶体管单元的放大横截面图,图16是沿图11的X1-X1线所取的横截面图,以及图17是图16的局部放大横截面图。为了便于图的理解,在图11中,省略了焊盘BP1,透视栅极指6a,6b,同时为了便于理解位于焊盘BP1和栅极指6a,6b之下的栅极图形8(栅极电极8G和栅极互连8L),用梨面修饰(pearskin finish)说明栅极图形8。
半导体芯片5b具有其上要形成元件的主表面(器件形成表面:第一表面)和与该主表面相对且其上要形成背面电极LBE的背侧表面(背面电极形成表面:第二表面)。构成半导体芯片5b的半导体衬底(第一半导体层)5LS例如由n+型硅单晶制成,以及由n-型硅单晶制成的外延层(第二半导体层)5LEP位于该衬底上方。在这个外延层5LEP的主表面上方,形成一个由氧化硅(SiO2等)制成的场绝缘膜FLD。在由这个场绝缘膜FLD和位于其之下的p阱PWL1所环绕的有源区域中,形成功率MOS Q2的多个单位晶体管单元和SBD D1。在外延层5LEP的主表面上方,上述焊盘BP1经由诸如PSG(磷硅玻璃)之类的绝缘层9a形成。焊盘BP1具有例如通过顺次连续层叠诸如钛钨(TiW)的阻挡金属层10a和诸如铝(A1)的金属层10b得到的结构,如图14中所示。在SBD D1的形成区域SDR中,焊盘BP1的阻挡金属层10a经由形成在绝缘层9a中的接触孔11a与外延层5LEP主表面相接触,以及在阻挡金属层10a和外延层5LEP的接触位置处形成SBD D1。为了减小SBD D1的泄漏电流,将外延层5LEP的杂质浓度调整到稍微低的水平,例如约5×1015/cm3。
在由栅极指6a,6b和SBD D1的形成区域SDR所环绕的有源区域中,设置功率MOS Q2的多个单位晶体管单元形成区域LQR。在这个形成区域LQR中,形成具有例如沟槽结构的n沟道型垂直功率MOSQ2。采用沟槽栅极结构能够实现功率MOS Q2的单位晶体管单元的小型化和高度集成。这个单位晶体管单元具有半导体衬底5LS和具有作为漏极区域功能的n阱NWL1,具有作为沟道形成区域功能的p型半导体区域(第三半导体层)12,具有作为源极区域功能的n+型半导体区域(第四半导体层)13,在外延层5LEP的厚度方向上制作的沟槽(第一沟槽)14,在沟槽14的底表面和侧表面上形成的栅极绝缘膜15,以及经由栅极绝缘膜15埋在沟槽14中的栅极电极8G。由于如上所述将外延层5LEP的杂质浓度调整到稍微低的水平,在单位晶体管形成区域LQR中的外延层5LEP的电阻分量不可避免地变大,以及当如上所述在外延层5LEP中形成功率MOS Q2的单位晶体管单元时,功率MOS Q2的导通电阻增加。一个深的n阱NWL1因此形成在功率MOS Q2的多个单位晶体管形成区域LQR中,以增加外延层5LEP的杂质浓度至例如约2×1016/cm3。这使得可以实现SBD D1的泄漏电流的减小和在具有SBD D1和功率MOS Q2的半导体芯片5b中的功率MOS Q2的导通电阻的减小。
在这个实施方式中,采用排列成条形的沟槽14和栅极电极8G作为实施例。具体地说,在功率MOS Q2的每个单位晶体管组形成区域中,以平面条形在第一方向X上延伸的多个栅极电极8G沿第二方向Y排列。沟槽14和栅极电极8G的平面排列形状不限于这种条形,而是可以采用各种形状。例如,它们可以排列成平面格子形状。制作沟槽14的深度达到n阱NWL1。栅极电极8G由例如低电阻多晶硅制成,并经由与其集成且由多晶硅制成的栅极互连8L,被拉到场绝缘膜FLD的上方。栅极电极8G和栅极互连8L的表面覆盖有绝缘层9a,以有效地与焊盘BP1绝缘。栅极互连8L经由形成在绝缘层9a中的接触孔11b电连接到栅极指6a,6b。栅极指6a,6b均具有类似于焊盘BP1的结构。在功率MOS Q2的多个单位晶体管单元形成区域LQR中,焊盘BP1经由形成在绝缘层9a中的接触孔11c电连接到用于源极的n+型半导体区域13,并且另外,经由在外延层5LEP中制作的沟槽16电连接到p+型半导体区域17,经此还电连接到用于沟道形成的p型半导体区域12。在每个单位晶体管单元中,使功率MOSQ2的工作电流在n阱NWL1和n+型半导体区域13之间,沿栅极电极8G的侧表面(即沟槽14的侧表面)在半导体衬底5LS的厚度方向上流动。在这种垂直功率MOS Q2中,每单位晶体管单元面积的栅极面积以及栅极电极8G与漏极漂移层的接合面积,大于水平场效应晶体管(其沟道形成在相对于半导体衬底主表面的水平方向上)的该面积,所以尽管栅—漏寄生电容增加,但是还可以增加每单位晶体管单元面积的沟道宽度,以及减小导通电阻。
在半导体芯片5b主表面上的最上层上,沉积表面保护膜18。表面保护膜18是由氧化硅膜和氮化硅(Si3N4)膜层叠的膜,或是通过在其上方层叠诸如聚酰亚胺膜(PiQ)的有机膜得到的膜。栅极指6a,6b具有覆盖有表面保护膜18的表面,而焊盘BP1,6BP经由在表面保护膜18的一个部分中形成的开口部分19部分地露出。这个露出区域用作其中连接导线的键合区域。在半导体衬底5LS的背侧表面上,形成由例如金(Au)制成的背面电极LBE。这个背面电极LBE是功率MOS Q2的漏极电极和SBD D1的阴极电极公用的电极。
图18表示对无电流时间期间传递到SBD的电流的计算结果的比较,IA(虚线)是当SBD和MOS形成在各自的半导体芯片上时的该电流,IB(实线)是当如在实施方式1中那样SBD和MOS形成在一个半导体芯片中时的该电流。
通过将SBD的面积设定为例如2mm2,同时对于MOS和SBD之间的寄生电感,在SBD形成在不同半导体芯片上时将其设定为1nH,在SBD形成在同一半导体芯片上时将其设定为0.1nH来进行计算。计算条件如下:用于输入的电源电位Vin=12V,输出电压Vout=1.3V,输出电流Iout=25A,以及工作频率f=1MHz,从图18可以明显看出,当如实施方式1那样SBD和MOS形成在一个半导体芯片中时,比当SBD形成在另一个半导体芯片中时,无电流时间期间传递到SBD的电流要多。SBD以较小的损耗快速工作,因为SBD的正向电压比寄生二极管(体二极管Dp)的正向电压低,且电子有利于操作。因此通过大电流到SBD的流动,可以减小无电流时间期间的传导损耗和恢复损耗。
图19表示在SBD和MOS形成在各自的半导体芯片上时和在SBD和MOS形成在一个半导体芯片上时损耗的计算结果。与没有SBD的半导体芯片相比,当SBD形成在不同芯片上时损耗较小。通过将SBD和MOS形成在一个半导体芯片上,产生大电流传递到SBD,这可以减小MOS的寄生二极管(体二极管)的传导损耗和恢复损耗。结果,当SBD和MOS形成在一个芯片上时,可以最有效地减小损耗。
图20是说明管壳20A内的结构实施例的平面图,该管壳20A具有上述半导体芯片5a,5b容纳在其中。图21是沿图20的X2-X2线所取的横截面图。为了便于图的理解,从其中省略掉树脂密封体MB。
在管壳20A中,两个芯片焊盘7a1和7a2邻近引线7b(7b1,7b2,7b3,7b6和7b7)排列,该引线7b围绕这两个芯片焊盘布置。在芯片焊盘7a1上方,设置其上方形成有用于高端开关的功率MOS Q1的半导体芯片5a,并使该芯片5a主表面向上。在半导体芯片5a的主表面上方,排列用于功率MOS Q1每个的源极电极的焊盘BP2和用于其栅极电极的焊盘6BP1。用于源极电极的这个焊盘BP2,经由多个导线WA1电连接到与芯片焊盘7a2集成的引线7b3。用于栅极电极的焊盘6BP1经由导线WB2电连接到引线7b6。输出信号从驱动电路3a输入到这个引线7b6。半导体芯片5a的背面用作要连接到功率MOS Q1漏极的漏极电极,并且经由芯片焊盘7a1电连接到与芯片焊盘7a1的外围集成的多个引线7b1。这个引线7b1电连接到端子ET1。导线WA1设置排列成Z字形,从而在第一方向X上彼此相邻的任何两个导线WA1交替地连接到上和下焊盘BP2。
在相对大些的芯片焊盘7a2上方,设置在其上方形成有用于低端开关的功率MOS Q2的半导体芯片5b,并使该芯片5b主表面向上。半导体芯片5b的焊盘BP1经由多个导线WA2电连接到引线7b2(7b),以及焊盘6BP2经由多个导线WB3电连接到引线7b7。输出信号从驱动电路3b输入到这个引线7b7。半导体芯片5b的背面电极LBE,经由芯片焊盘7a2电连接到与芯片焊盘7a2的外围集成的多个引线7b3(7b)。这些引线7b3电连接到用于输出的端子ET5。
这两个半导体芯片5a和5b,以及导线WA1,WA2,WB2和WB3,密封在树脂密封体MB中。通过将这两个半导体芯片5a和5b容纳在一个管壳20A中,能减小半导体芯片5a和5b之间的寄生电感,这带来损耗的减小。半导体芯片5a的结构以及半导体芯片5a和5b的排列将在下面以另一个实施方式更详细地描述。
图22是图20的修改实施例的平面图,而图23是沿图22的X3-X3线所取的横截面图。为了便于图的理解,从中省略掉树脂密封体MB。
在这个修改实施例中,焊盘BP2和引线7b3,以及焊盘BP1和引线7b2通过金属板互连21连接,而不是通过导线连接。这个金属板互连21由诸如铜(Cu)或铝(Al)的金属制成,并经由凸起电极22电连接到焊盘BP1,BP2,以及引线7b2,7b3。凸起电极22例如由诸如铅(Pb)/锡(Sn)或金(Au)的金属制成。凸起电极22可以用导电树脂代替。金属板互连21也可以由树脂密封体MB整个覆盖。
通过使用金属板互连21代替导线,能进一步减小寄生在互连通路上的电感和阻抗,并因此能进一步减小开关损耗和传导损耗。结构,能进一步提高非绝缘DC-DC转换器1的电压转换效率。
另外,SBD D1的阳极电极经由大面积的金属板互连21电连接到参考电位GND,所以能急剧地减小阳极侧上的互连电阻和寄生到阳极电极侧上的电感La。这就使得可以增强SBD D1的作用,由此减小二极管传导损耗和二极管恢复损耗,并进一步提高非绝缘DC-DC转换器1的电压转换效率。由于能减小电感Lk、La,所以能实现噪声的进一步减小。
图24是图22的修改实施例,并且是沿图22的X3-X3线所取部分的横截面图。
在这个修改实施例中,焊盘BP2和引线7b3,以及焊盘BP1和引线7b2通过金属板互连21连接。金属板互连21从树脂密封体MB部分地露出。该金属板互连21布置成特别地覆盖功率MOS Q1和Q2的形成区域,该功率MOS Q1和Q2是半导体芯片5a和5b的热量产生源。在这个修改实施例中,覆盖半导体芯片5a和5b的两个金属板互连21,从树脂密封体MB的上表面露出。取而代之,可以仅露出在半导体芯片5b侧上的金属板互连21,在该半导体芯片5b的上方形成有用于低端开关的功率MOS Q2,其具有相对较高的热产生量。通过在树脂密封体MB的上表面上设置散热片,并将它键合到金属板互连21的露出表面上,能进一步提高散热特性。根据图24的结构,由于金属板互连21本身装备有散热功能,而不需要另外的部件用来散热,所以与包括散热部件添加步骤的工序相比,能简化半导体器件的制造工序,并且能减小半导体器件的制造时间。另外,由于部件数目的减少,能实现半导体器件的损耗减小。
(实施方式2)
在实施方式2中将描述半导体芯片中的SBD的布置位置的修改实施例。图25是半导体芯片5b的整个平面图,而图26是给图25的半导体芯片5b加上导线WA和外部电极7E后的半导体芯片5b的整个平面图。尽管图25和图26是平面图,但给栅极指6a和6b以及焊盘BP1画上了阴影,以便于图的理解。
在这个实施方式2中,SBD D1的形成区域SDR靠近半导体芯片5b一侧上的长边布置。特别地,SBD D1的形成区域SDR在靠近如图26所示的外部电极7E的长边上布置。通过这种排列,能减小SBD D1的阳极侧上的寄生电感,由此能将较大电流传递到SBD D1。与实施方式1相比,这能够使得更多地减小二极管的传导损耗和恢复损耗。基于图9和图10所述的实施方式1的结构或实施方式2的结构中哪一个最有效,是根据实际使用条件而不同的。在其中无电流时间期间二极管的传导损耗或恢复损耗占支配地位的使用条件下,推荐使用如实施方式2中的结构。在其中MOS的传导损耗占支配地位的使用条件下,推荐使用如参照图9和图10在实施方式1中所述的结构。根据非绝缘DC-DC转换器1的使用条件,适当地使用这些结构。
栅极指6b从在半导体芯片5b一个长边上的栅极指6a,延伸到SBD D1的形成区域SDR附近。SBD D1的形成区域SDR因此插入在栅极指6a和栅极指6b之间。焊盘BP1在其一边上是带齿的梳状形式。
(实施方式3)
在实施方式3中,将描述半导体芯片中SBD的排列位置的另一个修改实施例。图27是半导体芯片5b的整个平面图,而图28是给图27加上导线WA和外部电极7E后的半导体芯片5b的整个平面图。图27和图28均是平面图,但给栅极指6a和6b以及焊盘BP1画上了阴影,以便于图的理解。
在实施方式3中,SBD D1的形成区域SDR靠近半导体芯片5b的一个短边布置。SBD D1的形成区域SDR沿半导体芯片5b的短边(第二方向Y)延伸。特别地,如图28中所示,SBD D1的形成区域SDR布置在靠近外部电极7E的短边上。通过这样的排列,能减小SBD D1的阳极侧上的寄生电感,并因此能将较大电流传递到SBD D1。与实施方式1相比,这能够实现二极管传导损耗和恢复损耗的进一步减小。
在这个实施方式3中,SBD D1的形成区域SDR布置在与用于栅极的焊盘6BP的排列位置相对的位置处,由此能彼此互不影响地排列连接到焊盘BP1的导线WA和连接到用于栅极的焊盘6BP的导线。
栅极指6b从在半导体芯片5b一个长边上的栅极指6a延伸到在芯片另一个长边上的栅极指6a附近,由此SBD D1的形成区域SDR在其四边处被栅极指6a和6b所环绕。另外,可以通过将栅极指6b进一步延伸,以连接一个长边上的栅极指6a和另一个长边上的栅极指6a,来隔离单个的焊盘BP1和单位晶体管单元组。但是,在这种情况下,当检查功率MOS Q2的多个单位晶体管单元时,必须对被栅极指6b分开的每个焊盘BP1执行单位晶体管组的检查。在这个实施方式3中,焊盘BP1作为一个整体形成,而没有被栅极指6a完全分开,由此能通过单一检查完成对功率MOS Q2的多个单位晶体管的检查。
(实施方式4)
在实施方式1中,描述了具有低端功率MOS和SBD形成在一个半导体芯片上的结构。当在图4的非绝缘DC-DC转换器50A中,半导体芯片5a至5d容纳在各自的管壳中时,产生如下所述的问题,并且减小了将低端功率MOS和SBD形成在一个芯片上的作用。在这个实施方式4中,将描述一种能够克服这些问题的结构实施例。
首先,将描述这些问题。通过将用于高端开关的功率MOS Q1、用于低端开关的功率MOS Q2、驱动电路3a和3b、以及肖特基势垒二极管D1如图4所示容纳在各自的管壳中,半导体芯片5a至5d(管壳)之间的互连通路变长,以及寄生在这些互连部分上的电感增加。结果,作为问题,产生非绝缘DC-DC转换器50A的电压转换效率的降低。图29是说明寄生到非绝缘DC-DC转换器50A的电感分量的等效电路。符号LdH,LgH,LsH,LdL,LgL,以及LsL代表寄生到功率MOS Q1和Q2以及印刷电路板互连上的电感。“VgH”代表用于导通功率MOS Q1的栅极电压,而“VgL”代表用于导通功率MOS Q2的栅极电压。受到寄生在用于高端开关的功率MOS Q1的源极侧的电感LsH,和寄生在其栅极侧的电感LgH,以及寄生在用于低端开关的功率MOS Q2的源极侧的电感LsL的影响,非绝缘DC-DC转换器50A的电压转换效率降低。尤其寄生电感LsH的增加引起用于高端开关的功率MOS Q1的导通损耗和截止损耗(特别是导通损耗)显著增加,导致非绝缘DC-DC转换器50A的电压转换效率急剧降低。导通损耗和截止损耗与频率和输出电流成比例,所以损耗分量随着非绝缘DC-DC转换器50A的电流增加和频率升高的进行而变大。
其次,将描述为什么寄生电感LsH的增加伴随着导通和截止的延迟以及导通损耗和截止损耗的增加。图30是非绝缘DC-DC转换器50A的电路操作的说明性视图,而图31是图30的电路操作时器件横截面的说明性视图。
当用于高端开关的功率MOS Q1的栅极电压超过阈值电压,以及电流(第一电流)I1开始从功率MOS Q1的漏极区域DR1流动到其源极区域SR1时,由寄生电感LsH产生反电动势(LsH×di/dt),由此用于高端开关的功率MOS Q1的源极电位变得高于输出节点N1的电位。功率MOS Q1的栅极电压由驱动电路3a以输出节点N1作为参考来进给,所以在要连接到用于高端开关的功率MOS Q1栅极的栅极电极G1和源极区域SR1之间供给的电压变得低于栅极电压VgH。由于用于高端开关的功率MOS Q1的沟道电阻R1没有足够减小,所以产生电流I1的损耗,换句话说,截止时间增加。导通损耗和截止损耗随电流和频率增加而增加的原因是,因为反电动势(LsH×di/dt)随电流和频率增加而增加。
用于高端开关的功率MOS Q1具有开关功能,用于在用来向非绝缘DC-DC转换器50A的输出(负载电路4的输入)供给电流的线圈L1中存储能量,从而加速开关操作,满足频率增加的需求。但是在驱动电路3a和功率MOS Q1之间产生的寄生电感LgH延迟了开关操作。换句话说,它产生开关损耗,带来电压转换效率的降低。
另一方面,用于低端开关的功率MOS Q2与功率MOS Q1相比,具有不容易引起这种开关损耗的结构。具体地说,当用于高端开关的功率MOS Q1截止时,电流(第二电流)I21经由与用于低端开关的功率MOS Q2并联连接的肖特基势垒二极管D1流到输出端,以及同时,电流(第二电流)I22经由寄生二极管Dp从参考电位GND流向功率MOS Q2的漏极区域DR2。当在这种状态下时,通过将栅极电压VgL施加到要连接到用于低端开关的功率MOS Q2栅极的栅极电极G2上,用于低端开关的功率MOS Q2导通,电流(第三电流)I23经由功率MOS Q2的沟道区域从功率MOS Q2的源极区域SR2流向漏极区域DR2。在电流I23流动之前,上述电流I21和I22已经流动。在电流I23流动时每单位时间的电流变化量很小,所以由寄生电感LsL产生的反电动势可忽略地小,而且它不会引起实质上的损耗。另一方面,当如上所述寄生在肖特基势垒二极管D1的阳极和阴极侧上的电感La、Lk较大时,在肖特基势垒二极管D1侧上流动的电流I21变小,并且通过连接具有正向电压小于寄生二极管Dp的正向电压的肖特基势垒二极管D1,没有产生足够的效果。寄生二极管Dp还存在于用于高端开关的功率MOS Q1中,但由于用于高端开关的功率MOSQ1侧上的寄生二极管Dp,具有形成在功率MOS Q1的源极区域SR1侧上的阳极和形成在功率MOS Q1的漏极区域DR1侧上的阴极,它不是在正向方向上连接,该正向方向是相对于与从功率MOS Q1的漏极区域DR1流到其源极区域SR1的电流(第一电流)I1相同的方向而言的。在通过施加栅极电压VgH导通功率MOS Q1之前,功率MOS Q1没有电流,以及没有产生每单位时间的电流变化量的减少,从而开关损耗产生。
功率MOS Q2是用于整流非绝缘DC-DC转换器50A的晶体管,并具有在与来自控制电路2的频率相同步地降低晶体管电阻的同时,进行整流的功能。由于如上所述功率MOS Q2的导通时间比功率MOSQ1的导通时间长,由于导通电阻而引起的损耗变得比开关损耗更突出。因此需要降低导通电阻。寄生电感LsL在功率MOS Q2和供有参考电位GND的端子(第二电源端子)ET4之间,由于该寄生电感LsL所产生的互连电阻(互连阻抗),导通电阻增加,以及电流转换效率降低。
在这个实施方式4中,其上方形成有用于高端开关的功率MOS Q1的半导体芯片5a,其上方形成有用于低端开关的功率MOS Q2和SBDD1的半导体芯片5b,以及其上方形成有驱动电路3a和3b的半导体芯片5c,各自构成如图1所示非绝缘DC-DC转换器1的一部分,且它们容纳在一个管壳中。与将这些芯片容纳在各自的管壳中相比,通过将半导体芯片5a至5c容纳在一个管壳中,能缩短半导体芯片5a至5c每一个的互连通路。这能够使得减小寄生在这些互连上的电感LdH,LgH,LsH,LdL,LgL以及LsL,从而提高非绝缘DC-DC转换器1的电压转换效率,并且使非绝缘DC-DC转换器1小尺寸化。
尽管考虑到仅小尺寸化和电感的减小,优选将用于高端开关的功率MOS Q1和用于低端开关的功率MOS Q2形成在一个半导体芯片上,但是当这些晶体管形成在一个半导体芯片上时,它们的元件特性不能被充分地呈现。另外,这样会使制造工序复杂化,以及增加制造半导体芯片所需的时间和成本。用于低端开关的功率MOS Q2易于产生热量,因为如上所述其导通时间比用于高端开关的功率MOS Q1的导通时间长。当功率MOS Q1和Q2两者形成在一个半导体芯片上时,担心在用于低端开关的功率MOS Q2操作时产生的热量通过半导体衬底对用于高端开关的功率MOS Q1具有不利的影响。从这种观点出发,将用于高端开关的功率MOS Q1、用于低端开关的功率MOS Q2、以及驱动电路3a和3b分别形成在半导体芯片5a至5c上。与将用于高端开关的功率MOS Q1、用于低端开关的功率MOS Q2、以及驱动电路3a和3b形成在一个半导体芯片上相比,每个元件能充分呈现其特性。另外,这样便于非绝缘DC-DC转换器1的制造,由此能缩短非绝缘DC-DC转换器1的制造时间,以及同时,能降低生产成本。而且,用于高端开关的功率MOS Q1以及驱动电路3a和3b不会受到用于低端开关的功率MOS Q2操作时产生的热量的不利影响,所以非绝缘DC-DC转换器1能够具有稳定的操作稳定性。驱动电路3a和3b被同步以及交替操作,所以将它们形成在一个半导体芯片5c上方,以保证整个电路操作的稳定性。
如上所述为了提高非绝缘DC-DC转换器1的电压转换效率,重要的是将半导体芯片5a至5c容纳在一个管壳中,但简单地容纳在一个管壳中对于提高电压转换效率是不够的。接下来将描述一个管壳的特定结构实施例,该管壳对于提高非绝缘DC-DC转换器1的电压转换效率是重要的。
图32是管壳20B的主表面侧上的整个平面图,图33是图32的管壳20B的侧视图,图34是图32的管壳20B背侧上的整个平面图,以及图35是图32的管壳20B外观的透视图。
实施方式4的管壳20B具有例如QFN(无引线四方扁平封装)结构。但它不限于QFN,而是可以采用各种结构。例如,还可以采用诸如QFP(四方扁平封装)和SOP(小外形封装)的扁平封装结构。
构成管壳20B的树脂密封体MB具有以薄板制作的外观。树脂密封体MB例如由环氧树脂制成。为了减小应力,可以使用添加有苯酚固化剂、硅酮橡胶和填料的联苯热固性树脂作为树脂密封体MB的材料。树脂密封体MB通过用于大量生产的传递模塑工序来形成。从树脂密封体MB的背面,露出平面上基本呈矩形形状的三个芯片焊盘7a1,7a2和7a3的背面。从树脂密封体MB的四个侧表面以及其背面的外围,多个引线(外部端子)7b沿树脂密封体MB的外围部分地露出。芯片焊盘7a1,7a2和7a3以及引线7b主要由诸如42合金的金属材料组成,以及它们的厚度例如约为200μm。作为用于芯片焊盘7a1,7a2和7a3以及引线7b的另一种材料,可以使用铜(Cu)或其表面逐次镀有镍(Ni)、钯(Pd)和金(Au)的铜。如后面所述,半导体芯片5a和5b分别安装在芯片焊盘7a1和7a2的主表面上,同时半导体芯片5c安装在芯片焊盘7a3的主表面上。在芯片焊盘7a3的一个角上,形成定位锥TR1(指示标记)。这个锥TR1用于当运送或将商标贴于管壳20B而面向管壳20B时,区分管壳20B的主表面和背侧表面。该锥例如通过蚀刻形成。芯片焊盘7a1和7a2上要安装有半导体芯片5a和5b,而该芯片5a和5b上方形成有功率MOS Q1和Q2,从而芯片焊盘7a1和7a2是被供有来自第一和第二电源端子的电流I1和I2的部分,所以形成锥TR1会使其外部尺寸减小,以及这可能对电流特性有影响。由于动态电流没有经过芯片焊盘7a3,且电位固定,所以不必考虑对电流特性的影响。因此,优选在芯片焊盘7a3的部分上形成定位锥TR1。
在这个结构中,芯片焊盘7a1至7a3的背面(与其上安装半导体芯片5a、5b和5c的表面相对的表面)以及引线7b的背面(要与布线衬底的端子结合的表面)存在于管壳20B的安装表面上(当把管壳20B安装在布线衬底上时面向布线衬底的表面)。
图36是当透视管壳20B的内部时,在主表面侧上管壳20B的整个平面图,图37是沿图36的Y3-Y3线所取的横截面图,以及图38是沿图36的X4-X4线所取的横截面图。尽管图36是平面图,但给芯片焊盘7a1至7a3、引线7b以及互连部分7c画上了阴影,以便于这些图的理解。
在管壳20B中,密封上述三个芯片焊盘7a1至7a3(第一至第二芯片安装部分)、如后面所述安装在芯片焊盘7a1至7a3上方的多个半导体芯片5a至5c、以及用于将半导体芯片5a至5c的焊盘BP1至BP11电连接到各自部分的导线WA1,WA2,WB1至WB6。
芯片焊盘7a1至7a3彼此相邻地布置,同时隔开一个预定距离。在半导体芯片5a至5c操作时产生的热量,主要从半导体芯片5a至5c的背面经由芯片焊盘7a1至7a3释放到外部。因此,分别形成芯片焊盘7a1至7a3的面积大于半导体芯片5a至5c的面积。这能够使得提高非绝缘DC-DC转换器1的散热特性,并且提高操作稳定性。通过形成半蚀刻区域,减薄芯片焊盘7a1至7a3以及引线7b背面上的外围部分。形成这个半蚀刻区域,以通过提高芯片焊盘7a1至7a3以及引线7b与树脂密封体MB之间的粘附力,来减少或防止芯片焊盘7a1至7a3以及引线7b的剥离或变形故障。
在图36左上的芯片焊盘7a1上方,布置其上方形成有用于高端开关的功率MOS Q1的半导体芯片5a,并使该芯片5a主表面向上。在半导体芯片5a的主表面上方,布置功率MOS Q1每一个的用于源极电极的焊盘BP2和用于栅极电极的焊盘6BP1。这个用于源极电极的焊盘BP2经由多个导线WA1电连接到芯片焊盘7a2,以及同时,经由多个导线WB1电连接到用于半导体芯片5c的驱动电路3a的源极电极的焊盘BP3。用于栅极电极的焊盘6BP1经由多个导线WB2电连接到用于半导体芯片5c的驱动电路3a的输出(漏极)电极的焊盘BP4。半导体芯片5a的背面用作要连接到功率MOS Q1的漏极的漏极电极,并经由芯片焊盘7a1电连接到与芯片焊盘7a1的外围集成的多个引线7b1(7b)。这些引线7b1电连接到端子ET1。导线WA1布置成Z字形,从而在第一方向X上彼此相邻的两个导线WA1交替地连接到上和下焊盘BP2上。
如图36所示,其上方形成有用于高端开关的功率MOS Q1的半导体芯片5a是矩形的。其在第一方向X上的边比其在与之垂直的第二方向Y上的另一边要长。相对于芯片焊盘7a1的中心,布置半导体芯片5a使得它靠近芯片焊盘7a2。换句话说,靠近芯片焊盘7a1的一边布置半导体芯片5a,该焊盘7a1的该边邻近于芯片焊盘7a2的一边。通过靠近芯片焊盘7a2布置半导体芯片5a,能缩短用于电连接用于功率MOS Q1源极电极的焊盘BP2和芯片焊盘7a2的导线WA1的长度,由此减小在功率MOS Q1的源极和功率MOS Q2的漏极之间产生的寄生电感LsH。以其长边沿邻近的芯片焊盘7a2的长边延伸的这种方式布置半导体芯片5a。这就使得可以保证用于半导体芯片5a的源极电极的焊盘BP2和芯片焊盘7a2的面向长度,由此能够实现多个导线WA1的排列。因此,能减小在功率MOS Q1的源极和功率MOSQ2的漏极之间的电感LsH。另外,能缩短由多晶硅制成的、沿如图36所示的第二方向Y延伸的栅极互连,以及因此能减小功率MOS Q1的栅极电阻,因为半导体芯片5a具有矩形形状。此外,半导体芯片5a布置成使半导体芯片5a和5c之间的距离短于半导体芯片5a和5b之间的距离,以特别地减小用于半导体芯片5a的栅极电极的焊盘6BP1和用于半导体芯片5c的输出电极的焊盘BP4之间的距离。采用这种结构是考虑到用于高端开关的功率MOS Q1的栅极电感增加对开关损耗增加的巨大影响。通过靠近半导体芯片5c布置半导体芯片5a,能减小用于电连接用于功率MOS Q1的栅极电极的焊盘6BP1和用于驱动电路3a的输出电极的焊盘BP4的导线WB2的长度,能减小寄生在功率MOS Q1的栅极上的电感LgH,并因此能减小功率MOS Q1的开关损耗。半导体芯片5a的这种排列使得可以减小功率MOS Q1的开关损耗,并因此提高非绝缘DC-DC转换器1的电压转换效率。
两种导线WA1和WB1电连接到用于半导体芯片5a的源极电极的焊盘BP2。换句话说,将要连接到芯片焊盘7a2的导线WA1和要连接到驱动电路3a源极的导线WB1,适当地用作电连接到用于半导体芯片5a的源极电极的焊盘BP2的导线。这使得可以分散电流,使其流入两个通路,一个通路用于电流I1,该电流I1经由芯片焊盘7a2从功率MOS Q1的源极流向输出端子,而另一个通路用于流向驱动电路3a的电流,由此减小在各自导线WA1和WB1中产生的电流负载。结果,能减小在功率MOS Q1和驱动电路3a之间的寄生电感,从而进一步改善开关损耗。
上述导线WA1、WB1和WB2例如由金(Au)制成,并且导线WA1比导线WB1和WB2要粗。这使得可以减小功率MOS Q1的源极侧上的互连电感,减小非绝缘DC-DC转换器1的开关损耗,以及因此提高其电压转换效率。
芯片焊盘7a2位于图36的底部并具有最宽大的面积,在该芯片焊盘7a2上方,布置其上方形成有用于低端开关的功率MOS Q2和SBDD1的半导体芯片5b,并使芯片5b主表面向上。在半导体芯片5b的主表面上方,布置用于功率MOS Q2的源极电极和SBD D1的阳极电极的焊盘BP1以及用于栅极电极的焊盘6BP2。该焊盘BP1经由多个导线WA2电连接到引线7b2,并经由多个导线WB3电连接到焊盘BP7,该焊盘BP7用于半导体芯片5c的驱动电路3b的源极电极。用于栅极电极的焊盘6BP2经由多个导线WB4电连接到焊盘BP8,该焊盘BP8用于半导体芯片5c的驱动电路3b的输出(漏极)电极。半导体芯片5b的背面用作功率MOS Q2的漏极电极和SBD D1的阴极电极,并经由芯片焊盘7a2电连接到多个引线7b3(7b),该多个引线7b3(7b)与芯片焊盘7a2的外围集成。这些引线7b3电连接到输出端子ET5。
其上方形成有用于低端开关的功率MOS Q2的半导体芯片5b,具有如图36所示的矩形形状。其在第一方向X上的边比在第二方向Y上的另一边要长。尽管半导体芯片5b沿半导体芯片5a布置,但它与半导体芯片5a分开,并且它不是布置在芯片焊盘7a2的中心,而是靠近引线7b2布置。具体地说,不是靠近输出端子ET5所连接的引线7b3布置半导体芯片5b,而是靠近在引线7b2附近的芯片焊盘7a2的角(图36的左角)布置,供有参考电位GND的端子ET4连接到该引线7b2。将半导体芯片5b在第二方向Y上的长度调整为大致等于多个引线7b2已经连接到的互连部分7c在第二方向上的长度,同时将半导体芯片5b在第一方向X上的长度调整为大致等于多个引线7b2已经连接到的互连部分7c在第一方向X上的长度。通过这种结构,能缩短用于将用于功率MOS Q2的源极电极和SBD D1的阳极电极的焊盘BP1电连接到引线7b2的导线WA2。半导体芯片5b相交的两边即长边和短边沿多个引线7b2的排列形状(平面L形形状)布置。特别地,用于功率MOS Q2的源极电极和SBD D1的阳极电极的焊盘BP1,具有沿多个引线7b2的排列形状延伸的形状。这使得焊盘BP1和多个引线7b2组可以彼此长距离面对,由此布置多个导线WA2。多个引线7b2沿芯片焊盘7a2的相交成直角的两边排列,并连接到互连部分7c,该互连部分7c呈平面L形形状并沿这两边延伸。通过将所有多个引线7b2连接到互连部分7c,与多个引线7b2的分开排列相比,产生容量的增加,这有利于减小互连电阻和增强参考电位GND。考虑到用于低端开关的功率MOS Q2的源极侧上的导通电阻增加对开关损耗增加的巨大影响,而采用这种结构。通过采用这种结构,能减小功率MOS Q2的源极侧上的导通电阻,并因此能减小功率MOS Q2的传导损耗。另外,能使导线WA2的寄生阻抗均匀,由此能使流到导线WA2的电流均匀。这使得可以提高非绝缘DC-DC转换器1的电压转换效率。此外,能增强参考电位GND,所以能提高非绝缘DC-DC转换器1的操作稳定性。
关于SBD D1,SBD D1的阴极电极能经由具有大面积的芯片焊盘7a2电连接到功率MOS Q1的输出互连或漏极电极,所以能急剧地减小寄生到阴极的电感Lk。另外,通过将功率MOS Q2和SBD D1形成在一个半导体芯片5b上,能减小SBD D1的阳极与功率MOS Q2的源极之间的互连长度,所以能极大地减小寄生在互连上的电感La。换句话说,由于能减小寄生到SBD D1的阳极和阴极的电感La、Lk,SBDD1能够充分呈现其作用,二极管传导损耗和二极管恢复损耗能被减小,并因此能提高非绝缘DC-DC转换器1的电压转换效率。另外,电感La、Lk的减小导致噪声的减小。
将用于低端开关的功率MOS Q2安装在具有最大面积的芯片焊盘7a2上,因为其在操作时的热产生量最大。这使得可以改善由功率MOS Q2产生的热的辐射,由此提高非绝缘DC-DC转换器1的操作稳定性。
上述导线WA2、WB3和WB4例如由金(Au)制成,并且导线WA2比导线WB3和WB4粗。通过使用粗导线WA2作为电连接到功率MOS Q2的源极和SBD D1的阳极的导线,能减小功率MOS Q2的源极侧和SBDD1的阳极侧上的互连电阻。这带来功率MOS Q2导通电阻的减小和二极管损耗的减小,所以能提高非绝缘DC-DC转换器1的电压转换效率。
芯片焊盘7a3位于图36的右上且具有最小的面积,在该芯片焊盘7a3上方,布置其上方形成有驱动电路3a和3b的半导体芯片5c,并使芯片5c主表面向上。在半导体芯片5c的主表面上方,布置用于驱动电路3a和3b的信号输入(栅极)电极的焊盘BP10和用于源极电极的焊盘BP11,以及上述焊盘BP3,BP4,BP7和BP8。用于栅极电极的焊盘BP10经由多个导线WB5电连接到引线7b4(7b)。用于源极电极的焊盘BP11经由多个导线WB6电连接到引线7b5(7b),该引线7b5(7b)与芯片焊盘7a3集成。
其上方形成有驱动电路3a和3b的半导体芯片5c也是平面矩形形状,并且要与功率MOS Q1和Q2连接的焊盘BP3、BP4、BP7和BP8,分别沿邻近半导体芯片5a和5b的两个边布置。这使得可以进一步减小导线WB1,WB2,WB3和WB4每一个的长度,由此使出现在互连通路上的寄生电感LgH,LsH,LgL和LsL进一步地减小。如上所述,为了减小半导体芯片5a中的开关电阻,而不是导通电阻,将半导体芯片5c和半导体芯片5a之间的距离调整为比半导体芯片5c和半导体芯片5b之间的距离短;以及另外,使分别电连接到功率MOS Q1的源极和栅极的导线WB1和WB2,比分别电连接到功率MOS Q2的源极和栅极的导线WB3和WB4短。
半导体芯片5a至5c因特性不同而在外部尺寸(面积)上不同。半导体芯片5a具有比半导体芯片5c大的外部尺寸,同时半导体芯片5b具有比半导体芯片5a大的外部尺寸。其上方形成有驱动电路3a和3b的半导体芯片5c,是用于控制功率MOS Q1和Q2的栅极的控制电路,所以考虑到整个封装的大小,优选元件的外部尺寸尽可能地小。另一方面,优选出现在晶体管中的导通电阻尽可能地小,因为电流I1和I2经过功率MOS Q1和Q2。导通电阻的减小能通过加宽每单位晶体管单元面积的沟道宽度来实现。因此半导体芯片5a和5b具有比半导体芯片5c大的外部尺寸。如图3所示,用于低端开关的功率MOS Q2的导通时间比用于高端开关的功率MOS Q1的导通时间长,所以必须使功率MOS Q2的导通电阻小于功率MOS Q1的导通电阻。因此半导体芯片5b具有比半导体芯片5a大的外部尺寸。
导线WA1,WA2和WB1至WB6例如通过超声波热压键合来连接。当超声波能量不能平稳地传递到芯片焊盘7a1至7a3及引线7b的导线键合部分时,存在键合失败的危险。因此在避开半蚀刻区域的同时执行导线键合。这使得可以减少或防止键合失败。
使用细导线作为要连接到半导体芯片5c的导线WB1至WB6,因为当使用粗导线时,焊盘BP3、BP4、BP7、BP8、BP10和BP11每一个的面积不可避免地会增加。这就增加了芯片尺寸以及生产成本。
图39是半导体芯片5a的放大平面图,图40是沿图39的X5-X5线所取的横截面图,图41是半导体芯片5a的局部横截面图,以及图42是沿图39的Y4-Y4线所取的横截面图。
半导体芯片5a具有半导体衬底5HS、在这个半导体衬底5HS的主表面(其上形成焊盘BP2和6BP1的表面侧)上方所形成的多个单位晶体管元件、通过在半导体衬底5HS主表面上方相继层叠绝缘层9b及栅极指6c和6d而得到的多层互连层、以及为覆盖这些栅极指6c和6d而形成的表面保护膜(最终保护膜)18。半导体衬底5HS例如由n+型硅(Si)单晶制成。绝缘层9b例如由氧化硅膜制成。焊盘BP2和6BP1以及栅极指6c和6d由诸如铝(Al)的金属材料制成,并且它们在这里构成最上的互连层。表面保护膜18例如是氧化硅膜、氮化硅(Si3N4)膜或在它们的层叠膜上方通过层叠诸如聚酰亚胺膜(PiQ)的有机膜而得到的层叠膜。
半导体芯片5a具有彼此相对的主表面(电路形成表面)5ax和背面(背面电极形成表面)5ay。集成电路及焊盘BP2和6BP1形成在半导体芯片5a的主表面5ax侧上,而电连接到漏极区域DR的背面电极HBE形成在背面5ay上。集成电路主要由在半导体衬底5HS的主表面5ax上方形成的晶体管元件、焊盘BP2及栅极指6c和6d组成。背面电极HBE通过沉积诸如金(Au)的金属而形成,并如上所述连接到芯片焊盘7a2。表面保护膜18具有开口部分19,从该开口部分19露出焊盘BP2和栅极指6c的部分。
在半导体芯片5a的宽度方向(第二方向Y)上,形成两个焊盘BP2用于源极电极。形成这些焊盘BP2,使得它们沿半导体芯片5a的较长方向(第一方向X)延伸,并彼此面对。用于栅极电极的焊盘6BP1布置在半导体芯片5a的一个短边附近。用于栅极电极的焊盘6BP具有平面正方形,且其平面尺寸例如为280μm×280μm。用于栅极电极的焊盘6BP1与栅极指6c和6d集成。栅极指6d是从焊盘6BP1沿半导体芯片5a的较长方向延伸的图形,并布置在上述两个焊盘BP2之间。另一方面,栅极指6c是沿半导体芯片5a的外围延伸并布置成以其围绕两个焊盘BP2。栅极指6c和6d均具有约25μm的宽度。通过这种结构,用于源极电极的焊盘BP2能靠近芯片焊盘7a2并沿一对长边布置。这使得可以缩短用于电连接用于源极电极的焊盘BP2和芯片焊盘7a2的导线WA1,并且此外尽可能多地排列导线WA1,由此减小寄生电感LsH。通过在半导体芯片5a的一个端部(与连接到焊盘6BP1的边相对的端部)与栅极指6c的部分分开地形成栅极指6d,能避免隔开功率MOS Q1的源极区域SR1。换句话说,通过不用隔开地形成源极区域SR1,能减小导通电阻。
在半导体衬底5HS的主表面上方,形成例如由n型硅单晶制成的外延层5HEP。这个外延层5HEP具有n-型半导体区域24n1、该区域24n1上方的p型半导体区域24p1、该区域24p1上方的n+型半导体区域24n2、以及p+型半导体区域24p2,该区域24p2从半导体衬底5HS的主表面延伸,以连接到p型半导体区域24p1。在这样一个半导体衬底5HS上方和外延层5HEP中形成具有沟槽栅极结构的n沟道型垂直功率MOS Q1。
功率MOS Q1具有用作源极区域SR1的n+型半导体区域24n2、用作漏极区域DR1的n-型半导体区域24n1、用作沟道形成区域CH1的p型半导体区域24p1、在沟槽14内壁表面上方形成的栅极绝缘膜15b、以及经由栅极绝缘膜15b埋在沟槽14中的栅极电极8G,该沟槽14在外延层5HEP的厚度方向上制作。栅极电极8G例如由低电阻多晶硅制成。通过采用这种沟槽栅极结构,能实现功率MOS Q1单位面积的小型化和更高的集成度。
每个单元的栅极电极8G经由栅极互连8L在场绝缘膜FLD上方拉出,栅极互连8L与该栅极电极集成,且由多晶硅制成,并经由接触孔11b电连接到栅极指6d。栅极电极8G和栅极互连8L的表面覆盖有表面保护膜18,并且它们与焊盘BP2绝缘。除了用于源极的n+型半导体区域24n2,焊盘BP2还经由p+型半导体区域24p2电连接到用于沟道形成的p型半导体区域24p1。功率MOS Q1操作时的电流I1沿沟槽14的深度方向,在源极区域SR1和漏极区域DR1之间流动(在漂移层的厚度方向流动),并同时沿栅极绝缘膜15的侧表面流动。由于这种垂直功率MOS Q1与相对于半导体衬底主表面在水平方向上形成有沟道的水平型场效应晶体管相比,具有每单位单元面积的较大栅极面积,以及具有栅极电极8G和漏极的漂移层之间的较大接合面积,所以能增加其每单位单元面积的沟道宽度,并且尽管栅—漏寄生电容增加,但还是能降低导通电阻。PWL2是p-型p阱。
因为在实施方式1中已经描述了其上方形成有用于低端开关的功率MOS Q2的半导体芯片5b的元件结构,所以这里省略其描述。但应注意的是,在从用于高端开关的功率MOS Q1切换到用于低端开关的功率MOS Q2时,不可避免电流(穿越性电流)从端子ET1流到端子ET4,这种现象称为“自导通”,为了防止这种现象,要控制用于低端开关的功率MOS Q2的阈值电压比用于高端开关的功率MOS Q1的阈值电压高。通过上述控制,能抑制或阻挡穿越性电流的通路,从而能抑制或防止自导通。
接下来将描述半导体芯片5c,它具有用于控制的驱动电路3a和3b。半导体芯片5c的电路结构与器件横截面的结构类似于参考图5和图6所描述的那些。图43中说明了驱动电路3a的基本结构实施例。驱动电路3b的器件结构基本上类似于驱动电路3a的器件结构,从而省略对驱动电路3b的描述。
驱动电路3a具有形成在n型阱NWL2中的p沟道水平型(相对于半导体衬底SUB的主表面在水平方向上形成有沟道)功率MOS Q3,和形成在p型阱PWL3中的n沟道水平型功率MOS Q4。功率MOS Q3具有源极区域SR3、漏极区域DR3、栅极绝缘膜15p和栅极电极G3。源极区域SR3和漏极区域DR3均具有p-型半导体区域25a和p+型半导体区域25b。功率MOS Q4具有源极区域SR4、漏极区域DR4、栅极绝缘膜15n和栅极电极G4。源极区域SR4和漏极区域DR4均具有n-型半导体区域26a和n+型半导体区域26b。漏极区域DR3和DR4连接到输出端子ET7,并经由输出端子ET7电连接到用于高端开关的功率MOS Q1的栅极。源极区域SR4连接到端子ET8,并经由端子ET8电连接到用于高端开关的功率MOS Q1的源极。
图44是管壳20B的一个安装实施例的平面图,而图45是图44的管壳20B的侧视图。在图44中,透视管壳20B,以便于理解布线衬底30的互连。
布线衬底30例如由印刷电路板制成,并且管壳20B、31和32以及芯片部件33和34安装在其主表面上。管壳31具有形成在其中的控制电路2,而管壳32具有形成在其中的负载电路4。芯片部件33具有形成在其中的线圈L1,而芯片部件34具有形成在其中的电容器C1。管壳31的引线31a经由布线衬底30的互连30a电连接到管壳20B的引线7b(7b4)。管壳20B的引线7b1电连接到布线衬底30的互连30b。管壳20B的输出引线(输出端子)7b3经由布线衬底30的互连(输出互连)30c电连接到芯片部件33的线圈L1的一端。芯片部件33的线圈L1在其另一端经由布线衬底30的互连(输出互连)30d电连接到负载电路4。用于管壳20B的参考电位GND的引线7b2经由布线衬底30的互连30e电连接到多个芯片部件34的电容器C1的一端。芯片部件34的电容器C1在其另一端经由布线衬底30的互连30d电连接到负载电路4。
图46说明了包括根据实施方式1的管壳20B的非绝缘DC-DC转换器1的电路系统结构的一个实施例。在这个电路系统中,多个管壳20B与一个负载电路4并联连接。输出电源电位Vin、参考电位GND和控制电路2均公用于多个管壳20B。当在这种电路系统中,功率MOS Q1和Q2、驱动电路3a和3b、以及SBD D1容纳在各自的管壳中时,整个系统的小尺寸化会受到影响。另一方面,在实施方式1中,功率MOS Q1和Q2、驱动电路3a和3b以及SBD D1(SBD D1和功率MOS Q2形成在一个半导体芯片5b上)容纳在同一管壳20B中,这使得整个系统小尺寸化。
接下来将基于图47的制造流程图,描述根据实施方式1的管壳20B的制造工序。
首先,制备三个半导体晶片以及切割胶带(步骤100a和100b)。这三个半导体晶片均具有多个半导体芯片5a至5c形成在其主表面上。将切割胶带粘合到每个半导体晶片的背面,接着通过切割刀片从每个半导体晶片切割半导体芯片5a至5d(步骤101和102)。
然后,制备引线框和芯片粘合剂(步骤103a和103b)。图48和图49均说明了引线框的7单位面积的局部平面图的一个实施例。图48说明了引线框7的主表面,而图49说明了引线框7的背面。引线框7具有沿图48的水平方向延伸的两个框架部分7f1、在与框架部分7f1成直角的方向上延伸以便成为该两个框架部分7f1之间桥路的框架部分7f2、从框架部分7f1和7f2的内围向单位面积的中心延伸的多个引线7b、与该多个引线7b集成并通过这些引线7b由框架部分7f1和7f2支撑的三个芯片焊盘7a1至7a3、以及L形互连部分7c。在引线7b和芯片焊盘7a1至7a3的背面上的外围处,形成半蚀刻区域HF,该区域HF比其他区域薄。在图49中,给半蚀刻区域HF画上了阴影,以便于这个图的理解。作为芯片粘合剂,采用银(Ag)浆。
在通过芯片粘合剂在引线框7的每个单位区域中,将半导体芯片5a至5c安装在芯片焊盘7a1至7a3的主表面上方之后,通过热处理固化芯片粘合剂,由此如图50的步骤S1中所示,半导体芯片5a至5c被牢固地粘贴到芯片焊盘7a1至7a3上(步骤104和105)。通过按5c、5a和5b这样的顺序安装半导体芯片,还可以提高生产率。
然后,制备两种导线WA1、WA2和WB1至WB6(步骤106a和106b)。导线WA1、WA2和WB1至WB6均由例如金(Au)制成。导线WA1和WA2具有宽约50μm的直径,而导线WB1至WB6具有窄约30μm的直径。通过超声波热压方法键合这两种导线WA1、WA2和WB1至WB6(步骤106)。粗导线WA1和WA2的键合处理所必需的负载大于细导线WB1至WB6的键合处理所必需的负载。当粗导线WA1和WA2在键合细导线WB1至WB6之后键合时,细导线WB1至WB6可能会因粗导线键合时施加的大负载而断开。根据本发明人的研究,这种断开故障往往发生在特别是芯片焊盘7a1至7a3彼此分开时。在实施方式4的导线键合步骤中,细导线WB1至WB6的键合在粗导线WA1和WA2键合之后进行,如图50的步骤S2和S3所示。这使得可以抑制或防止细导线WB1至WB6的断开故障。
然后制备密封树脂和密封胶带(步骤107a和107b)。然后通过传递模塑工序进行树脂密封(模塑)步骤(步骤108)。传递模塑工序是这样的工序,即通过使用装备有盒(pot)、流道、树脂注入口和空腔的模具,将热固性树脂通过流道和树脂注入口从盒注入到空腔中,而形成树脂密封体MB。适于制造QFN型管壳20B的是一对一系统传递模塑工序,其对于每个产品形成区域一个一个地利用树脂密封安装在每个产品形成区域上的半导体芯片,或批量系统传递模塑工序,其在使用具有多个产品形成区域(器件形成区域、产品获得区域)的多片形成引线框的同时,一次密封安装在每个产品形成区域上的多个半导体芯片。在这个实施方式4中,采用一对一系统传递模塑工序。
例如以下列方式执行树脂密封步骤。首先,在将密封胶带设置在用于树脂模塑的下模的表面上方之后,使引线框7位于密封胶带上方,并夹紧树脂模具,从而多个引线7b和芯片焊盘7a1至7a3的部分的背面粘贴到密封胶带上。在该树脂密封步骤之前,将密封胶带粘贴到引线框7的背面上,是因为下列原因。如实施方式4中那样,在一个管壳6中具有多个芯片焊盘7a1至7a3的这种结构,其树脂密封步骤中,树脂往往从如图48所示的形成三个芯片焊盘7a1至7a3边界的缝隙的交叉点Z处泄漏。泄漏的树脂(树脂毛刺)经由该交叉点Z渗入到芯片焊盘7a1至7a3的背面(在将管壳20B安装在布线衬底上时的安装表面),并可能使管壳20B的安装受到影响,引起封装失败。为了避免这种失败,预先粘贴密封胶带。在这个实施方式4中,在密封步骤之前,将密封胶带牢固地粘贴到三个芯片焊盘的背面(包括形成三个芯片焊盘边界的缝隙),以防止如上所述的树脂泄漏,并防止密封树脂从交叉点Z处泄漏到芯片焊盘7a1至7a3的背面。这使得可以防止另外将会由树脂毛刺引起的管壳20B的封装失败。优选地,密封胶带具有提供0.5N或更大的粘性强度的粘合强度,因为在密封步骤中期望密封胶带牢固粘贴到芯片焊盘7a1至7a3。近年来,已经使用具有镍(Ni)/钯(Pd)/金(Au)薄镀层的引线框7。在镀有Pd(钯)的引线框7的情况下,当把管壳20B安装到布线衬底上时可以使用无铅焊料,并因此有利于环境。除了这种效果之外,尽管普遍采用的引线框需要预先把银(Ag)浆涂敷到引线框的导线键合部分上,但也能将导线连接到没有已经涂敷Ag浆材料的上述引线框上。即使镀Pd引线框7由于上述的树脂毛刺,也免不了封装失败的问题。如果树脂毛刺形成,就通过清洗去除。由于为了减少制造步骤的数目,通过在树脂密封步骤之前电镀引线框7来制备镀Pd引线框7,所以当通过清洗剥离该树脂毛刺时,Pd镀膜不可避免地会与树脂毛刺一起被剥离。简而言之,镀Pd引线框7有可能变得不能用。另一方面,在实施方式4中,能使用具有上述优点的镀Pd引线框7,因为防止了树脂毛刺的形成,并因此,在密封步骤之后,强清洗处理是不必要的。
将密封树脂注入到上模(空腔)中,并且用树脂密封半导体芯片5a至5c以及多个导线WA1、WA2和WB1至WB6,以从树脂密封体MB(密封部件)露出芯片焊盘7a1至7a3的部分和多个引线7b的部分,由此形成树脂密封体MB。在这个实施方式4中,在芯片焊盘7a1至7a3和引线7b的背面上的外围处形成半蚀刻区域。通过形成这种半蚀刻区域(阴影区域),能增强芯片焊盘7a1至7a3以及引线7b与树脂密封体MB的粘合力。简而言之,能抑制或防止引线从密封体脱出。特别地,随着对更薄更轻半导体器件的日益增加的需求,引线框变得更细。另外,由于引线7b比其他部分更细,且其端部释放,没有被连接,所以上述树脂密封可能会引起引线部分的变形和剥离。因此,也半蚀刻在引线7b端侧上的背面外围部分,以在引线7b端侧上的背面外围部分处形成台阶差。在半蚀刻之后通过密封步骤,密封树脂渗入并覆盖半蚀刻部分,并保持在引线7b端侧上的外围部分,由此能抑制或防止引线7b的变形或剥离。
在这种树脂密封步骤之后,固化这样注入的密封树脂(树脂固化步骤108)。然后执行标记步骤109,之后将单个产品部分从引线框7分离出来(步骤110)。
(实施方式5)
图51是实施方式5的管壳20C的结构实施例的平面图,图52是沿图51的X6-X6线所取的横截面图,以及图53是沿图51的Y5-Y5线所取的横截面图。在图51中,透视树脂密封体MB,并给芯片焊盘7a1和7a2、引线7b和互连部分7c画上了阴影,以便于这个图的理解。
在实施方式5中,用金属板互连21代替用于电连接焊盘和各自部件的一些互连。具体地说,用于半导体芯片5a的功率MOS Q1的源极电极的焊盘BP2,经由一个金属板互连21电连接到芯片焊盘7a2。半导体芯片5b的功率MOS Q2的焊盘BP1经由一个金属板互连21电连接到引线7b2。这个金属板互连21的结构和连接到另一部件的方法,类似于实施方式1中所述的那些,从而这里省略其描述。金属板互连21还整个覆盖有树脂密封体MB。
根据实施方式5,通过使用金属板互连21代替导线,能进一步减小寄生到互连通路上的电感和阻抗,从而进一步地减小开关损耗和二极管传导损耗。结果,与实施方式4相比,能进一步提高非绝缘DC-DC转换器1的电压转换效率。
另外,SBD D1的阳极电极经由具有大面积的金属板互连21电连接到参考电位GND,从而能急剧地减小阳极侧上的互连电阻和寄生到阳极电极侧上的电感La。因此,与实施方式4相比,SBD D1能够充分呈现其作用,且能减小二极管传导损耗和二极管恢复损耗,由此能进一步提高非绝缘DC-DC转换器1的电压转换效率。另外,电感Lk和La的减小带来噪声的进一步减小。
当只关注寄生到互连通路上的电感时,优选采用金属板互连21来形成导线WB1至WB6,用于电连接驱动电路3a和3b的多个焊盘BP3、BP4、BP7、BP8、BP10和BP11至各自部件。驱动电路3a和3b的多个焊盘BP3、BP4、BP7、BP8、BP10和BP11每一个的开口部分为90μm那么窄,从而当金属板互连21取代导线WB1至WB6时,必须使用具有窄宽度的金属板互连21。即使与使用导线所带来的效果相比,在这种情况下减小寄生电感的效果可能也是不够的。另外,100μm或更窄的金属板互连21不能被容易地制作,且不能像导线那样容易地连接。因此,担心生产成本增加和产量降低。用于驱动电路3a和3b的半导体芯片5c容纳在同一管壳20C中,从而即使使用导线也能充分地减小寄生电感。因此,在这个实施方式5中,驱动电路3a和3b的多个焊盘BP3、BP4、BP7、BP8、BP10和BP11与各自部件之间经由导线WB1至WB6连接。
但是,在连接功率MOS Q1和Q2与驱动电路3a和3b的互连通路中,为了减小寄生到这个互连通路上的电感,将多个导线WB1和WB2并联连接。在这个部分处,可以使用宽200μm的金属板互连21,从而这个金属板互连21能取代导线WB1和WB2。通过经由金属板互连21电连接功率MOS Q1和Q 2与驱动电路3a和3b,能减小寄生电感,并因此,能减小开关损耗。
(实施方式6)
图54和图55是实施方式6的管壳20D的部分的横截面图,该部分对应于沿图51的X6-X6线和Y5-Y5线所取的横截面。管壳20D具有类似于图51所示的内部结构。管壳20D的上表面是与管壳20D的安装表面相对的表面(与布线衬底相对的表面)。
在实施方式6中,如实施方式5中那样,焊盘和部件经由金属板互连21连接。但是金属板互连21的部分从树脂密封体MB露出。金属板互连21布置成覆盖功率MOS Q1和Q2的形成区域,该区域是半导体芯片5a和5b的热产生源。这里,覆盖半导体芯片5a和5b的两个金属板互连21都从管壳20D的上表面露出。作为选择,可以仅露出半导体芯片5b侧上的金属板互连21,在该芯片5b上已经形成用于低端开关的功率MOS Q2,该功率MOS Q2具有相对大的热产生量。通过在管壳20D上方放置散热片,并将其与金属板互连21的露出表面接合,能进一步提高散热特性。
在实施方式6中,金属板互连21被给予散热功能,且用于散热的其他部件是不必要的。因此,根据实施方式6,除了由实施方式4和5得到的效果之外,与其中必须添加散热部件的情况相比,能减少管壳20D的制造步骤的数目,并因此能缩短管壳20D的制造时间。由于部件数目的减少,还能实现半导体器件的成本减小。
(实施方式7)
由于DC-DC转换器的电流和频率增加趋势引起的另一个问题是操作时的热量。特别是,在实施方式1和4至6的描述中,半导体芯片5a和5b容纳在一个管壳中,从而高散热特性变得必要。接下来在实施方式7中,将描述考虑到其散热特性的结构。
图56是根据实施方式7的管壳20的横截面图,其中与实施方式4至6的引线7b相比,引线7b是反接的。在这个结构中,芯片焊盘7a1和7a2的背侧表面(与其上安装半导体芯片5a和5b的表面相对的表面)从管壳20E的上表面露出,以及引线7b的背面(要与布线衬底的端子接合的表面)从管壳20E的安装表面露出。
图57是说明图56的管壳20E安装在布线衬底30上的一个实施例的横截面图。管壳20E的背面(安装表面)上的引线7b经由诸如铅/锡焊料的粘合剂38键合到布线衬底30的端子上。散热片(热沉)40经由绝缘板39键合到管壳20E的上表面即芯片焊盘7a1和7a2的背面,该绝缘板39具有高热导率,例如硅酮橡胶。在这种结构中,由半导体芯片5a和5b产生的热量,经由芯片焊盘7a1和7a2,从半导体芯片5a和5b的背面传递到散热片40,然后释放。即使对于非绝缘DC-DC转换器1的电流增加和频率增加,在一个管壳20E中具有两个半导体芯片5a和5b的这种结构中,也是可以获得高散热特性的。这里给定空气制冷的热沉作为一个实施例,但是可以使用液体制冷的热沉来代替,该液体制冷的热沉具有流动通道,能够将冷却的流水注入散热器。
(实施方式8)
在实施方式1至7中,SBD和MOS形成在一个半导体芯片的各自的区域中。但是,在这种结构中,MOS的形成区域不是布置在SBD的形成区域中,并且在具有预定尺寸的半导体芯片中,MOS的面积与SBD的面积成反比地变小,这增加了MOS的传导损耗。
在实施方式8中,如图58所示,SBD D1形成在功率MOS Q2的单位晶体管的形成区域LQR(有源区域)中。在功率MOS Q2的单位晶体管中,将最初形成以连接焊盘BP1和p型半导体区域12的沟槽16加深,以从主表面穿过沟道层(p型半导体区域12),并使沟槽16中的阻挡金属层10a与沟槽16底部上的n-型外延层5LEP相接触,由此形成肖特基连接。在焊盘BP1和p型半导体区域12之间,在沟槽16的侧表面上形成欧姆连接。
通过采用这种结构,SBD D1的专有区域在半导体芯片5b中变得不再必要,由此不用减小半导体芯片5b主表面内的功率MOS Q2形成区域的面积,就能形成具有大面积的SBD。图59表示实施方式8的损耗分析的计算结果。在这个结构中,将功率MOS Q2的寄生二极管(体二极管)Dp和SBD D1作为一个来对待,因为它们在计算时不能区分开,但是图表表明传导损耗和驱动损耗没有发生变化,而体二极管的损耗极大地减小。当SBD D1形成在不同于MOS区域的区域中时损耗减小效果约为0.2W,而通过实施方式8中的结构,能达到约0.55W的损耗减小。
然而,本发明人已经发现仅通过简单加深沟槽16所发生的下述两个问题。
第一个问题是阻挡金属层10a和p型半导体区域12之间的不充分连接。具体地说,p型半导体区域12通常具有不大于1017/cm3的杂质浓度,这对于形成欧姆接触是不够的。因此在焊盘BP1和p型半导体区域12之间不可能形成良好连接。
第二个问题是在肖特基结处大的泄漏电流,因为n-型外延层5LEP具有高的杂质浓度。在实施方式8的结构中,功率MOS Q2和SBD D1形成在同一区域中,从而不可能如实施方式1至7那样,仅在功率MOS Q2的形成区域中形成深的n阱,或通过使用低浓度n-型外延层在SBD D1的形成区域中形成肖特基连接。当肖特基结形成在具有杂质浓度不大于1016/cm3的n-型外延层中时,由于泄漏电流引起的损耗因SBD过大的泄漏电流而增加。
以克服第一个问题为目的,在实施方式8中,如图58中所示,p+型半导体区域(第六半导体层)41形成在p型半导体区域12中,以便使其与沟槽16的侧表面相接触,并在沟槽16的侧表面上,使阻挡金属层10a与p+型半导体区域41形成欧姆接触。这使得能够形成焊盘BP1和p型半导体区域12之间的良好连接。形成p+型半导体区域41,使其不到达沟道(即,沟槽14的侧表面)。当p+型半导体区域41到达沟道时,反型层的形成变得困难,这不可避免地增加了阈值电压Vt。如在实施方式8中,通过形成该层使其不到达沟道,能克服上述问题。
以克服第二个问题为目的,在实施方式8中,通过在与阻挡金属层10a相接触的沟槽(第二沟槽)16底侧上的一个区域中,形成n--型半导体区域(第五半导体层)42,局部地降低肖特基结处n-型外延层5LEP的杂质浓度。换句话说,通过n--型半导体区域42,在肖特基结处形成具有电阻高于n-型外延层5LEP的电阻的区域。这使得可以不用增加导通电阻而降低SBD D1的泄漏电流。
在这种情况下,SBD D1可以形成在,如图11所示的半导体芯片5b的功率MOS Q2的各单位晶体管单元形成区域LQR中,两个邻近的条形栅极电极8之间的每行中。它可以交替或每隔几行形成。焊盘BP1、6BP1,栅极指6a和6b,栅极电极8G和栅极互连8L的平面布局类似于参照图9至图11和图25至图28所述的那些。
基于图60的流程图,参照图61至图66,将描述根据实施方式8的半导体芯片5b的制造方法的一个实施例。为了比较,图67说明了由本发明人研究的具有SBD和MOS的半导体芯片的制造方法的一个实施例。
如图61所示,制备由n+型硅单晶制成的半导体晶片(平面盘形的半导体衬底5LS),以及在其主表面上方,通过外延工序(步骤200)形成具有例如2×1016/cm3的杂质浓度的n-型外延层5LEP。在本发明人所研究的图67的步骤300中,外延层的杂质浓度约为5×1015/cm3那么低,而在实施方式8的方法中,不必为了在功率MOSQ2的单位晶体管单元形成区域内形成SBD D1,而降低外延层5LEP的杂质浓度。
通过离子注入和随后对其进行热扩散处理,在半导体晶片的外延层5LEP中形成上述p阱PWL1(步骤201)。在本发明人所研究的图67的半导体芯片中,为了减小功率MOS Q2的导通电阻,在p阱PWL1的形成步骤201之前,在外延层5LEP中形成深的n阱NWL1(步骤300)。另一方面,在实施方式8中,深的n阱并不是必需的,因为不需要降低外延层5LEP的杂质浓度,由此能省略形成步骤300。这使得可以缩短半导体芯片5b的制造时间,以及提高生产量。
在形成到达半导体晶片主表面上的外延层5LEP的沟槽14(步骤202)之后,使在半导体晶片主表面上的外延层5LEP的表面氧化,以在外延层5LEP的表面上,包括沟槽14的内部,形成栅极绝缘膜15(步骤203)。然后将低电阻多晶硅膜沉积在半导体晶片主表面上方,并且同时填入沟槽14中。通过利用蚀刻构图多晶硅膜,在沟槽14中形成栅极电极8G,以及形成栅极互连8L(步骤204)。
在半导体晶片的主表面中,离子注入诸如硼的p型杂质,接着进行热扩散,由此形成p型半导体区域12(步骤205)。在半导体晶片的主表面中,离子注入诸如磷(P)或砷(As)的n型杂质,接着进行热扩散,由此将n+型半导体区域13形成在栅极电极8G之间的p型半导体区域12上方(步骤206)。
在半导体主表面上方沉积绝缘层9a之后,在该绝缘层9a中形成开口部分9a1。如图62所示,利用绝缘层9a作为离子注入掩模,将诸如硼的p型杂质离子注入到p型半导体区域12中,接着进行杂质的热扩散处理,由此如图63所示,在半导体晶片的p型半导体区域12中形成二维平面上(two-dimensionally)宽于开口部分9a1的p+型半导体区域41(步骤207)。优选在低温下进行短时间的该热扩散处理,从而p+型半导体区域41不到达沟道侧(沟槽14的侧表面)。
利用绝缘层9a作为蚀刻掩模,蚀刻从中露出的硅部分(即顺次蚀刻n+型半导体区域13、p型单导体区域12、p+型半导体区域41、p型半导体区域12和n-型外延层5LEP的上面部分),由此如图64所示,形成沟槽16(步骤208),该沟槽16穿过p型半导体区域12,并到达位于区域12下方的n-型外延层5LEP。从沟槽16的侧表面露出p+型半导体区域41。
如图65所示,利用绝缘层9a作为离子注入掩模,将p型杂质离子注入到沟槽16的底部中,以局部地降低在沟槽16底部上的n-型外延层5LEP的n型杂质的浓度。然后,通过热扩散处理,在沟槽16的底部区域上形成n--型半导体区域42(步骤209)。在该实施方式8中,已经形成p+型半导体区域41,从而图67的p+注入扩散步骤不是必需的。
如图66所示,蚀刻绝缘层9a,以加宽开口部分9a1的开口宽度。这个阶段的开口部分9a1是上述的接触孔11c,从该孔11c底部露出n+型半导体区域13。然后,如图58所示,逐次沉积阻挡金属层10a和金属层10b(步骤210和211),以及通过利用蚀刻对它们进行构图,形成焊盘BP1和6BP以及栅极指6a和6b。然后在半导体晶片的背面上方沉积金(Au),以形成背面电极LBE(步骤212)。在常规采用的步骤之后,将半导体晶片切割成单个的半导体芯片。
基于一些实施方式,对本发明人所做出的发明进行了描述。然而,应认识到本发明并不限于此。不必说,在不脱离本发明主旨的范围下,可以对本发明进行修改。
例如,在上述实施方式中给定扁平封装结构作为封装结构的实施例。但是封装结构并不限于此,例如,还可以采用BGA(球栅阵列)封装结构。
在上述描述中,将本发明人所做出的本发明应用于用来驱动CPU或DSP的电源电路中,这是本发明背景的应用领域。但它能应用于各种领域,而不用限于例如用于驱动另一电路的电源电路的上述领域。
本发明能应用于半导体器件的制造。

Claims (18)

1.一种半导体器件,包括:
半导体芯片,该半导体芯片具有场效应晶体管和与该场效应晶体管并联连接的肖特基势垒二极管,
其中,在所述半导体芯片中,布置构成所述场效应晶体管的多个晶体管单元形成区域,以在其间插入所述肖特基势垒二极管的形成区域;以及
其中,在所述半导体芯片的主表面上方,安排第一金属栅极互连和多个第二金属栅极互连,该第一金属栅极互连沿所述半导体芯片的外围延伸,该多个第二金属栅极互连从所述第一金属栅极互连朝向所述肖特基势垒二极管形成区域,在所述多个晶体管单元形成区域上方延伸,以便在所述多个第二金属栅极互连之间插入所述肖特基势垒二极管形成区域。
2.根据权利要求1所述的半导体器件,
其中,所述肖特基势垒二极管的阳极电连接到的端子布置在所述半导体芯片的外部,并且所述肖特基势垒二极管形成区域沿该端子的延伸方向布置。
3.根据权利要求1所述的半导体器件,
其中,所述肖特基势垒二极管形成区域的中心位置与所述半导体芯片的中心位置一致。
4.根据权利要求1所述的半导体器件,
其中,布置所述肖特基势垒二极管形成区域,以在所述半导体芯片的第一方向上从一端侧延伸到另一相对端侧,并布置在与所述第一方向相交的第二方向的中心处。
5.根据权利要求4所述的半导体器件,
其中,所述半导体芯片在所述第一方向的长度比所述半导体芯片在所述第二方向的长度长。
6.根据权利要求1所述的半导体器件,
其中,在所述半导体芯片的所述主表面上方的没有所述第一金属栅极互连、所述第二金属栅极互连和金属栅极端子的区域中,安排所述多个晶体管单元的源极和所述肖特基势垒二极管的阳极要电连接到的金属端子。
7.根据权利要求6所述的半导体器件,
其中,在所述半导体芯片外部设置端子,并且该端子经由键合导线电连接到所述金属端子。
8.一种半导体器件,包括:
半导体芯片,该半导体芯片具有场效应晶体管和与该场效应晶体管并联连接的肖特基势垒二极管,
其中,在所述半导体芯片中,布置构成所述场效应晶体管的多个晶体管单元形成区域,和所述肖特基势垒二极管的形成区域;以及
其中,所述肖特基势垒二极管的所述形成区域的中心位置与所述半导体芯片的中心位置不一致。
9.根据权利要求8所述的半导体器件,
其中,在所述半导体芯片的主表面上方,排列沿所述半导体芯片的外围延伸的第一金属栅极互连、在所述多个晶体管形成区域上方从所述第一金属栅极互连延伸的多个第二金属栅极互连、以及所述第一和第二金属栅极互连及所述半导体芯片外部的栅极端子要电连接到的金属栅极端子,以及
其中,所述肖特基势垒二极管形成区域布置在与布置所述金属栅极端子所沿的一侧相对的一端侧。
10.根据权利要求8所述的半导体器件,
其中,所述肖特基势垒二极管的阳极电连接到的端子布置在所述半导体芯片的外部,以及
其中,所述肖特基势垒二极管形成区域布置在沿其布置所述端子的所述半导体芯片的所述端侧。
11.根据权利要求8所述的半导体器件,
其中,布置所述肖特基势垒二极管形成区域,以在所述半导体芯片的第一方向上从一个端侧向与其相对的另一端侧延伸,并布置到与所述第一方向相交的第二方向上的一个短边。
12.根据权利要求11所述的半导体器件,
其中,所述半导体芯片在所述第一方向的长度比所述半导体芯片在所述第二方向的长度长。
13.根据权利要求8所述的半导体器件,
其中,所述肖特基势垒二极管形成区域布置到所述半导体芯片在所述第一方向的一端侧,并布置成从与所述第一方向相交的所述第二方向的一个端侧向与其相对的另一端侧延伸。
14.根据权利要求13所述的半导体器件,
其中,排列沿所述半导体芯片的外围延伸的第一金属栅极互连、在所述多个晶体管形成区域上方从所述第一金属栅极互连延伸的多个第二金属栅极互连、以及所述第一和第二金属栅极互连及所述半导体芯片外部的栅极端子要电连接到的金属栅极端子,以及
其中,布置所述肖特基势垒二极管形成区域,以使其被所述第一金属栅极互连和所述第二金属栅极互连环绕。
15.根据权利要求8所述的半导体器件,
其中,在所述半导体芯片的主表面上方的没有所述第一金属栅极互连、所述第二金属栅极互连和金属栅极端子的区域中,设置所述多个晶体管单元的源极和所述肖特基势垒二极管的阳极要电连接到的金属端子。
16.根据权利要求15所述的半导体器件,
其中,在所述半导体芯片的外部布置端子,且该端子经由键合导线电连接到所述金属端子。
17.一种半导体器件的制造方法,包括以下步骤:
(a)在半导体衬底的第一导电类型的第一半导体层上方,形成第二半导体层,该第二半导体层是第一导电类型的半导体层,并具有比所述第一半导体层低的第一导电类型杂质浓度;
(b)在所述第二半导体层上方,形成第三半导体层,该第三半导体层具有与所述第一导电类型相反的第二导电类型;
(c)在所述第三半导体层上方,形成具有第一导电类型的第四半导体层;
(d)形成第一沟槽,该第一沟槽从所述半导体衬底的主表面延伸,并到达所述第二半导体层;
(e)在所述第一沟槽中,形成用于构成场效应晶体管的多个晶体管单元的栅极绝缘膜,并且然后形成栅极电极;
(f)形成第二沟槽,该第二沟槽从所述半导体衬底的所述主表面延伸,并到达所述第二半导体层;
(g)在所述第二沟槽底部的所述第二半导体层上方,形成具有第一导电类型杂质浓度低于所述第二半导体层的该浓度的第五半导体层;以及
(h)在所述第二沟槽中形成构成肖特基结的第一金属层,并在所述第一金属层和所述第五半导体层之间的接触部分处形成肖特基势垒二极管。
18.根据权利要求17所述的半导体器件的制造方法,
其中,所述第二沟槽形成步骤包括以下步骤:
在所述半导体衬底的所述主表面上方,形成具有开口部分的掩模图形,该开口部分用于形成所述第二沟槽;
利用所述掩模图形作为杂质引入掩模,将所述第二导电类型的杂质经由所述开口部分引入到所述第三半导体层,接着扩散所述第二导电类型的杂质,以在所述第三半导体层中形成第二导电类型的第六半导体层,该第六半导体层在二维平面上比所述开口部分宽,且具有比所述第三半导体层的杂质浓度高的第二导电类型杂质浓度;以及
利用所述掩模图形作为蚀刻掩模,逐次蚀刻从所述开口部分露出的所述第四半导体层、所述第三半导体层、所述第六半导体层和所述第二半导体层,由此形成所述第二沟槽。
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