TWI591799B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI591799B
TWI591799B TW104142354A TW104142354A TWI591799B TW I591799 B TWI591799 B TW I591799B TW 104142354 A TW104142354 A TW 104142354A TW 104142354 A TW104142354 A TW 104142354A TW I591799 B TWI591799 B TW I591799B
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Taiwan
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region
gate
power mos
semiconductor wafer
pair
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TW104142354A
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English (en)
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TW201611237A (zh
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白石正樹
宇野友彰
松浦伸悌
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瑞薩電子股份有限公司
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Publication of TW201611237A publication Critical patent/TW201611237A/zh
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Description

半導體裝置
本發明係有關半導體裝置及其製造技術，特別有關適用於具有電源電路之半導體裝置及其製造方法之有效技術。
作為電源電路之一例而廣泛使用之DC-DC轉換器係具有高側用之功率MOS‧FET(Metal Oxide Semiconductor Field Effect Transistor：金屬氧化半導體場效電晶體)，及低側用之功率MOS‧FET串聯地連接之構成。高側用之功率MOS‧FET具有DC-DC轉換器之控制用之開關機能，低側用之功率MOS‧FET具有同步整流用之開關機能，藉由此等2種功率MOS‧FET一面取得同步，一面交互地開啟/關閉，以便進行電源電壓之轉換。
然而，用於桌上型個人電腦、伺服器及遊戲機等之電源電路之非絕緣型DC-DC轉換器，其伴隨驅動之CPU(中央處理單元)等之電流增大化或如抗流線圈及輸入‧輸出電容等被動零件之小型化要求，係傾向電流增大化及高頻化。然而，若電流增大及高頻化進展，會增大高側用之功率MOS‧FET及低側用之功率MOS‧FET一起在關閉期間(空檔期間)中，寄生於低側用之功率MOS‧FET之本體二極體(Body Diode)之導通損失及恢復損失。因此，所採取之手法係將蕭特基障壁二極體(Schottky Barrier Diode：以下簡稱為SBD)並聯地連接於低側用之功率MOS‧FET，於空檔期間中，不將電流流入本體二極體，而 是流入SBD，以減低二極體之導通損失及恢復損失。
關於DC-DC轉換器，於例如：特開平10-150140號公報有記載揭示，於個別之半導體晶片形成MOS‧FET，及並聯地連接於該MOS‧FET之SBD，將該個別之半導體晶片內包於同一封裝之構成(參考專利文獻1)。
又，於例如：特開2003-124436號公報揭示，將形成有構成DC-DC轉換器之高側之功率MOS‧FET之半導體晶片，及形成有低側之功率MOS‧FET和並聯地連接於其之SBD之半導體晶片，內包於同一封裝內之構成(參考專利文獻2)。
並且，於例如：特開平9-102602號公報揭示，於形成有低側之MOS‧FET及並聯地連接於其之SBD之半導體晶片，將SBD形成於低側之MOS‧FET之有效格內之構成(參考專利文獻3)。
[專利文獻1]特開平10-150140號公報
[專利文獻2]特開2003-124436號公報
[專利文獻3]特開平9-102602號公報
然而，於將低側之功率MOS‧FET及SBD形成於個別之半導體晶片之上述專利文獻1之技術，由於連接低側之功率MOS‧FET與SBD之布線之電感影響，空檔時間中往SBD之轉流變小，結果存在有即使連接至順向電壓比本體二極體低之SBD，在減低二極體之導通損失或恢復損失上，仍無法獲得充分效果之問題。
又，現狀是低側之功率MOS‧FET之閘極電阻未如高側之功率MOS‧FET之閘極電阻受到重視，但本發明者首度發現，如上述伴隨電流增大及高頻化，若低側之功率MOS‧FET之閘極電阻為某值以上，將具有自開啟現象將突然變得顯著，損失顯著增大的問題。自開啟現象係於關閉低側之功率MOS‧FET，開啟高側用之功率MOS‧ FET時，連結低側之功率MOS‧FET與高側之功率MOS‧FET之布線之電位上升，因應低側之功率MOS‧FET之汲極‧閘極間之電容與源極‧閘極間之電容之比，低側之功率MOS‧FET之閘極電壓上升，結果有違意圖，低側之功率MOS‧FET開啟之誤動作。因此，若根據本發明者等之檢討，為了降低低側之功率MOS‧FET之閘極電阻，宜於半導體晶片主面之有效區域，亦延伸配置複數金屬布線(閘極指叉)。於上述專利文獻2係揭示有關在同一半導體晶片，形成低側之功率MOS‧FET及並聯地連接於其之SBD，但並未揭示任何有關伴隨電流增大及高頻化而頻繁發生之自開啟現象、及起因於其之損失增大之問題、或其對策之閘極指叉之構成、進而SBD區域、功率MOS‧FET區域及閘極指叉之較佳配置。
並且，於上述專利文獻3係揭示，將SBD形成於低側之MOS‧FET之有效格內，但未揭示任何有關低側之MOS‧FET之通道層與蕭特基金屬之歐姆接觸，因此未記載任何有關該歐姆接觸之形成手段。又，亦未揭示任何有關SBD之蕭特基接觸部之漏洩電流增大的問題，因此亦未記載任何有關該漏洩電流之減低手段。
本發明之目的係在於提供一種提升半導體裝置之電源電壓轉換效率之技術。
本發明之前述以及其他目的和新特徵，應可從本說明書之記述及附圖闡明。
於本申請案所揭示之發明中，簡單說明代表者之概要如下。
亦即，本發明之半導體晶片係具有場效電晶體及SBD；形成前述場效電晶體之複數電晶體格之形成區域係以夾著前述SBD之配置區域之方式配置，且與前述複數電晶體格之各個閘極電極電性連接之複數金屬閘極布線，係以夾著前述SBD之配置區域之方式，配置於前述複 數電晶體格之形成區域。
又，本發明係具備：第一電位供給用之第一電源端子；第二電位供給用之第二電源端子，其係比前述第一電位低者；控制電路，其係與此等第一、第二場效電晶體之輸入電性連接，控制該第一、第二場效電晶體之動作者；輸出布線部，其係連接於連結前述第一、第二場效電晶體之布線者；及SBD，其係於前述輸出布線部與前述第二電源端子之間，並聯地連接於前述第二場效電晶體者；前述第二場效電晶體及前述SBD係形成於同一半導體晶片；於前述半導體晶片，形成前述第二場效電晶體之複數電晶體格之形成區域係以夾著前述SBD之配置區域之方式配置，且與前述複數電晶體格之各個之閘極電極電性地連接之複數金屬閘極布線，係以夾著前述SBD之配置區域之方式，形成於前述複數電晶體格之形成區域。
又，本發明係具備：第一電位供給用之第一電源端子；第二電位供給用之第二電源端子，其係比前述第一電位低者；第一、第二場效電晶體，其係於前述第一、第二電源端子間串聯地連接者；控制電路，其係與此等第一、第二場效電晶體之輸入電性連接，控制該第一、第二場效電晶體之動作者；輸出布線部，其係連接於連結前述第一、第二場效電晶體之布線者；及SBD，其係於前述輸出布線部與前述第二電源端子之間，並聯地連接於前述第二場效電晶體者；前述第一場效電晶體形成於第一半導體晶片，前述第二場效電晶體及前述SBD係形成於同一之第二半導體晶片，前述控制電路形成於第三半導體晶片；於前述第二半導體晶片，形成前述第二場效電晶體之複數電晶體格之形成區域係以夾著前述SBD之配置區域之方式配置，且與前述複數電晶體格之各個之閘極電極電性地連接之複數金屬閘極布線，係以夾著前述SBD之配置區域之方式，形成於前述複數電晶體格之形成區域；前述第一、第二及第三半導體晶片係密封於同一密封體。
又，於具有場效電晶體及SBD之半導體晶片，本發明係前述SBD形成於形成前述場效電晶體之複數電晶體格之形成區域；於形成前述SBD之金屬與形成前述半導體晶片之半導體基板之接觸部，形成比前述半導體基板之雜質濃度低之半導體區域。
又，於具有場效電晶體及SBD之半導體晶片，本發明係前述SBD形成於形成前述場效電晶體之複數電晶體格之形成區域；於形成前述SBD之金屬與前述複數電晶體格之各個之通道層之接觸部，形成比前述通道層之雜質濃度高之第一半導體區域；於形成前述SBD之金屬與形成前述半導體晶片之半導體基板之接觸部，形成比前述半導體基板之雜質濃度低之第二半導體區域。
將藉由本申請案所揭示之發明中之代表者所獲得之效果，簡單說明如以下。
亦即，由於可於具有前述場效電晶體及前述金屬閘極布線之半導體晶片內，良好地形成前述SBD，故可減低連接前述場效電晶體及前述SBD之布線之電感，因此可提升半導體裝置之電源電壓之轉換效率。
1‧‧‧非絕緣型DC-DC轉換器
2‧‧‧控制電路
3a‧‧‧驅動器電路(第一控制電路)
3b‧‧‧驅動器電路(第二控制電路)
4‧‧‧負載電路
5a‧‧‧半導體晶片(第一半導體晶片)
5b‧‧‧半導體晶片(第二半導體晶片)
5c‧‧‧半導體晶片(第三半導體晶片)
5d‧‧‧半導體晶片(第四半導體晶片)
5LS‧‧‧半導體基板
5LEP‧‧‧磊晶層
6a‧‧‧閘極指叉(第一金屬閘極布線)
6b‧‧‧閘極指叉(第二金屬閘極布線)
6c,6d‧‧‧閘極指叉
6BP,6BP1,6BP2‧‧‧接合墊(金屬閘極端子)
7E‧‧‧外部電極
7‧‧‧引線架
7a1‧‧‧晶片墊(第一晶片搭載部)
7a2‧‧‧晶片墊(第二晶片搭載部)
7a3‧‧‧晶片墊(第三晶片搭載部)
7a4‧‧‧晶片墊(第四晶片搭載部)
7b,7b1~7b7‧‧‧引線
7c‧‧‧布線部
7f1,7f2‧‧‧框體部
8‧‧‧閘極圖案
8G‧‧‧閘極電極
8L‧‧‧閘極布線
9a,9b‧‧‧絕緣層
10a‧‧‧障壁金屬層
10b‧‧‧金屬層
12‧‧‧p型半導體區域
13‧‧‧n+型半導體區域
14‧‧‧溝
15,15b,15n,15p‧‧‧閘極絕緣膜
16‧‧‧溝
17‧‧‧p+型半導體區域
18‧‧‧表面保護膜
19‧‧‧開口部
20A~20E‧‧‧封裝
21‧‧‧金屬板布線
22‧‧‧凸塊電極
24n1‧‧‧n-型半導體區域
24p1‧‧‧p型半導體區域
24n2‧‧‧n+型半導體區域
24p2‧‧‧p+型半導體區域
25a‧‧‧p-型半導體區域
25b‧‧‧p+型半導體區域
26a‧‧‧n-型半導體區域
26b‧‧‧n+型半導體區域
30‧‧‧布線基板
30a~30e‧‧‧布線
31,32‧‧‧封裝
33,34‧‧‧晶片零件
38‧‧‧黏著材料
39‧‧‧絕緣片
40‧‧‧散熱片
41‧‧‧p+型半導體區域(第六半導體層)
42‧‧‧n--型半導體區域(第五半導體層)
50A‧‧‧非絕緣型DC-DC轉換器
Q1‧‧‧功率MOS‧FET(第一場效電晶體)
Q2‧‧‧功率MOS‧FET(第二場效電晶體)
Q3‧‧‧功率MOS‧FET
Q4‧‧‧功率MOS‧FET
D1‧‧‧蕭特基障壁二極體
Dp‧‧‧寄生二極體
L1‧‧‧線圈
C1‧‧‧電容器
N1‧‧‧輸出節點(輸出端子)
Vin‧‧‧輸入用電源電位
GND‧‧‧基準電位
G‧‧‧閘極
S‧‧‧源極
D‧‧‧汲極
IN1‧‧‧輸入信號
OUT1‧‧‧輸出信號
ET1‧‧‧端子(第一電源端子)
ET2,ET3‧‧‧端子
ET4‧‧‧端子(第二電源端子)
ET5‧‧‧端子
ET6‧‧‧端子
ET7‧‧‧端子
ET8‧‧‧端子
I1,I2‧‧‧電流
UVL‧‧‧保護電路
SUB‧‧‧半導體基板
NISO‧‧‧n型半導體區域
PW‧‧‧p型半導體區域
CHN‧‧‧n型半導體區域
CHP‧‧‧p型半導體區域
PR1‧‧‧p+型半導體區域
NR1‧‧‧n+型半導體區域
G1,G2,G3,G4‧‧‧閘極電極
SR1,SR2,SR3‧‧‧源極領域
DR1,DR2,DR3‧‧‧汲極領域
MB‧‧‧樹脂密封體
BP1~BP4,BP7~BP11‧‧‧接合墊
WA1,WA2‧‧‧接合金屬線
WB1~WB6‧‧‧接合金屬線
FLD‧‧‧場絕緣膜
PWL1,PWL2,PWL3‧‧‧p井
NWL1,NWL2‧‧‧n井
SDR‧‧‧蕭特基障壁二極體之形成區域
LQR‧‧‧低端低側用之功率MOS‧FET之形成區域
圖1係表示本發明之實施型態之半導體裝置之一例之電路圖。
圖2為圖1之半導體裝置之控制電路之一例之電路圖。
圖3為圖1之半導體裝置之動作時之時序圖之一例之說明圖。
圖4係本發明者所檢討之半導體裝置之半導體晶片構成例之說明圖。
圖5為半導體裝置之電路之說明圖。
圖6係形成有控制用晶片之半導體晶片之寄生動作之說明圖。
圖7係形成有本發明者所檢討之低側開關用之場效電晶體之現狀 之半導體晶片之一例之全體平面圖。
圖8係概略表示圖7之低側開關用之場效電晶體之閘極電阻與損失之依存性之計算結果圖。
圖9係形成有圖1之半導體裝置之低側開關用之場效電晶體及蕭特基障壁二極體之半導體晶片之全體平面圖。
圖10係表示於圖9配置接合金屬線及外部電極之狀態之半導體晶片之全體平面圖。
圖11為圖9之區域A之放大平面圖。
圖12為圖11之Y1-Y1線之剖面圖。
圖13為圖11之Y2-Y2線之剖面圖。
圖14為圖9之蕭特基障壁二極體之要部放大剖面圖。
圖15為圖9之低側開關用之場效電晶體之單位電晶體格之放大剖面圖。
圖16為圖11之X1-X1線之剖面圖。
圖17為圖16之要部放大剖面圖。
圖18係表示空檔時間之期間中之轉流至蕭特基障壁二極體之計算結果之曲線圖。
圖19係表示將蕭特基障壁二極體形成在不同於場效電晶體之半導體晶片之情況，及與場效電晶體形成於同一半導體晶片之情況之損失之計算結果之曲線圖。
圖20係透視本發明之一實施型態之半導體裝置之封裝內部時之封裝主面側之全體平面圖。
圖21為圖20之X2-X2線之剖面圖。
圖22係透視本發明之其他實施型態之半導體裝置之封裝內部時之封裝主面側之全體平面圖。
圖23為圖22之X3-X3線之剖面圖。
圖24係相當於本發明進一步其他實施型態之半導體裝置之圖22之X3-X3線處之剖面圖。
圖25為本發明之其他實施型態之半導體裝置之半導體晶片之全體平面圖。
圖26係表示於圖25配置接合金屬線及外部電極之狀態之半導體晶片之全體平面圖。
圖27為本發明之進一步其他實施型態之半導體裝置之半導體晶片之全體平面圖。
圖28係表示於圖27配置接合金屬線及外部電極之狀態之半導體晶片之全體平面圖。
圖29係寄生於本發明者所檢討之半導體裝置之電感成分之等價電路圖。
圖30為半導體裝置之電路動作之說明圖。
圖31為圖30之電路動作時之元件剖面之說明圖。
圖32為本發明之其他實施型態之半導體裝置之封裝之主面側之全體平面圖。
圖33為圖32之半導體裝置之封裝之側面圖。
圖34為圖32之半導體裝置之封裝之背面側之全體平面圖。
圖35為圖32之半導體裝置之封裝之外觀立體圖。
圖36係透視圖32之半導體裝置之封裝內部時之封裝主面側之全體平面圖。
圖37為圖36之Y3-Y3線之剖面圖。
圖38為圖36之X4-X4線之剖面圖。
圖39係構成圖36之半導體裝置之第一半導體晶片之主面側之全體平面圖。
圖40為圖39之X5-X5線之剖面圖。
圖41為圖39之第一半導體晶片之要部剖面圖。
圖42為圖39之Y4-Y4線之剖面圖。
圖43係構成圖36之半導體裝置之第三半導體晶片之要部剖面圖。
圖44為圖32之半導體裝置之安裝狀態之一例之平面圖。
圖45為圖44之半導體裝置之安裝狀態之側面圖。
圖46係表示包含圖32之半導體裝置之電路系統構成之一例之電路圖。
圖47係表示圖32之半導體裝置之組裝步驟之流程圖。
圖48係在圖32之半導體裝置之組裝步驟所用之引線架之單位區域之主面側之一例之平面圖。
圖49為圖48之引線架之單位區域之背面側之平面圖。
圖50為圖32之半導體裝置之組裝步驟中之引線架之單位區域之平面圖。
圖51係表示本發明之其他實施型態之半導體裝置之構成例之平面圖。
圖52為圖51之X6-X6線之剖面圖。
圖53為圖51之Y5-Y5線之剖面圖。
圖54係相當於本發明之其他實施型態之半導體裝置之圖51之X6-X6線處之剖面圖。
圖55係相當於圖54之半導體裝置之圖51之Y5-Y5線處之剖面圖。
圖56為本發明之其他實施型態之半導體裝置之剖面圖。
圖57係於圖56安裝散熱片之構成之半導體裝置之剖面圖。
圖58為本發明之其他實施型態之半導體裝置之第二半導體晶片之要部剖面圖。
圖59係表示圖58之半導體裝置之損失之計算結果之曲線圖。
圖60為圖58之半導體裝置之第二半導體晶片之製造例之流程圖。
圖61為圖58之第二半導體晶片之製造步驟中之要部剖面圖。
圖62係接續圖61之第二半導體晶片之製造步驟中之要部剖面圖。
圖63係接續圖62之第二半導體晶片之製造步驟中之要部剖面圖。
圖64係接續圖63之第二半導體晶片之製造步驟中之要部剖面圖。
圖65係接續圖64之第二半導體晶片之製造步驟中之要部剖面圖。
圖66係接續圖65之第二半導體晶片之製造步驟中之要部剖面圖。
圖67係本發明者所檢討之第二半導體晶片之製造步驟例之流程圖。
於以下之實施型態，若為了方便而有其必要時，分割成複數區段或實施型態說明，但特別明示之情況除外，其等並非互無關係，處於一方為另一方之一部分或全部之變形例、詳細、補充說明等關係。又，於以下實施型態，提及要素數(包含個數、數值、量、範圍等)之情況，特別明示之情況及原理上明顯限定於特定數之情況等除外，不限定於該特定數，特定數以上或以下均可。並且，於以下實施型態，特別明示之情況及原理上認為明顯為必須之情況等除外，無需贅述，其構成要素(亦包含要素步驟等)未必是必須。同樣地，於以下實施型態，提及構成要素等之形狀、位置關係等時，特別明示之情況及原理上認為明顯不是如其之情況等除外，實質上包含近似或類似該形狀者 等。關於上述數值及範圍，此亦同理。又，於用以說明本實施型態之所有圖式，具有同一機能者係標示同一符號，並省略其重複說明。又，於本實施型態，將代表場效電晶體之MOS‧FET(金屬氧化半導體場效電晶體)，簡稱為MOS。以下根據圖式，詳細說明本發明之實施型態。
(實施型態1)
本實施型態1之半導體裝置係用於例如：桌上型個人電腦、筆記型個人電腦、伺服器或遊戲機等電子機器之電源電路之非絕緣型DC-DC轉換器。圖1係表示該非絕緣型DC-DC轉換器之電路圖之一例。非絕緣型DC-DC轉換器1具有如：控制電路2；驅動器電路(第一、第二控制電路)3a、3b；功率MOS(第一、第二場效電晶體)Q1、Q2；SBD(Schottky Barrier Diode：蕭特基障壁二極體)D1、線圈L1及電容器C1等元件。
控制電路2係為了供給控制例如：脈衝寬調制(Pulse Width Modulation：PWM)電路等之功率MOS Q1、Q2之電壓開啟之寬度(開啟時間)之信號之電路。此控制電路2係有別於功率MOS Q1、Q2而另外封裝。此控制電路2之輸出(控制信號用之端子)係電性連接於驅動器電路3a、3b之輸入。驅動器電路3a、3b之輸出分別電性連接於功率MOS Q1、Q2之閘極。驅動器電路3a、3b係藉由從控制電路2所供給之控制信號，分別控制功率MOS Q1、Q2之閘極之電位，以控制功率MOS Q1、Q2之動作之電路。驅動器電路3a、3b係藉由例如：CMOS反向器電路所形成。於圖2表示驅動器電路3a之電路圖之一例。驅動器電路3a係具有將p通道型之功率MOS Q3與n通道型之功率MOS Q4串連地互補連接之電路構成。根據控制用輸入信號IN1控制驅動器電路3a，經由功率MOS Q1控制輸出信號OUT1之位準。再者，符號G表示閘極，D表示汲極，S表示源極。又，由於驅動器電路3b之動作大致 與驅動器電路3a相同，因此省略說明。
圖1所示之上述功率MOS Q1、Q2係串聯地連接於輸入用電源電位(第一電源電位)Vin供給用之端子(第一電源端子)ET1，與基準電位(第二電源電位)GND供給用之端子(第二電源端子)之間。亦即，功率MOS Q1之其源極‧汲極路徑係設置成，串聯地連接於端子ET1與輸出節點(輸出端子)N1之間；功率MOS Q2之其源極‧汲極路徑係設置成，串聯地連接於輸出結點N1與接地電位GND供給用之端子之間。輸入用電源電位Vin為例如：5~12V程度。又，基準電位GND係比例如：輸入用電源電位低之電源電位，例如：接地電位為0(零)V。又，非絕緣型DC-DC轉換器1之動作頻率(將功率MOS Q1、Q2開啟、關閉時之週期)為例如：1MHz程度。
功率MOS Q1為高側開關(高電位側：第一動作電壓)用之功率電晶體，具有用以對於將電力供給至非絕緣型DC-DC轉換器1之輸出(負載電路4之輸入)之線圈L1，儲存能量之開關機能。此功率MOS Q1係藉由其通道形成於半導體晶片之厚度方向之縱型場效電晶體所形成。若根據本發明者之檢討，於高側開關用之功率MOS Q1，由於附加於其之寄生電容，隨著非絕緣型DC-DC轉換器1之動作頻率變高，開關損失(開啟損失及關閉損失)會看似變高。因此通常，考慮到開關損失，作為高側開關用之場效電晶體，宜適用通道沿著半導體晶片之主面(對於半導體晶片之厚度方向交叉之面)形成之橫型場效電晶體。此理由係由於橫型場效電晶體之閘極電極與汲極區域之重疊面積，比縱型場效電晶體小，因此可減低附加於閘極與汲極間之寄生電容(閘極寄生電容)。然而，若要使橫型場效電晶體之動作時所產生之電阻(開啟電阻)，獲得與縱型場效電晶體相同程度之值，必須使橫型場效電晶體之格面積增大為縱型場效電晶體之格面積之約2.5倍以上，因此不利於元件小型化。相對於此，縱型場效電晶體之情況，相較於橫型 場效電晶體，可增加每單位面積之通道寬，減低開啟電阻。亦即，藉由以縱型場效電晶體形成高側開關用之功率MOS Q1，可實現元件小型化，使封裝小型化。
另一方面，功率MOS Q2為低側開關(低電位側：第二動作電壓)用之功率電晶體，為非絕緣型DC-DC轉換器1之整流用電晶體，具有同步於來自控制電路2之頻率，降低電晶體之電阻而進行整流之機能。與功率MOS Q1相同，此功率MOS Q2係藉由通道形成於半導體晶片之厚度方向之縱型功率MOS所形成。此係根據例如：其次之理由。圖3係表示非絕緣型DC-DC轉換器1之時序圖之一例。Ton為高側開關用之功率MOS Q1之開啟時之脈衝寬，T為脈衝週期。如此圖3所示，低側開關用之功率MOS Q2係其開啟時間(施以電壓之間之時間)，比高側開關用之功率MOS Q1之開啟時間長。因此，於功率MOS Q2，由於開啟電阻所造成之損失看似比開關損失大，因此相較於橫型場效電晶體，適用可增加每單位面積之通道寬之縱型場效電晶體較有利。亦即，藉由以縱型場效電晶體形成低側開關用之功率MOS Q2，可縮小開啟電阻，因此即使流入非絕緣型DC-DC轉換器1之電流增大，仍可提升電壓轉換效率。
於連結圖1之非絕緣型DC-DC轉換器1之功率MOS Q1之源極與功率MOS Q2之汲極之布線間，設有將輸出用電源電位供給至外部之上述輸出節點N1。輸出節點N1係經由輸出布線而與線圈L1電性連接，並且經由輸出布線而與負載電路4電性連接。於連結此輸出節點N1及線圈L1之輸出布線，與基準電位GND供給用之端子之間，上述SBD D1係與功率MOS Q2並聯地電性連接。此SBD D1係順向電壓Vf比功率MOS Q2之寄生二極體Dp低之二極體。SBD D1之陽極係電性連接於基準電位GND供給用之端子，陰極係電性連接於將輸出節點N1與功率MOS Q2之汲極連結之輸出布線。如此，構成上係藉由連接SBD D1，可縮小開啟功率MOS Q2時之空檔時間之電壓下降，可減低二極體之導通損失，而且藉由逆回復時間(trr)之高速化，可減低二極體恢復損失。
於連結上述線圈L1及負載電路4之輸出布線與基準電位GND供給用之端子之間，電性連接有上述電容器C1。負載電路4可例示上述電子機器之CPU(中央處理單元)或DSP(數位信號處理器)等。又，圖1之端子ET2、ET3分別是對於驅動器電路3a、3b之電源電壓供給用端子。
於如此之電路，藉由一面以功率MOS Q1、Q2取得同步，一面交互開啟/關閉，以進行電源電壓之轉換。亦即，高側開關用之功率MOS Q1開啟時，電流(第一電流)I1係從電性連接於功率MOS Q1之汲極之端子ET1，經由功率MOS Q1，流至輸出節點N1，高側開關用之功率MOS Q1關閉時，電流I2藉由線圈L1之逆起電壓而流入。此電流I2流入時，開啟低側開關用之功率MOS Q2，可減少電壓下降。上述電流I1為例如：20A程度之大電流。
然而，圖4係表示在個別之半導體晶片，形成低側之功率MOS Q2與SBD D1之情況之非絕緣型DC-DC轉換器50A之構成之一例。於此非絕緣型DC-DC轉換器50A，高側開關用之功率MOS Q1、低側開關用之功率MOS Q2、驅動器電路3a、3b及蕭特基障壁二極體D1分別形成於個別之半導體晶片5a~5d。然而，於此構成，本發明者發現有以下問題。
第一問題係由於使SBD D1為另外晶片，電性連接SBD D1之陰極與非絕緣型DC-DC轉換器50A之輸出布線之布線路徑，或電性連接SBD D1之陽極與接地用之布線之布線路徑變長，寄生於其等布線之寄生電感Lk、La增大，非絕緣型DC-DC轉換器50A之空檔時間(兩功率MOS Q1、Q2關閉之期間)中之負載電流之轉流被上述寄生電感 Lk、La所妨礙，難以流至SBD D1而流至功率MOS Q2之寄生二極體Dp，結果即使連接順向電流比本體二極體Dp低之SBD D1，在減低二極體導通損失及減低逆回復時間(trr)之高速化所造成之二極體恢復損失上，無法獲得充分效果，具有妨礙SBD D1所造成之電壓轉換效率之提升效果的問題。近年來，於非絕緣型DC-DC轉換器，伴隨負載電路4之驅動電流增大，非絕緣型DC-DC轉換器所需之驅動電流增大，而且從安定供給定電壓之觀點，或使線圈L1及電容器C1小型化(減少元件個數，縮小全體尺寸)之觀點來看，非絕緣型DC-DC轉換器之動作頻率亦變高，因此起因於上述布線之電感Lk、La之問題成為日益顯著的問題。
第二問題係起因於對於上述SBD D1之負載電流之轉流，被布線之寄生電感Lk、La所妨礙，在形成有驅動器電路3a、3b之驅動器晶片(半導體晶片5c)所產生之問題。藉由圖5及圖6說明此問題。圖5係表示包含驅動器電路3a、3b及其輸出段之非絕緣型DC-DC轉換器之電路之說明圖；圖6係表示形成有驅動器電路3a之半導體晶片5c之寄生元件之動作之說明圖。圖5之端子ET4為上述基準電位GND供給用之端子，端子ET5為非絕緣型DC-DC轉換器1之輸出端子。端子ET6(BOOT)係為了控制高側開關用之功率MOS Q1之閘極之自舉電路(Bootstrap Circuit)用之端子，由於功率MOS Q1之源極電位係相對於基準電位GND為較高值(浮起)，因此對於其電壓係從端子ET6供給電壓。符號UVL係於端子ET5及端子ET6之間之電壓未達到某一定基準電壓之情況，判斷為異常狀態，具有自動停止非絕緣型DC-DC轉換器1產生輸出之機能之保護電路。又，符號GH係表示高側開關用之功率MOS Q1之閘極。又，圖6之半導體基板SUB為上述半導體晶片5c之基板部，由例如：p型之矽(Si)單晶所組成。符號NISO表示n型半導體區域，PW表示p型半導體區域(p井)，CHN表示形成有p通道型之功率 MOS Q3之通道之n型半導體區域，CHP表示形成有n通道型之功率MOS Q4之之通道之p型半導體區域，PR1表示p通道型之功率MOS Q3之源極‧汲極用之p+型半導體區域，NR1表示n通道型之功率MOS Q4之源極‧汲極用之n+型半導體區域。
於此構成，兩功率MOS Q1、Q2之空檔時間時，負載電流經由SBD D1而供給。然而於重負載時，如上述，若起因於布線之寄生電感Lk、La，流至SBD D1之負載電流變小，負載電流亦流入低側開關用之功率MOS Q2之寄生二極體(本體二極體)Dp，則非絕緣型DC-DC轉換器50A之輸出側之端子ET5(VSWH)之電位，將往負電位降低寄生二極體Dp之順向電壓Vf分，電性連接於功率MOS Q1之驅動器晶片(控制用IC)之輸出亦成為負電位，結果於半導體晶片5c內，寄生之npn型雙極電晶體Qp會開啟，具有增加驅動器晶片耗電的問題。並且，若從端子ET6(BOOT)所拉走之電荷量變大，端子ET5與端子ET6之間之電位比規定之電位值低，將具有產生誤動作之問題，上述保護電路UVL將自動動作，有違意圖而使功率MOS Q1之動作停止。
第三問題係由於蕭特基障壁二極體D1為另外封裝，系統大型化的問題。特別是於1個負載電路4，電性連接有複數非絕緣型DC-DC轉換器，以建構全體系統之情況，若於個別之非絕緣型DC-DC轉換器，以另外之封裝連接蕭特基障壁二極體D1，將具有妨礙全體系統小型化之問題。
因此如後述，於本實施型態1，於同一半導體晶片內形成功率MOS Q2及SBD D1。藉此，可大幅減低寄生於連接功率MOS Q2與SBD D1之布線之寄生電感Lk、La，因此於空檔時間之期間中，可使電流不流至本體二極體Dp而流至SBD D1。亦即，可充分發揮SBD D1之機能。因此可減低二極體之導通損失及恢復損失，故可提升非絕緣型DC-DC轉換器1之電源電壓之轉換效率。又，可充分發揮SBD D1之 效果，因此在形成有驅動器電路3a、3b之半導體晶片5c內，可抑制或防止開啟寄生之npn型雙極電晶體Qp。並且，由於可抑制從上述圖5所示之端子ET6拉走電荷，因此可抑制或防止端子ET5與端子ET6之間之電位，變得比規定之電位值低。因此，可抑制或防止保護電路UVL之動作所造成之功率MOS Q1之動作停止(誤動作)，故可提升非絕緣型DC-DC轉換器1之動作可靠性。而且，由於SBD D1形成在形成有功率MOS Q2之半導體晶片5b，因此可使系統小型化。
其次，圖7係表示形成有本發明者所檢討之低側開關用之功率MOS Q2之現狀之半導體晶片51之全體平面圖之一例。再者，圖7之X為第一方向，Y為正交於第一方向之第二方向。
於此半導體晶片51之主面上，沿著半導體晶片51之外周形成閘極指叉6a。又，於半導體晶片51之1個角部附近，功率MOS Q2之閘極電極用之大寬度之接合墊(以下僅稱為墊)係6BP係與上述閘極指叉6a一體地形成。於半導體晶片51之主面上之中央，未配置閘極指叉，配置有功率MOS Q2之源極電極及SBD D1之陽極電極用之墊BP50。並且於半導體晶片51之長度方向(第一方向X)中央，上述SBD D1之形成區域SDR係從半導體晶片51之短方向(第二方向Y)之端邊，延伸至相反側之端邊而配置。於此SBD D1之配置區域DR之左右兩側，配置有功率MOS Q2之複數單位電晶體格。
然而，本發明者首度發現，於如此之僅於半導體晶片51之主面外周有閘極指叉6a之構造，無法減低功率MOS Q2之閘極電阻，開關速度變慢。特別是將此構成適用於非絕緣型DC-DC轉換器1之低側之功率MOS Q2之情況，若低側之功率MOS Q2之閘極電阻成為某值以上，將具有自開啟現象將突然變得顯著，損失明顯增大的問題。自開啟現象係於關閉低側之功率MOS Q2，開啟高側用之功率MOS Q1時，連結低側之功率MOS Q2與高側之功率MOS Q1之布線之電位上 升，因應低側之功率MOS Q2之汲極‧閘極間之電容與源極‧閘極間之電容之比，低側之功率MOS Q2之閘極電壓上升，結果有違意圖，低側之功率MOS Q2開啟之誤動作。圖8係表示在例如：輸入用電源電位Vin=12V、輸出電壓Vout=1.3V、輸出電流Iout=25A、動作頻率f=1MHz之條件之低側之功率MOS Q2之閘極電阻與損失之依存性之計算結果之概略。可知於圖8之曲線圖之橫軸電阻(低側之功率MOS Q2之閘極電阻+驅動器電路3b之輸出段之電阻)超過2.4Ω附近，開始引起自開啟現象，損失增大。現狀係由於非絕緣型DC-DC轉換器1之電流小且頻率低，因此自開啟現象所造成之損失增大之影響小，低側之功率MOS Q2之閘極電阻未如高側之功率MOS Q1之閘極電阻受重視，但如上述，伴隨非絕緣型DC-DC轉換器1之電流增大及高頻化，自開啟現象所造成之損失增大將成為問題。
因此，於本實施型態1，為了降低低側之功率MOS Q2之閘極電阻，於半導體晶片5b之主面有效區域，亦配置複數閘極指叉(金屬閘極布線)，藉此可抑制自開啟現象，因此可減低非絕緣型DC-DC轉換器1之損失。又，亦可對應非絕緣型DC-DC轉換器1之大電流及高頻化。
其次，於圖9~圖17表示形成有本實施型態1之低側之功率MOS Q2及SBD D1之半導體晶片5b之具體例。
圖9係表示半導體晶片5b之全體平面圖。再者，圖9雖為平面圖，但為了易於觀看，於閘極指叉6a、6b及墊BP1附加影線。
半導體晶片5b之平面形狀係例如：第一方向X之長度比第二方向Y之長度長之長方形狀。於此半導體晶片5b主面之第二方向Y之中央，上述SBD D1之形成區域SDR係從第一方向X之端邊，延伸至相反側之端邊而配置。於此SBD D1之配置區域SDR之第二方向Y之上下，形成上述功率MOS Q2之複數單位電晶體格群之形成區域係夾著上述 SBD D1之形成區域SDR而配置。若改變看法，半導體晶片5b主面之功率MOS Q2之複數單位電晶體格群之形成區域，係由上述SBD D1之形成區域SDR之配置，上下大致均等地被2分割。
如此，於本實施型態1，藉由在SBD D1之上下兩側配置功率MOS Q2之複數單位電晶體格(特別是以上述SBD D1之形成區域SDR，將半導體晶片5b主面之功率MOS Q2之複數單位電晶體格之形成區域大致均等地2分割)，可使從SBD D1至最遠之功率MOS Q2之單位電晶體格之距離，比使SBD D1之形成區域SDR偏向一方之邊而配置之情況之該距離縮短。而且，於其分割時，藉由不是以圖7所示之長度方向(第一方向X)2分割，而是以短方向(第二方向Y)進行2分割，可使從SBD D1至最遠之功率MOS Q2之單位電晶體格之距離，比圖7之情況之該距離縮短。又，藉由使SBD D1之形成區域SDR，延伸於半導體晶片5b之長度方向(第一方向X)，可使接近SBD D1之功率MOS Q2之單位電晶體數，比圖7之情況之該數目增加。藉此，可遍及半導體晶片5b內之功率MOS Q2之複數單位電晶體格之全體，更有效地發揮SBD D1之機能，因此可減低非絕緣型DC-DC轉換器1之損失。
於此半導體晶片5b之主面，閘極指叉(第一金屬閘極布線)6a及墊(金屬閘極端子)6BP係與圖7相同地配置。在此不同的是，於功率MOS Q2之複數單位電晶體格群之形成區域上，亦配置有複數閘極指叉(第二金屬閘極布線)6b。各閘極指叉6b係與外周之閘極指叉6a一體地形成，並以夾著上述SBD D1之形成區域SDR之方式，從半導體晶片5b之長邊側之閘極指叉6a之複數處延伸至半導體晶片5b之第二方向Y中央之SBD D1之形成區域SDR之位置。如此，藉由將閘極指叉6b亦配置於功率MOS Q2之複數單位電晶體格群之形成區域上，可減低功率MOS Q2之閘極電阻，抑制自開啟現象，因此可減低非絕緣型DC-DC轉換器1之損失，而且亦可對應非絕緣型DC-DC轉換器1之電流增大及 高頻化。而且，本實施型態1之情況係藉由如上述將SBD D1之形成區域SDR，配置於半導體晶片5b之短方向(第二方向Y)之中央，可使閘極指叉6b之長度，比使SBD D1之形成區域SDR偏向一方之邊而配置之情況之該長度縮短。亦即，可將功率MOS Q2之閘極電阻，比使SBD D1之形成區域SDR偏向一方之邊而配置之情況之該電阻減低。而且，由以上理由，藉由在上述位置配置SBD D1之形成區域SDR，可不致妨礙功率MOS Q2之閘極電阻之減低效果，而於形成有功率MOS Q2之半導體晶片5b形成SBD D1。
於半導體晶片5b主面上，在由閘極指叉6a、6b所包圍之區域，墊BP1在平面上形成為梳齒狀。在此係例示墊BP1之齒狀部分形成於上下(第二方向)兩方之情況。此墊BP1成為功率MOS Q2之源極電極及SBD D1之陽極電極之共同電極。閘極指叉6a、6b、墊6BP及墊BP1係將同一金屬藉由蝕刻進行圖案化而形成，但互相絕緣。
其次，圖10係表示半導體晶片5b之全體平面圖，其表示於圖9配置接合金屬線(以下僅稱金屬線)WA及外部電極(端子)7E之狀態。再者，圖10雖為平面圖，但為了易於觀看，於閘極指叉6a、6b及墊BP1附加影線。
在此係例示以沿著半導體晶片5b之一方短邊及長邊之方式，配置平面L字狀之外部電極7E之情況。此外部電極7E係經由複數條金屬線WA，與上述源極及陽極用之墊BP1電性地連接。金屬線WA係由例如：金(Au)所組成之金屬細線。於本實施型態1，藉由如上述將SBD D1配置於半導體晶片5b之短方向(第二方向Y)之中央，可使SBD D1與外部電極7E之距離不會變得太遠。藉此亦不會使SBD D1之陽極側之寄生電感La增加。又，藉由如上述將SBD D1配置於半導體晶片5b之短方向(第二方向Y)之中央，亦可使功率MOS Q2與外部電極7E之距離不會變得太遠。藉此，由於不會使功率MOS Q2之源極側之寄生電感 及阻抗增加，因此亦可抑制在功率MOS Q2之損失增加。又，藉由使SBD D1延伸於半導體晶片5b之長度方向(第一方向X)，可儘可能將金屬線WA相對於SBD D1及功率MOS Q2之條數較多地配置。藉此，可減低SBD D1之陽極及功率MOS Q2之源極之寄生電感和阻抗。由以上可減低非絕緣型DC-DC轉換器1之損失。
其次，圖11表示圖9之區域A之放大平面圖，圖12表示圖11之Y1-Y1線之剖面圖，圖13表示圖11之Y2-Y2線之剖面圖，圖14表示SBD D1之要部放大剖面圖，圖15表示功率MOS Q2之單位電晶體格之放大剖面圖，圖16表示圖11之X1-X1線之剖面圖，圖17表示圖16之要部放大剖面圖。再者，於圖11，為了使圖式容易觀看，將墊BP1除去，並且將閘極指叉6a、6b透明表示，為了使墊BP1及閘極指叉6a、6b下層之閘極圖案8(閘極電極8G及閘極布線8L)容易觀看，於閘極圖案8附加班點狀影線而表示。
半導體晶片5b具有：形成有元件之主面(元件形成面：第一面)，及其相反側之形成有背面電極LBE之背面(背面電極形成面：第二面)。構成此半導體晶片5b之半導體基板(第一半導體層)5LS係由例如：n+型矽單晶所組成，於其上層形成有n-型矽單晶所組成之磊晶層(第二半導體層)5LEP。於此磊晶層5LEP之主面，形成有例如：氧化矽(SiO2等)所組成之場絕緣膜FLD。在此場絕緣膜FLD及其下層之p井PWL1所包圍之活性區域，形成有功率MOS Q2之複數單位電晶體格及SBD D1。於磊晶層5LEP之主面上，經由例如：PSG(Phospho Silicate Glass：磷矽玻璃)等絕緣層9a，形成有上述墊BP1。例如：圖14所示，墊BP1所具有之構成係從下層依序層疊：鈦鎢(TiW)等障壁金屬層10a及例如：鋁(Al)等金屬層10b。於上述SBD D1之形成區域，墊BP1之障壁金屬層10a係經由形成於絕緣層9a之接觸孔洞11a而與磊晶層5LEP之主面相接，於該障壁金屬層10a與磊晶層5LEP之接觸部，形 成上述SBD D1。為了減低SBD D1之漏洩電流，磊晶層5LEP之雜質濃度設為例如：5×1015/cm3程度之稍低濃度。
另一方面，於上述閘極指叉6a、6b及SBD D1之形成區域SDR所包圍之活性區域，配置有上述功率MOS Q2之複數單位電晶體格之形成區域LQR。於此形成區域LQR，形成有例如：溝槽閘極構造之n通道型之縱型功率MOS Q2。藉由製成溝槽閘極構造，可實現功率MOS Q2之單位電晶體格之微細化及高積體化。此單位電晶體格係具有：具有作為汲極區域之機能之半導體基板5LS及n井NWL1；具有作為通道型成區域之機能之p型半導體區域(第三半導體層)12；具有作為源極區域之機能之上述n+型半導體區域(第四半導體層)13；於磊晶層5LEP之厚度方向所挖掘之溝(第一溝)14；於溝14之底面及側面所形成之閘極絕緣膜15；及經由閘極絕緣膜15而埋入於溝14內之閘極電極8G。如上述，由於磊晶層5LEP之雜質濃度設定稍低，因此若直接於磊晶層5LEP形成功率MOS Q2之單位電晶體格，於該單位電晶體格之形成區域LQR之磊晶層5LEP之電阻成分變大，功率MOS Q2之開啟電阻增大。因此，藉由在功率MOS Q2之複數單位電晶體格之形成區域LQR，形成深的n井NWL1，以將磊晶層5LEP之雜質濃度，高濃度化達到例如：2×1016/cm3。藉此可於包含SBD D1及功率MOS Q2雙方之半導體晶片5b，同時達成SBD D1之漏洩電流減低及功率MOS Q2之低開啟電阻。
在此係例示溝14及閘極電極8G配置成條紋狀之情況。亦即，於功率MOS Q2之各單位電晶體群之形成區域，延伸於第一方向X之平面帶狀之複數閘極電極8G係沿著第二方向Y排列複數而配置。溝14及閘極電極8G之平面配置形狀不限於條紋狀，可進行各種變更，作為例如：平面格子狀亦可。溝14之深度為達到n井NWL1之程度。閘極電極8G係由例如：低電阻之多晶矽所組成，經由與此一體形成之多 晶矽所組成之閘極布線8L，拉出於場絕緣膜FLD上。閘極電極8G及閘極布線8L之表面係以上述絕緣層9a所包覆，以謀求墊BP1之絕緣，而閘極布線8L係經由形成在絕緣層9a之接觸孔洞11b，與上述閘極指叉6a、6b電性連接。閘極指叉6a、6b之構成係與上述墊BP1相同。於功率MOS Q2之複數單位電晶體格之形成區域LQR，墊BP1係經由形成在絕緣層9a之接觸孔洞11c，與源極用之n+型半導體區域13電性連接，此外並經由在磊晶層5LEP所挖掘之溝16，與p+型半導體區域17電性連接，經由此，亦與通道形成用之p型半導體區域12電性連接。功率MOS Q2之動作電流係於各單位電晶體格，沿著閘極電極8G之側面(亦即溝14之側面)，往半導體基板5LS之厚度方向而流於n井NWL1與n+型半導體區域13之間。相較於橫型場效電晶體(通道係對於半導體基板之主面形成於水平方向)，如此之縱型功率MOS Q2係每單位電晶體格面積之閘極面積大，而且閘極電極8G與汲極之漂移層之接合面積大，因此閘極-汲極間之寄生電容大，但另一方面，可增大每單位電晶體格面積之通道寬，縮小開啟電阻。
於半導體晶片5b之主面最上層，堆積有表面保護膜18。表面保護膜18係例如：氧化矽膜及氮化矽(Si3N4)膜之疊層膜，或於該疊層膜上層疊有聚醯亞胺膜(PiQ)之有機膜。閘極指叉6a、6b之表面係由表面保護膜18所包覆，但墊BP1、6BP之一部分係經由形成於表面保護膜18之一部分之開口部19而露出。此露出區域為連接有金屬線之接合區域。另一方面，於半導體基板5LS之背面，形成有例如：金(Au)等所組成之上述背面電極LBE。此背面電極LBE為上述功率MOS Q2之汲極電極及上述SBD D1之陰極電極之共同電極。
其次，圖18係將空檔期間中轉流於SBD之電流之計算結果，以在有別於形成有SBD及MOS之半導體晶片之其他半導體晶片形成之情況IA(虛線)，及如本實施型態1之SBD及MOS形成於同一半導體晶片之 情況IB(實線)比較而表示。
SBD之面積為例如：2mm2。MOS與SBD之間之寄生電感在SBD形成於其他半導體晶片之情況，以例如：1nH計算，在SBD形成於同一半導體晶片之情況，以例如：0.1nH計算。以下計算條件均為例如：輸入用電源電位Vin=12V，輸出電壓Vout=1.3V，輸出電流Iout=25A，動作頻率f=1MHz。如圖18所示可知，如本實施型態1將SBD及MOS形成於同一半導體晶片之情況，相較於將SBD形成於其他半導體晶片之情況，於空檔時間之期間中，更多電流轉流入SBD。SBD之順向電壓比寄生二極體(本體二極體)Dp低，電子有助於動作，因此損失小、動作快。因此，多量之電流流入SBD，可減低空檔時間之期間中之導通損失及恢復損失。
其次，圖19係表示將SBD形成在與MOS不同之半導體晶片之情況，及形成在與MOS同一半導體晶片之情況之損失計算結果。相較於沒有SBD，以其他半導體晶片搭載SBD之一方之損失較小，但進一步藉由將SBD形成於同一半導體晶片，由於更多電流轉流入SBD，因此可減低MOS之寄生二極體(本體二極體)之導通損失及恢復損失，結果將SBD及MOS單一晶片化之情況最減低損失。
其次，圖20係表示收容上述半導體晶片5a、5b之封裝20A內之構成例之平面圖，圖21係表示圖20之X2-X2線之剖面圖。再者，於圖20，為了使圖式容易觀看，將樹脂密封體MB取下而表示。
於封裝20A內，2個晶片墊7a1、7a2及配置於其周圍之引線7b(7b1、7b2、7b3、7b6、7b7)係以互相接近之狀態配置。於晶片墊7a1上，形成有上述高側開關用之功率MOS Q1之半導體晶片5a，係以其主面朝上之狀態配置。於此半導體晶片5a主面，配置有功率MOS Q1之源極電極用之墊BP2及閘極電極用之墊6BP1。此源極電極用之墊BP2係經由複數條金屬線WA1，電性連接於與晶片墊7a2一體地形成 之引線7b3。又，上述閘極電極用之墊6BP1係經由金屬線WB2，與引線7b6電性連接。於此引線7b6，輸入有來自上述驅動器電路3a之輸出信號。並且，半導體晶片5a之背面係與功率MOS Q1之汲極連接之汲極電極，經由晶片墊7a1，與一體形成於晶片墊7a1外周之複數引線7b1電性連接。此引線7b1係電性連接於上述端子ET1。再者，金屬線WA1係以鄰接於第一方向X之金屬線WA1，交互連接於上下之墊BP2之方式而交叉配置。
於相對較大之晶片墊7a2上，上述形成有上述低側開關用之功率MOS Q2之半導體晶片5b，係以其主面朝上之狀態配置。此半導體晶片5b之上述墊BP1係經由複數條金屬線WA2，電性連接於引線7b2(7b)，上述墊6BP2係經由金屬線WB3，與引線7b7電性連接。於此引線7b7，輸入有來自上述驅動器電路3b之輸出信號。並且，半導體晶片5b之背面電極LBE係經由晶片墊7a2，與一體形成於晶片墊7a2外周之複數引線7b3(7b)電性連接。此引線7b3係電性連接於輸出用之上述端子ET5。
此2片半導體晶片5a、5b及金屬線WA1、WA2、WB2、WB3係由樹脂密封體MB所密封。如此，藉由將2片半導體晶片5a、5b收容於1個封裝20A內，可減低半導體晶片5a、5b間之寄生電感，減低損失。再者，關於半導體晶片5a之構成或半導體晶片5a、5b之配置等，於後述之實施型態詳細說明。
其次，圖22係表示圖20之變形例之平面圖，圖23係表示圖22之X3-X3線之剖面圖。再者，於圖22，為了易於觀看圖式，將樹脂密封體MB取下而表示。
在此，取代金屬線，墊BP2及引線7b3、墊BP1及引線7b2分別以金屬板布線21所連接。此金屬板布線21係由例如：銅(Cu)或鋁(Al)等金屬所組成，經由凸塊電極22，與墊BP1、BP2或引線7b2、7b3電性 連接。凸塊電極22係由例如：鉛(Pb)/錫(Sn)或金(Au)等金屬所組成。亦可使用導電性樹脂以取代凸塊電極22。金屬板布線22亦其全體藉由樹脂密封體MB所包覆。
如此，藉由使用金屬板布線21，可進一步減低寄生於布線路徑之電感及阻抗，因此可減低開關損失及導通損失，進一步提升非絕緣型DC-DC轉換器1之電壓轉換效率。
又，由於SBD D1之陽極電極係經由大面積之金屬板布線21，電性連接於基準電位GND，因此可大幅降低陽極側之布線電阻及寄生於陽極電極側之電感La。因此，可進一步發揮SBD D1之效果，減低二極體導通損失及二極體恢復損失，故可進一步提升非絕緣型DC-DC轉換器1之電壓轉換效率。又，可減低電感Lk、La，因此亦可進一步減低雜訊。
其次，圖24係表示圖22之變形例之相當於圖22之X3-X3處之剖面圖。
於此，墊BP2及引線7b3、墊BP1及引線7b2分別以金屬板布線21所連接。但該金屬板布線21之一部分係由樹脂密封體MB露出。金屬板布線21配置成包覆特別是半導體晶片5a、5b之熱產生源之功率MOS Q1、Q2之形成區域。在此係例示包覆半導體晶片5a、5b之2個金屬板布線21之雙方，從樹脂密封體MB上面露出之情況，但構成上亦可僅露出形成有發熱量相對高之低側開關用之功率MOS Q2之半導體晶片5b側之金屬板布線21。又，藉由在樹脂密封體MB上面，裝載散熱片，並接合於金屬板布線21之露出面，亦可提高散熱性。若根據圖24之構成，除了上述所說明之效果以外，藉由使金屬板布線21具有散熱機能，由於無須追加散熱用之其他零件，因此相較於追加散熱用零件之情況，可簡化半導體裝置之組裝步驟，縮短半導體裝置之組裝時間。又，可減少零件數，因此可減低半導體裝置之成本。
(實施型態2)
於本實施型態2，說明有關半導體晶片內之SBD之配置位置之變形例。圖25表示半導體晶片5b之全體平面圖，圖26表示半導體晶片5b之全體平面圖，其表示於圖25配置金屬線WA及外部電極7E之狀態。再者，圖25及圖26雖為平面圖，但為了易於觀看圖式，於閘極指叉6a、6b及墊BP1附加影線。
於本實施型態2，SBD D1之形成區域SDR係靠近半導體晶片5b之單側長邊而配置。特別如圖26所示，SBD D1之形成區域SDR配置於接近外部電極7E之長邊側。藉此，可減低SBD D1之陽極側之寄生電感，因此可將更多電流轉流入SBD D1。因此，可比前述實施型態1，更減低二極體之導通損失及恢復損失。前述實施型態1之圖9及圖10所說明之構成，及本實施型態2之構成之何者較有效，係按照實際之使用條件而不同。亦即，在空檔時間之期間中之二極體之導通損失及恢復損失為支配性使用條件時，宜採用如本實施型態2之構成，在MOS之導通損失為支配性條件時，宜採用前述實施型態1之圖9及圖10所說明之構成。因此，按照非絕緣型DC-DC轉換器1之使用條件，區分採用各個構成。
再者，閘極指叉6b係從半導體晶片5b之一方長邊側之閘極指叉6a，延伸至SBD D1之形成區域SDR附近。藉此，SBD D1之形成區域SDR係由閘極指叉6a及閘極指叉6b所夾住，而墊BP1為單側具有齒之梳齒形狀。
(實施型態3)
於本實施型態3，說明有關半導體晶片內之SBD之配置位置之變形例。圖27表示半導體晶片5b之全體平面圖，圖28表示半導體晶片5b之全體平面圖，其表示於圖27配置金屬線WA及外部電極7E之狀態。再者，圖27及圖28雖為平面圖，但為了易於觀看圖式，於閘極指叉 6a、6b及墊BP1附加影線。
於本實施型態3，SBD D1之形成區域SDR係靠近半導體晶片5b之單側短邊而配置。在此，SBD D1之形成區域SDR係沿著半導體晶片5b之短邊(第二方向Y)而延伸。特別如圖28所示，SBD D1之形成區域SDR配置於接近外部電極7E之短邊側。藉此，可減低SBD D1之陽極側之寄生電感，因此可將更多電流轉流入SBD D1。因此，可比前述實施型態1，更減低二極體之導通損失及恢復損失。
又，於本實施型態3，SBD D1之形成區域SDR係對於閘極用之墊6BP之配置位置，配置於相反位置。藉此可互不干擾地配置連接於墊BP1之金屬線WA，及連接於閘極用之墊6BP之金屬線。
又，閘極指叉6b係從半導體晶片5b之一方長邊側之閘極指叉6a，延伸至另一方長邊側之閘極指叉6a附近。藉此，SBD D1之形成區域SDR係成為其四邊由閘極指叉6a、6b所包圍之狀態。在構成上亦可將閘極指叉6b進一步延伸，與一方長邊側之閘極指叉6a及另一方長邊側之閘極指叉6a連接，使各墊BP1及單位電晶體格群孤立。但該情況，在檢查功率MOS Q2之複數單位電晶體格時，必須針對每個以閘極指叉6b所區劃之複數墊BP1，進行單位電晶體格群之檢查。因此於本實施型態3，不以閘極指叉6a將墊BP1完全切斷，而是作為1個墊BP1而構成。藉此，可一次完成功率MOS Q2之複數單位電晶體格之檢查。
(實施型態4)
前述實施型態1係說明有關將低側之功率MOS與SBD形成於同一半導體晶片之構成。但於圖4之非絕緣型DC-DC轉換器50A，若將各半導體晶片5a~5d收容於個別之封裝而構成，將具有以下課題，使低側之功率MOS及SBD單一晶片化之效果會減低。於本實施型態4，說明用以解決此之構成例。
首先，說明有關課題。亦即，於前述圖4，由於將高側開關用之 功率MOS Q1、低側開關用之功率MOS Q2、驅動器電路3a、3b及蕭特基障壁二極體D1收容於個別之封裝，各半導體晶片5a~5d(封裝)間之布線路徑變長，寄生於該配線部之電感增大，結果具有非絕緣型DC-DC轉換器50A之電壓轉換效率降低之問題。圖29係表示寄生於非絕緣型DC-DC轉換器50A之電感成分之等價電路。符號LdH、Lgh、LsH、LdL、LgL、LsL表示寄生於功率MOS Q1、Q2之封裝及印刷布線基板之布線等之電感。又，VgH表示用以開啟功率MOS Q1之閘極電壓，符號VgL表示用以開啟功率MOS Q2之閘極電壓。由於寄生於高側開關用之功率MOS Q1之源極側之電感LsH及寄生於閘極側之LgH、寄生於低側開關用之功率MOS Q2之源極側之電感LsL之影響，非絕緣型DC-DC轉換器50A之電壓轉換效率降低。特別是寄生之電感LsH若增加，高側開關用之功率MOS Q1之開啟損失及關閉損失(特別是開啟損失)將顯著變大，非絕緣型DC-DC轉換器50A之電壓轉換效率會顯著降低。開啟損失及關閉損失係與頻率及輸出電流成比例，因此如上述，隨著非絕緣型DC-DC轉換器50A之電流增大及高頻化，損失成分將變大。
其次，說明有關若寄生之電感LsH增加，開啟及關閉變慢，開啟損失及關閉損失增加之原因。圖30為非絕緣型DC-DC轉換器50A之電路動作之說明圖，圖31為圖30之電路動作時之元件剖面說明圖。
若高側開關用之功率MOS Q1之閘極電壓超過臨限值，電流(第一電流)I1開始從功率MOS Q1之汲極區域DR1朝向源極區域SR1流動，由於寄生之電感LsH，產生反電動勢(LsH×di/dt)，相較於輸出節點N1，高側開關用之功率MOS Q1之源極電位變高。功率MOS Q1之閘極電壓係以輸出節點N1為基準，由驅動器電路3a所賦予，因此施加於連接在高側開關用之功率MOS Q1之閘極之閘極電極G1與源極區域SR1之間之電壓，變得比閘極電壓VgH低。因此，高側開關用之功率 MOS Q1之通道電阻R1未充分降低，故產生電流I1之損失。亦即，開啟時間變長。如上述，由於電力增大及高頻化而開啟損失及關閉損失增加，係由於反電動勢(LsH×di/dt)由於電力增大及高頻化而增加所致。
又，高側開關用之功率MOS Q1係具有在用以將電力，供給至非絕緣型DC-DC轉換器50A之輸出(負載電路4之輸入)之線圈L1，儲存能量之開關機能，因此於高頻化，要求開關動作之高速化。然而，於驅動器電路3a與功率MOS Q1之間，由於產生寄生之電感LgH，因此開關動作變慢。亦即成為開關損失，電壓轉換效率變低。
另一方面，於低側開關用之功率MOS Q2，構成上係比功率MOS Q1難以產生上述開關損失。亦即，若關閉高側開關用之功率MOS Q1，電流(第二電流)I21經由並聯地連接於低側開關用之功率MOS Q2之蕭特基障壁二極體D1而流至輸出側，而且電流(第二電流)I22經由寄生二極體Dp，從基準電位GND流往功率MOS Q2之汲極區域DR2。於此狀態，若將閘極電壓VgL施加在與低側開關用之功率MOS Q2之閘極之閘極電極G2，電流(第三電流)I23係從功率MOS Q2之源極區域SR2，經由功率MOS Q2之通道區域，流往汲極區域DR2，但之前已經流有上述電流I21、I22，電流I23流入時之每單位時間之電流變化量小，因此可忽視寄生之電感LsL所造成之反電動勢係小至可忽視程度，不會導致實質損失。然而，若如上述，寄生於蕭特基障壁二極體D1之陽極及陰極側之電感La、Lk較大，流至蕭特基障壁二極體D1側之電流I21變小，無法充分獲得連接順向電壓比寄生二極體Dp小之蕭特基障壁二極體D1所造成之效果。再者，於高側開關用之功率MOS Q1，亦同樣存在寄生二極體Dp，但高側開關用之功率MOS Q1側之寄生二極體Dp，係分別於功率MOS Q1之源極區域SR1側形成有陽極，於功率MOS Q1之汲極區域DR1側形成有陰極，並未對於從功率MOS Q1之汲極區域DR1往源極區域SR1流動之電流(第一電流)I1之相同方向，順向地連接。因此，於施加閘極電壓VgH以開啟之前，電流並未流至功率MOS Q1，每單位時間之電流變化量不會變小，因此產生開關損失。
又，功率MOS Q2為非絕緣型DC-DC轉換器50A之整流用電晶體，具有同步於來自控制電路2之頻率，降低電晶體之電阻以進行整流之機能。因此如上述，功率MOS Q2之開啟時間比功率MOS Q1長，因此相較於開關損失，開啟電阻所造成之損失變得顯著，要求開啟電阻之低電阻化。然而，於功率MOS Q2與被供給基準電位GND之端子(第二電源端子)ET4之間，由於寄生之電感LsL所產生之布線電阻(布線電感)，開啟電阻增加，電流轉換效率降低。
因此，於本實施型態4，構成上係於同一封裝收容：半導體晶片5a，其係形成有構成圖1所示之非絕緣型DC-DC轉換器1之高側開關用之功率MOS Q1者；半導體晶片5b，其係形成有低側開關用之功率MOS Q2及SBD D1者；及半導體晶片5c，其係形成有驅動器電路3a、3b者。如此，藉由將半導體晶片5a~5c收容於同一封裝內，相較於分別收容於不同封裝之構成，可縮短各半導體晶片5a~5c之布線路徑，因此可減低寄生於該布線之電感LdH、Lgh、LsH、LdL、LgL、LsL。因此可提升非絕緣型DC-DC轉換器1之電壓轉換效率，而且可使非絕緣型DC-DC轉換器1小型化。
在此，著眼於小型化或電感減低之情況，宜於同一半導體晶片形成高側開關用之功率MOS Q1及低側開關用之功率MOS Q2，但若於同一半導體晶片形成各電晶體，無法充分發揮各元件特性。又，製造過程變得複雜，半導體晶片之製造會耗費時間，並且亦有成本增大的問題。又，如上述，相較於高側開關用之功率MOS Q1，低側開關用之功率MOS Q2之開啟時間長，因此較易發熱。因此，若於同一半 導體晶片形成兩功率MOS Q1、Q2，唯恐低側開關用之功率MOS Q2在動作時所產生之熱，將經由半導體基板而對於高側開關用之功率MOS Q1造成不良影響。從此觀點考量，將高側開關用之功率MOS Q1、低側開關用之功率MOS Q2及驅動器電路3a、3b，分別分開形成於另外之半導體晶片5a~5c。藉此，相較於將高側開關用之功率MOS Q1、低側開關用之功率MOS Q2及驅動器電路3a、3b，形成於同一半導體晶片之情況，可充分發揮各元件特性。又，可使非絕緣型DC-DC轉換器1之製造過程變得容易，因此可縮短非絕緣型DC-DC轉換器1之製造時間，而且可減低成本。又，可使高側開關用之功率MOS Q1及驅動器電路3a、3b，不受低側開關用之功率MOS在動作時所產生之熱之不良影響，因此可提升非絕緣型DC-DC轉換器1之動作安定性。再者，驅動器電路3a、3b係互相同步而交互動作，因此從全體電路動作安定性之觀點來考量，而形成於同一半導體晶片5c。
然而，如上述，為了提升非絕緣型DC-DC轉換器1之電壓轉換效率，重要的是將各半導體晶片5a~5c收容於同一封裝，但僅單純地收容在同一封裝，並無法獲得充分提高電壓轉換效率之效果。因此，說明有關在提升非絕緣型DC-DC轉換器1之電壓轉換效率上，重要封裝內之具體構成例。
圖32表示封裝20B之主面側之全體平面圖，圖33表示圖32之封裝20B之側面圖，圖34表示封裝20B之背面側之全體平面圖，圖35表示圖32之封裝20B之外觀立體圖。
本實施型態4之封裝20B為例如：QFN(Quad Flat Non-leaded package：四方無引腳扁平封裝)之構成。但不限於QFN，亦可進行各種變更，例如：QFP(Quad Flat Package：四方扁平封裝)或SOP(Small Out-line Package：縮小外型封裝)等扁平封裝構成亦可。
構成封裝20B之樹脂密封體MB係其外觀形成為薄板狀。樹脂密 封體MB係由例如：環氧系樹脂所組成。又，從謀求低應力化等理由來看，作為樹脂密封體MB之材料，使用例如：酚系硬化劑、矽膠及添加有填充劑等之聯苯系熱硬化性樹脂亦可。作為樹脂密封體MB之形成方法，採用適合大量生產之轉移成形法。從此樹脂密封體MB之背面，露出例如：平面大致矩形之3個晶片墊(第一~第三晶片搭載部)7a1、7a2、7a3之背面。又，從樹脂密封體MB之四側面及背面外周，沿著樹脂密封體MB之外周，露出複數引線(外部端子)7b之一部分。晶片墊7a1、7a2、7a3及引線7b係以例如：42合金等之金屬材料為主材料所形成，其厚度為例如：200μm程度。作為晶片墊7a1、7a2、7a3及引線7b之其他材料，亦可使用在例如：銅(Cu)或銅之表面，依序由表面電鍍鎳(Ni)、鈀(Pd)及金(Au)者。如後述，於晶片墊7a1、7a2之主面，分別搭載有上述半導體晶片5a、5b。又，於晶片墊7a3之主面，搭載有上述半導體晶片5c。於晶片墊7a3之1個角部，形成有定位用之錐形TR1(索引標記)。此錐形TR1係於例如：將封裝20B出貨時之對排或於封裝20B印刷商標等時，用於區別封裝20B之背面、背面，藉由例如：蝕刻所形成。搭載形成有功率MOS Q1、Q2之半導體晶片5a、5b之晶片墊7a1、7a2，係從第一、第二電源端子供給電流I1、I2之部分，因此若形成錐形TR1，外型尺寸將變小，唯恐影響電流特性。相對於此，於晶片墊7a3未流有動態電流，因此電位固定，不甚需要注意電流特性，故定位用之錐形TR1宜形成在晶片墊7a3之一部分。
再者，於此構造，晶片墊7a1~7a3之背面(搭載有半導體晶片5a、5b、5c之面之相反側之面)、引線7b背面(與布線基板之端子接合之接合面)均存在於封裝20B之搭載面(將封裝20B搭載於布線基板時，與布線基板對向之面)。
其次，圖36係表示透視觀看封裝20B之內部時之封裝20B之主面 側之全體平面圖，圖37表示圖36之Y3-Y3線之剖面圖，圖38表示圖36之X4-X4線之剖面圖。再者，圖36雖為平面圖，但為了易於觀看，於晶片墊7a1~7a3、引線7b及布線部7c附加影線。
於封裝20B內，於封裝20B內密封有：上述3個晶片墊7a1~7a3(第一~第三晶片搭載部)、於該晶片墊7a1~7a3上如後述所搭載之複數半導體晶片5a~5c、及將半導體晶片5a~5c之墊BP1~BP11電性連接於各部之金屬線WA1、WA2、WB1~WB6。
晶片墊7a1~7a3係以具有特定間隔7a1~7a3而分離之狀態鄰接配置。半導體晶片5a~5c在動作時所產生之熱，主要經由半導體晶片5a~5c之背面，經由晶片墊7a1~7a3而從其背面側散熱至外部。因此，各晶片墊7a1~7a3形成比半導體晶片5a~5c之面積大。藉此，可提高非絕緣型DC-DC轉換器1之散熱性，提高動作安定性。晶片墊7a1~7a3及引線7b之背面側之外周一部分係以其厚度變薄之方式，形成半蝕刻區域。此係為了提升晶片墊7a1~7a3及引線7b與樹脂密封體MB之密接性，減低或防止晶片墊7a1~7a3及引線7b剝離或變形故障。
於圖36左上之晶片墊7a1上，形成有上述高側開關用之功率MOS Q1之半導體晶片5a，係以其主面朝上之狀態配置。於此半導體晶片5a之主面，配置有功率MOS Q1之源極電極用之墊BP2及閘極電極用之墊6BP1。此源極電極用之墊BP2係經由複數條金屬線WA1，而與晶片墊7a2電性連接，並且經由複數條金屬線WB1，而與半導體晶片5c之驅動器電路3a之源極電極用之墊BP3電性連接。又，上述閘極電極用之墊6BP1係經由複數條金屬線WB2，而與半導體晶片5c之驅動器電路3a之輸出(汲極)電極用之墊BP4電性連接。並且，半導體晶片5a之背面係成為與功率MOS Q1之汲極連接之汲極電極，經由晶片墊7a1，與一體形成於晶片墊7a1外周之複數引線7b1(7b)電性連接。此引線7b1係與上述端子ET1電性連接。再者，金屬線WA1係以鄰接於第一 方向X之金屬線WA1交互連接於上下墊BP2之方式而交叉配置。
形成有高側開關用之功率MOS Q1之半導體晶片5a係形成為，圖36之第一方向X之長度比正交於此之第二方向Y之長度長之長方形。此半導體晶片5a係從晶片墊7a1之中央接近晶片墊7a2而偏離配置。亦即，半導體晶片5a係接近於鄰接在晶片墊7a2之一邊之晶片墊7a1之一邊而配置。如此，藉由將半導體晶片5a接近晶片墊7a2而配置，可縮短連接功率MOS Q1之源極電極用之墊BP2及晶片墊7a2之金屬線WA1之長度，因此可於功率MOS Q1之源極與功率MOS Q2之汲極之間，減低寄生之電感LsH。又，半導體晶片5a係其長邊沿著晶片墊7a2之鄰接長邊而配置。藉此，可確保半導體晶片5a之源極電極用之墊BP2與晶片墊7a2之對向長度，因此可配置複數條上述金屬線WA1，減低功率MOS Q1之源極與功率MOS Q2之汲極之間之電感LsH。又，藉由將半導體晶片5a形成長方形，可縮短延伸在圖36之第二方向Y之以多晶矽所形成之閘極布線之長度，因此可減低功率MOS Q1之閘極電阻。並且，半導體晶片5a係特別使半導體晶片5a之閘極電極用之墊6BP1與半導體晶片5c之輸出電極用之墊BP4之距離接近而配置，以便使半導體晶片5a、5c間之距離比半導體晶片5a、5b間之距離短。此係考慮在高側開關用之功率MOS Q1，該閘極之電感增大會大幅影響開關損失之增大之構成；藉由將半導體晶片5a接近半導體晶片5c而配置，可縮短電性連接功率MOS Q1之閘極電極用之墊6BP1與驅動器電路3a之輸出電極用之墊BP4之金屬線WB2之長度，因此可減低寄生於功率MOS Q1之閘極之電感LgH，減低功率MOS Q1之開關損失。藉由如以上之半導體晶片5a之配置，可減低功率MOS Q1之開關損失，提高非絕緣型DC-DC轉換器1之電壓轉換效率。
又，於半導體晶片5a之源極電極用之墊BP2，電性連接有2種金屬線WA1、WB1。亦即，將與半導體晶片5a之源極電極用之墊BP2電 性連接之金屬線，區分成與晶片墊7a2連接之金屬線WA1及與驅動器電路3a之源極連接之金屬線WB1。藉此，可分散從功率MOS Q1之源極經由晶片墊7a2而流至輸出端子之電流I1，及流往驅動器電路3a之電流之路徑，因此可減低在各金屬線WA1、WB1所產生之電流負載。因此可減低產生於功率MOS Q1與驅動器電路3a之間之寄生電感，因此可進一步改善開關損失。
又，上述金屬線WA1、WB1、WB2均由例如：金(Au)所組成，但金屬線WA1使用比金屬線WB1、WB2粗者。藉此，可減低功率MOS Q1之源極側之布線電感，因此可減低非絕緣型DC-DC轉換器1之開關損失，提高電壓轉換效率。
又，於圖36下側之面積最大之晶片墊7a2上，形成有上述低側開關用之功率MOS Q2及SBD D1之半導體晶片5b，係以其主面朝上之狀態配置。於此半導體晶片5b之主面，配置有功率MOS Q2之源極電極及SBD D1之陽極用之墊BP1及閘極電極用之墊6BP2。此墊BP1係經由複數條金屬線WA2，而與引線7b2(7b)電性連接，並且經由複數條金屬線WB3，而與半導體晶片5c之驅動器電路3b之源極電極用之墊BP7電性連接。又，上述閘極電極用之墊6BP2係經由複數條金屬線WB4，而與半導體晶片5c之驅動器電路3b之輸出(汲極)電極用之墊BP8電性連接。並且，半導體晶片5b之背面係成為功率MOS Q2之汲極電極及SBD D1之陰極電極，經由晶片墊7a2，與一體形成於晶片墊7a2外周之複數引線7b3(7b)電性連接。此引線7b3係與輸出用之上述端子ET5電性連接。
形成有低側開關用之功率MOS Q2之半導體晶片5b係形成為，圖36之第一方向X之長度比第二方向Y之長度長之長方形。此半導體晶片5b係沿著半導體晶片5a而配置，但離開半導體晶片5b，以接近引線7b2之方式，從晶片墊7a2之中央偏離配置。亦即，半導體晶片5b係不 接近輸出用端子ET5所連接之引線7b3，而接近供給有基準電位GND之端子ET4之引線7b2之晶片墊7a2之角部(圖36之左側角部)而配置。而且，半導體晶片5b之第二方向Y之長度係與連接有複數引線7b2之布線部7c之第二方向Y之長度大致相等，而且半導體晶片5b之第一方向X之長度係與與連接有複數引線7b2之布線部7c之第一方向X之長度大致相等。藉由此構成，可縮短連接功率MOS Q2之源極電極及SBD D1之陽極電極用之墊BP1與引線7b2之金屬線WA2之長度。又，半導體晶片5a之互相交叉之長邊及短邊之2邊，係配置成沿著複數引線7b2之配置形狀(平面L字狀)，特別是成為功率MOS Q2之源極電極及SBD D1之陽極電極用之墊BP1沿著複數引線7b2之配置形狀延伸之形狀。藉此，可較長地確保墊BP1與複數引線7b2之一群之對向長度，因此可配置複數條上述金屬線WA2。並且，複數引線7b2係沿著晶片墊7a2之互相正交之2邊而配置，且連接在沿著該2邊延伸之平面L字狀之布線部7c。如此，藉由將複數引線7b2匯總連接，體積將比分割複數引線7b2增加，可減低布線電阻，強化基準電位GND。此類構成係考慮在低側開關用之功率MOS Q2之源極側之開啟電阻增大，會大幅影響開關損失之增大之構成；藉由成為上述構成，可減低功率MOS Q2之源極側之開啟電阻，因此可減低功率MOS Q2之導通損失。又，可減低在金屬線WA2所產生之寄生阻抗之偏差，因此亦可減低流至金屬線WA2之電流大小之偏差。藉此，可提高非絕緣型DC-DC轉換器1之電壓轉換效率。又，可強化基準電位GND，提升非絕緣型DC-DC轉換器1之動作安定性。
又，關於SBD D1，SBD D1之陽極電極亦經由大面積之晶片墊7a2，而與輸出布線或功率MOS Q1之汲極電極電性連接，因此可大幅減低寄生於上述陰極之電感Lk。又，如前述，藉由在同一半導體晶片5b形成功率MOS Q2及SBD D1，可縮短連結SBD D1之陽極與功率 MOS Q2之源極之布線長，因此可大幅減低寄生於該布線之電感La。亦即，可減低寄生於SBD D1之陽極及陰極之電感La、Lk，因此如上述，可充分發揮SBD D1之效果，減低二極體導通損失及二極體恢復損失，提高非絕緣型DC-DC轉換器1之電壓轉換效率。又，可減低電感La、Lk，因此亦可減低雜訊。
又，如上述，由於低側開關用之功率MOS Q2在動作時之發熱量最高，因此搭載於面積最大之晶片墊7a2。藉此，可提高在功率MOS Q2所產生之熱之散熱性，因此可提高非絕緣型DC-DC轉換器1之動作安定性。
又，上述金屬線WA2、WB3、WB4均由例如：金(Au)所組成，但金屬線WA2使用比金屬線WB3、WB4粗者。藉由使用粗金屬線WA2，作為電性連接於功率MOS Q2之源極及SBD D1之陽極之金屬線，可減低功率MOS Q2之源極及SBD D1之陽極側之布線電阻，因此可減低功率MOS Q2之開啟電阻，而且可減低二極體之損失，故可提高非絕緣型DC-DC轉換器1之電壓轉換效率。
並且，於圖36右上之面積最小之晶片墊7a3上，形成有上述驅動器電路3a、3b之半導體晶片5c，係以其主面朝上之狀態配置。於此半導體晶片5c之主面，除了上述墊BP3、BP4、BP7、BP8以外，還配置有驅動器電路3a、3b之各信號輸入電極(閘極)電極用之墊BP10及源極電極用之墊BP11。此閘極電極用之墊BP10係經由複數條金屬線WB5，而與引線7b4(7b)電性連接。源極電極用之墊BP11係經由複數條金屬線WB6，而電性連接於與晶片墊7a3一體形成之引線7b5(7b)電性連接。
形成有此驅動器電路3a、3b之半導體晶片5c亦形成平面矩形狀，於半導體晶片5c之主面，與功率MOS Q1、Q2連接之墊BP3、BP4、BP7、BP8係沿著與半導體晶片5a、5b之各個鄰接側之2邊配置。藉 此，可更縮短金屬線WB1、WB2、WB3、WB4之長度，因此進一步減低在布線路徑所產生之寄生之電感LgH、LsH、LgL、LsL。又，如上述，於半導體晶片5a，相較於開啟電阻，更要減低開關損失，因此除了如上述，使半導體晶片5c與半導體晶片5a之距離比半導體晶片5c與半導體晶片5b之距離更近而配置之點以外，關於上述金屬線WB1、WB2、WB3、WB4，亦將分別與功率MOS Q1之源極、閘極電性連接之金屬線WB1、WB2，比分別與功率MOS Q2之源極、閘極電性連接之金屬線WB3、WB4更短地形成。
上述半導體晶片5a~5c由於各個特性不同，因此外型尺寸(面積)不同，半導體晶片5a之外型尺寸比半導體晶片5c之外型尺寸更大地形成，半導體晶片5b之外型尺寸比半導體晶片5a之外型尺寸更大地形成。由於具有驅動器電路3a、3b之半導體晶片5c為控制功率MOS Q1、Q2之閘極之控制電路，因此考慮封裝全體之尺寸，儘可能縮小元件之外型尺寸。相對於此，於功率MOS Q1、Q2，由於流有電流I1、I2，因此儘可能減低在電晶體內所產生之開啟電阻。為了減低開啟電阻，可加大每單位電晶體格之通道寬而實現。因此，半導體晶片5a、5b之外型尺寸係比半導體晶片5c之外型尺寸更大地形成。並且如圖3所示，由於低側開關用之功率MOS Q2之開啟時間係比高側開關用之功率MOS Q1長，因此功率MOS Q2之開啟電阻必須比功率MOS Q1之開啟電阻更減低。因此，半導體晶片5b之外型尺寸比半導體晶片5a之外型尺寸更大地形成。
再者，上述金屬線WA1、WA2、WB1~WB6係藉由例如：超音波熱壓著接合法而連接，但若超音波能量無法順利傳達至晶片墊7a1~7a3或引線7b之金屬線接合部，唯恐成為接合故障，因此避開上述半蝕刻區域而進行金屬線接合。藉此可減少或防止接合故障。
又，於連接於半導體晶片5c之金屬線WB1~WB6使用細金屬線之 理由在於，若使用粗金屬線，必然亦必須增大墊BP3、BP4、BP7、BP8、BP10、BP11等，晶片尺寸增大，成本變高。
其次，圖39表示上述半導體晶片5a之放大平面圖，圖40表示圖39之X5-X5線之剖面圖，圖41表示半導體晶片5a之要部剖面圖，圖42表示圖39之Y4-Y4線之剖面圖。
半導體晶片5a係具有：半導體基板5HS；形成於此半導體基板5HS主面(墊BP2、6BP1之形成面側)之複數單位電晶體元件；於半導體基板5HS之主面上，將絕緣層9b及閘極指叉6c、6d之各個層疊複數段之多層布線層；及包覆此閘極指叉6c、6d而形成之表面保護膜(最終保護膜)18等。半導體基板5HS係由例如：n+型之矽(Si)單晶所組成。絕緣層9b係由例如：氧化矽膜所組成。墊BP2、6BP1、閘極指叉6c、6d係由例如：鋁(Al)之金屬材料所組成，在此為最上面之布線層。表面保護膜18係於例如：氧化矽膜、氮化矽(Si3N4)膜，或其等之疊層膜上，層疊如聚醯亞胺膜(PiQ)之有機膜而成。
半導體晶片5a具有互相位於相反側之主面(電路形成面)5ax及背面(背面電極形成面)5ay。於半導體晶片5a之主面5ax側，形成有積體電路及墊BP2、6BP1，於背面5ay形成與汲極區域DR電性連接之背面電極HBE。積體電路主要由形成在半導體基板5HS之主面5ax之電晶體元件、墊BP2及閘極指叉6ac、6d等所構成。背面電極HBE係蒸鍍有例如：金(Au)等金屬而形成，並如上述與晶片墊7a2連接。於表面保護膜18，以露出墊BP2、閘極指叉6c之一部分之方式而形成開口部19。
源極電極用之墊BP2係於半導體晶片5a之寬度方向(第二方向Y)形成2個，各墊BP2係以互相對向而沿著半導體晶片5a之長度方向(第一方向X)之狀態形成。閘極電極用之墊6BP1係配置於半導體晶片5之一方短邊附近。閘極電極用之墊6BP1之平面形狀為例如：正方形， 其平面尺寸為例如：280μm×280μm程度。閘極電極用之墊6BP1係與閘極指叉6c、6d一體地形成。閘極指叉6d係從墊6BP1沿著半導體晶片5a之長度方向延伸之圖案，配置於上述2個墊BP2之間。另一方之閘極指叉6c係沿著半導體晶片5a之外周而延伸之圖案，包圍2個圖案BP2而配置。閘極指叉6c、6d之寬度為例如：25μm程度。藉由如此構成，可使源極電極用之墊BP2靠近上述晶片墊7a2，且沿著1對長邊而配置。藉此，可縮短電性連接源極電極用之墊BP2及晶片墊7a2之金屬線WA1之長度，並且將更多之金屬線WA1排列配置，故可減低寄生之電感LsH。又，於閘極指叉6d，半導體晶片5a之一方端部(與墊6BP1連接之邊之相反側之端部)係不與閘極指叉6c之一部分相連而形成，可不將功率MOS Q1之源極區域SR1分離而形成。亦即，不分離源極區域SR1而形成，可減低開啟電阻。
於上述半導體基板5HS之主面，形成由例如：n型之矽單晶所組成之磊晶層5HEP。於此磊晶層5HEP形成有：n-型半導體區域24n1；於其上之p型半導體區域24p1；於其上之n+型半導體區域24n2；p+型半導體區域24p2其係從半導體基板5HS之主面，連接於上述p型半導體區域24p1而延伸者。而且，於此半導體基板5HS及磊晶層5HEP，形成例如：溝槽構造之n通道型之縱型功率MOS Q1。
功率MOS Q1係具有：具有作為源極區域SR1之機能之上述n+型半導體區域24n2、具有作為汲極區域DR1之機能之上述n-型半導體區域24n1、具有作為通道型成區域CH1之機能之上述p型半導體區域24p1、形成在磊晶層5HEP之厚度方向所挖掘之溝14之內壁面之閘極絕緣膜15b、及經由閘極絕緣膜15b而埋入溝14內之閘極電極8G。閘極電極8G係以例如：低電阻之多晶矽所形成。藉由製成此溝槽閘極構造，可實現功率MOS Q1之單位區域之微細化及高積體化。
各格之閘極電極8G係經由與此一體成形之由多晶矽所組成之閘 極布線8L，而拉出至場絕緣膜FLD上，並經由接觸孔洞11d而與上述閘極指叉6d電性連接。閘極電極8G及閘極布線8L表面係以上述表面保護膜18所包覆，以謀求與墊BP2之絕緣。除了源極用之n+型半導體區域24n2以外，墊BP2亦經由p+型半導體區域24p2而與通道形成用之p型半導體區域24p1電性連接。功率MOS Q1之動作時之上述電流I1係沿著溝14之深度方向(流向漂流層之厚度方向)，而流於源極區域SR1與汲極區域DR1之間，且沿著閘極絕緣膜15b之側面流動。相較於通道相對於半導體基板主面而形成於水平方向之橫型場效電晶體，此縱型功率MOS Q1係每單位格面積之閘極面積大，而且閘極電極8G與汲極之漂流層之接合面積大，因此閘極-汲極間之寄生電容大，但另一方面，可增大每單位格面積之通道寬，縮小開啟電阻。再者，PWL2為p-型之p井。
其次，關於形成有低側開關用之功率MOS Q2之半導體晶片5b之元件構成，已於前述實施型態1說明，因此省略。但低側開關用之功率MOS Q2之臨限值電壓，係以高於高側開關用之功率MOS Q1之臨限值之值控制。此係為了抑制將開關從高側開關用之功率MOS Q1切換為低側開關用之功率MOS Q2時，產生電流(貫通電流)從端子ET1流向端子ET4之現象(自開啟現象)，藉由如上述，可抑制或遮斷貫通電流之路徑，因此可抑制或防止上述自開啟。
其次，說明有關形成有控制用之驅動器電路3a、3b之半導體晶片5c。半導體晶片5c之電路構成及元件剖面構成係與圖5及圖6所說明者相同。於圖43表示驅動器電路3a之基本構成例。再者，驅動器電路3b之元件構成係與驅動器電路3a大致相同，因此說明驅動器電路3a以省略驅動器電路3b。
驅動器電路3a具有：形成於n型井NWL2之p通道型之橫型(通道係相對於半導體基板SUB之主面而形成於水平方向之類型)功率MOS Q3；及形成於p型井PWL3之n通道型之橫型功率MOS Q4。功率MOS Q3具有：源極區域SR3、汲極區域DR3、閘極絕緣膜15p及閘極電極G3。源極區域SR3及汲極區域DR3係具有p-型半導體區域25a、p+型半導體區域25b。功率MOS Q4具有：源極區域SR4、汲極區域DR4、閘極絕緣膜15n及閘極區域G4。源極區域SR4及汲極區域DR4係具有：n-型半導體區域26a及n+型半導體區域26b。又，汲極區域DR3、DR4連接於輸出用之端子ET7，經由輸出用之端子ET7，電性連接於高側開關用之功率MOS Q1之閘極。又，源極區域SR4連接於端子ET8，經由此端子ET8而電性連接於高側開關用之功率MOS Q1之源極。
其次，圖44係示封裝20B之安裝狀態之一例之平面圖，圖45係表示圖44之封裝20B之側面圖。再者，於圖44，為了理解布線基板30之布線狀態而透視封裝20B。
布線基板30係由例如：印刷布線基板，於其主面搭載封裝20B、31、32及晶片零件33、34。於封裝31形成有上述控制電路2，於封裝32形成有上述負載電路4。於晶片零件33形成有上述線圈L1，於晶片零件34形成有上述電容器C1。封裝31之引線31a係經由布線基板30之布線30a，而與封裝20B之引線7b(7b4)電性連接。封裝20B之引線7b1係與布線基板30之布線30b電性連接。封裝20B之輸出之引線(輸出端子)7b3係經由布線基板30之布線(輸出布線)30c，而電性連接於晶片零件33之線圈L1之一端。晶片零件33之線圈L1之另一端係經由布線基板30之布線(輸出布線)30d，而與負載電路4電性連接。封裝20B之基準電位GND用之引線7b2係經由布線基板30之布線30e，而與複數晶片零件34之電容器C1之一端電性連接。晶片零件34之電容器C1之另一端係經由布線基板30之布線30d，而與負載電路4電性連接。
其次，圖46係表示包含本實施型態1之封裝20B之非絕緣型DC-DC轉換器1之電路系統構成之一例。於此電路系統，對於1個負載電 路4係並聯連接有複數個封裝20B。於複數個封裝20B，輸入電源電位Vin、基準電位GND及控制電路2係為共同。於此電路系統，若為功率MOS Q1、Q2、驅動器電路3a、3b、SBD D1分別個別封裝之構成，會妨礙系統全體之小型化。對於此，於本實施型態1，由於功率MOS Q1、Q2、驅動器電路3a、3b、SBD D1(SBD D1形成在與功率MOS Q2相同之半導體晶片5b)收容於同一封裝20B，因此可使系統全體小型化。
其次，以本實施型態1之封裝20B之組裝方法，說明圖47之組裝流程圖。
首先，準備3種半導體晶圓及切割台(步驟100a、100b)。於3種半導體晶圓之主面，分別形成複數個半導體晶片5a~5c。接著於各半導體晶圓之背面，貼附切割膠帶，藉由切割刀分別切出半導體晶片5a~5d(步驟101、102)。
其次，準備引線架及黏晶糊(步驟103a、103b)。於圖48及圖49，表示引線架7之單位區域之要部平面圖之一例。圖48表示引線架7之主面，圖49表示引線架7之背面。引線架7具有：沿著圖48左右方向延伸之2個框體部7f1；以橫跨2個框體部7f1間之方式，延伸在對於框體部7f1正交方向之框體部7f2；從框體部7f1、7f2內周往單位區域中央延伸之複數引線7b；及與此複數引線7b一體成形，經由該引線7b而由框體部7f1、7f2支撐之3個晶片墊7a1~7a3及L字狀之布線部7c。於引線7b及晶片墊7a1~7a3之背面側外周，形成有半蝕刻區域HF，比其他部分薄。再者，於圖49，為了易於觀看圖式，在上述半蝕刻區域HF附加斜線之影線。又，作為黏晶糊則使用例如：銀(Ag)糊。
接著，於上述引線架7之各單位區域之晶片墊7a1~7a3之主面，經由黏晶糊搭載上述半導體晶片5a~5c之後，施加熱處理，使黏晶糊硬化，如圖50之步驟S1所示，將半導體晶片5a~5c固定於晶片墊7a1~7a3 上(步驟104、105)。依序搭載小的半導體晶片5c、5a、5b，亦可謀求生產性提升。
其次，準備2種金屬線WA1、WA2、WB1~WB6(步驟106a、106b)。金屬線WA1、WA2、WB1~WB6均由例如：金(Au)所組成，但金屬線WA1、WA2為例如：50μm粗之粗金屬線，金屬線WB1~WB6為例如：30μm粗之細金屬線。接著，藉由超因波熱壓著法，接合2種金屬線WA1、WA2、WB1~WB6(步驟106)。在此，於粗金屬線WA1、WA2之接合處理，需要比細金屬線WB1~WB6之接合處理時更大之荷重，因此若於將細的金屬線WB1~WB6接合後，再接合粗金屬線WA1、WA2，唯恐由於當時甚大之荷重，細的金屬線WB1~WB6會斷線。特別是根據發明者之檢討，於晶片墊7a1~7a3分離之情況，容易產生上述金屬線斷線故障。因此，於本實施型態4之金屬線接合步驟，如圖50之步驟S2、S3所示，於接合粗金屬線WA1、WA2之後，再接合細金屬線WB1~WB6。藉此可抑制或防止細金屬線WB1~WB6之斷線故障。
其次，準備密封用樹脂及密封用膠帶(步驟107a、107b)。接著藉由轉移成形法進行樹脂密封(成形)步驟(步驟108)。轉移成形法係使用具備壺、澆道、樹脂注入澆口及模穴等之成形模具(mold die)，從壺經由澆道及樹脂注入澆口，將熱硬化性樹脂注入於模穴內部，形成樹脂密封體MB之方法。於QFN型之封裝20B之製造採用：個別方式轉移成形法，其係使用具有複數形成區域(裝置形成區域、製品取得區域)之取得多數個引線架，該搭載於各製品形成區域之半導體晶片，樹脂密封於各製品形成區域者；或一次集中方式之轉移成形法，其係將搭載於各製品形成區域之半導體晶片，一次集中進行樹脂密封者。於本實施型態4採用例如：個別方式之轉移成形法。
於此樹脂密封步驟係例如其次。首先，於樹脂成形模具之下模 之模具面上配置密封用膠帶之後，於該密封用膠帶上配置引線架7，並進行樹脂成形模具之緊模(夾模)，以便使複數引線7b之一部分及晶片墊7a1~7a3之背面密接於密封用膠帶。於樹脂密封步驟之前，在引線架7之背面預先貼附密封用膠帶之理由在於防止，如本實施型態4，在1個封裝6內具有複數晶片墊7a1~7a3之構成者之樹脂密封步驟，於如圖48所示之形成3個晶片墊7a1~7a3之邊界之狹縫之交點部分Z，容易產生樹脂漏洩，經由該交點部分Z而進入晶片墊7a1~7a3背面(將封裝20B安裝於布線基板時之安裝面)側之樹脂(樹脂刺)將妨礙封裝20B之安裝，導致安裝故障。於本實施型態4，為使不產生如上述之樹脂漏洩，於密封步驟之前，將密封用膠帶確實貼附於3個晶片墊之背面側(包含形成3個晶片墊之邊界之狹縫)，使密封用樹脂不致從上述交點附近Z等，漏洩到晶片墊7a1~7a3背面。藉此可防止樹脂刺所造成之封裝20B之安裝故障。如上述，密封用膠帶宜於密封步驟時，確實黏著於晶片墊7a1~7a3等，因此從該觀點來看，密封用膠帶之黏著強度宜可獲得例如：0.5N以上之高黏性強度者。另一方面，近年來使用例如：施加有鎳(Ni)/鈀(Pd)/金(Au)薄鍍之引線架7。此係由於Pd(鈀)電鍍製之引線架7之情況，將封裝20B安裝於布線基板時，可使用無鉛焊錫，對於環境良好之效果以外，相對於於一般之引線架，為了金屬線接合，必須預先於引線架之金屬接合部塗布銀(Ag)糊，具有即使不塗布該類Ag糊，仍可連接金屬線等優點。然而，於Pd電鍍製之引線架7之情況，亦產生如上述由於樹脂刺所造成之安裝故障問題，因此已形成樹脂刺之情況，藉由洗淨處理等除去樹脂刺，但Pd電鍍製之引線架7之情況，為了減少製造步驟，於樹脂密封步驟前，在引線架7施加電鍍處理，因此若要藉由洗淨處理等剝離此樹脂刺，將具有預先電鍍之Pd電鍍膜亦剝離之問題。亦即，可能無法使用Pd電鍍製之引線架7。相對於此，如上述，於本實施型態4可防止形成樹脂刺，於密封步 驟後無須進行強力之洗淨處理即可，因此可使用具有如上述良好優點之Pd電鍍製之引線架7。
接著，於上模(模穴)內注入密封用樹脂，以晶片墊7a1~7a3之一部分及複數引線7b之一部分從樹脂密封體MB(密封構件)露出之方式，將半導體晶片5a~5c及複數金屬線WA1、WA2、WB1~WB6進行樹脂密封，形成樹脂密封體MB。於本實施型態4，如上述，於晶片墊7a1~7a3及引線7b背面之周邊部，形成半蝕刻區域。如此地形成半蝕刻區域(附加斜影線之區域)，可強化晶片墊7a1~7a3及引線7b與樹脂密封體MB之密接力。亦即可抑制或防止引線脫落。特別是加上伴隨半導體裝置之輕薄輕量化，引線架厚度易變薄，引線7b相較於其他部分變細，而且其前端為未與其他部分連接而浮起之狀態，因此若未採取任何手段而進行樹脂密封，會有引線部分變形或剝離之情況。因此，將引線7b之前端側之背面外周部分亦進行半蝕刻，於引線7b之前端側之背面外周形成階差。藉此，於密封步驟時，密封用樹脂將流入該半蝕刻部分，包覆半蝕刻部分，將引線7b之前端側外周部壓下，因此可抑制或防止引線7b變形或剝離。
如上述樹脂密封步驟後，將注入之密封用樹脂硬化(樹脂硬化步驟108)，進行標記步驟109之後，從引線架7將各製品部分分割(步驟110)。
(實施型態5)
圖51係表示本實施型態5之封裝20C之構成例之平面圖，圖52表示圖51之X6-X6線之剖面圖，圖53表示圖51之Y5-Y5線之剖面圖。再者，圖51亦為了易於觀看，將樹脂密封體MB透明表示，並且於晶片墊7a1、7a2、引線7b及布線部7c附加影線。
於本實施型態5，將墊及各部電性連接之布線之一部分係以金屬板布線21取代金屬線。亦即，半導體晶片5a之功率MOS Q1之源極電 極用之墊BP2係經由1個金屬板布線21，而與晶片墊7a2電性連接。又，半導體晶片5b之功率MOS Q2之墊BP1係經由1個金屬板布線21，而與引線7b2(7b)電性連接。此金屬板布線21之構成或與各部之連接方法係與前述實施型態1所說明者相同，因此省略說明。金屬板布線21之其全體亦由樹脂密封體MB所包覆。
如此，若根據本實施型態5，藉由使用金屬板布線21以取代金屬線，可進一步減低寄生於布線路徑之電感及阻抗，因此可進一步減低開關損失及二極體導通損失，比實施型態4更提升非絕緣型DC-DC轉換器1之電壓轉換效率。
又，由於以大面積之金屬板布線21，將SBD D1之陽極電極電性連接於基準電位GND，因此可大幅減低陽極側之布線電阻及寄生於陽極側之電感La。因此，相較於前述實施型態4，可充分發揮SBD D1之效果，減低二極體導通損失及二極體恢復損失，因此可進一步提升非絕緣型DC-DC轉換器1之電壓轉換效率。又，由於可減低電感Lk、La，因此亦可進一步減低雜訊。
在此，若僅著眼於寄生在布線路徑之電感之情況，亦宜以金屬板布線21，形成將驅動器電路3a、3b之複數墊BP3、BP4、BP7、BP8、BP10、BP11與各部電性連接之金屬線WB1~WB6。然而，驅動器電路3a、3b之複數墊BP3、BP4、BP7、BP8、BP10、BP11之開口部窄至例如：90μm，若使用金屬板布線21取代金屬線WB1~WB6，金屬板布線21亦不得不使用寬度窄者，相較於金屬線，預測在減低寄生電感上，亦無法發揮充分效果。又，由於難以製造例如：100μm以下之金屬板布線21，比金屬線難以連接，因此唯恐製品成本增加或製品良率降低。又，由於驅動器電路3a、3b之半導體晶片3c亦收容於同一封裝20C內，因此以金屬線亦可充分縮小寄生電感。因此於本實施型態5，採用以金屬線WB1~WB6連接驅動器電路3a、3b之複數墊BP3、 BP4、BP7、BP8、BP10、BP11與各部之構成。
但如上述連結功率MOS Q1、Q2與驅動器電路3a、3b之布線路徑，為了減低於該布線路徑之寄生電感，因次將複數條金屬線WB1、WB2排列連接。亦即，於此部分，可使用例如：200μm寬之寬度大之金屬板布線21，因此可使用金屬板布線21取代金屬線WB1、WB2。如此，關於功率MOS Q1、Q2及驅動器電路3a、3b之間，藉由以金屬板布線21連接雙方，可減低寄生之電感，因此可減低開關損失。
(實施型態6)
圖54及圖55係表示相當於本實施型態6之封裝20D之圖51之X6-X6線及Y5-Y5線之處之剖面圖。再者，封裝20D內之狀態係與圖51所示相同。又，封裝20D上面係與封裝20D之搭載面(與布線基板對向之面)相反側之面。
於本實施型態6，與前述實施型態5相同，墊及各部係藉由金屬板布線21連接。但該金屬板布線21之一部分從樹脂密封體MB露出。金屬板布線21特別包覆半導體晶片5a、5b之熱產生源之功率MOS Q1、Q2之形成區域之方式而配置。在此係例示包覆半導體晶片5a、5b之2個金屬板布線21，雙方從封裝20D上面露出之情況，但構成上亦可僅露出形成有發熱量相對高之低側開關用之功率MOS Q2之半導體晶片5b側之金屬板布線21。又，藉由在封裝20D之上面搭載散熱片，並接合於金屬板布線21之露出面，亦可進一步提高散熱性。
若根據本實施型態6，除了以前述實施型態4、5所獲得之效果以外，藉由使金屬板布線21具有散熱機能，由於無須追加散熱用之其他零件，因此相較於追加散熱用零件之情況，可僅少封裝20D之組裝步驟，縮短封裝20D之組裝時間。又，可減少零件數，因此可減低半導體裝置之成本。
(實施型態7)
作為起因於DC-DC轉換器之電流增大及高頻化之其他問題，有動作時之熱的問題。特別是於前述實施型態1、4~6之說明，係將半導體晶片5a、5b收容於同一封裝之構成，因此需要高散熱性。於本實施型態7，說明有關考慮到該散熱性之構成。
圖56係表示本實施型態7之封裝20E之剖面圖。在此，引線7b係相對於前述實施型態4~6之引線7b之情況而逆成形。於此構造，晶片墊7a1、7a2之背面(搭載半導體晶片5a、5b之面之相反側之面)露出於封裝6之上面，引線7b之背面(與布線基板之端子接合之接合面)側露出於封裝20E之搭載面。
又，圖57係表示將圖56之封裝20E搭載於布線基板30之狀態之一例之剖面圖。封裝20E之背面(搭載面)之引線7b係經由例如：鉛/錫焊錫等黏著材料38，而與布線基板30之端子接合。於封裝20E上面，亦即晶片墊7a1、7a2之背面，散熱片(散熱器)40係經由具有例如：矽膠等高熱傳導性之絕緣片39而接合。於此構成，在半導體晶片5a、5b所產生之熱係從半導體晶片5a、5b背面，經由晶片墊7a1、7a2而傳達至散熱片40而散熱。藉此，於1個封裝20E內具有2個半導體晶片5a、5b之構成，非絕緣型DC-DC轉換器1即使電流增大及高頻化，仍可獲得高散熱性。在此係例示風冷式散熱器，但亦可使用例如：具有可將冷卻流水流至散熱體之流路之液冷式散熱器。
(實施型態8)
於前述實施型態1~7，於同一半導體晶片之其他區域形成SBD及MOS，但於此構造，於SBD之形成區域無法配置MOS之形成區域，而且半導體晶片之尺寸固定，因此MOS面積將縮小內置SBD之部分，具有增大MOS導通損失的問題。
因此，於本實施型態8，例如：圖58所示，於功率MOS Q2之單位電晶體之形成區域LQR(活性區域)內，形成SBD D1。在此，於功率 MOS Q2之單位電晶體，將原本用以連接墊BP1與p型半導體區域12而形成之溝16，從主面穿至通道層(p型半導體區域12)而深入形成，於該溝16之底面，使溝16內之障壁金屬層10a及n-型磊晶層5LEP接觸，形成蕭特基接觸。又，墊BP1與p型半導體區域12之接觸係於溝16之側面，形成歐姆接觸。
藉由製成此構成，將無須於半導體晶片5b內確保SBD D1之專用區域，因此可不減少半導體晶片5b內之主面內之功率MOS Q2之形成區域面積而形成大面積之SBD。圖59係表示本實施型態8之損失分析之計算結果。於本構造，由於無法在計算上區別功率MOS Q2之寄生二極體(本體二極體)Dp與SBD D1，因此成為一體，但可知導通損失、驅動損失維持不變，本體二極體損失大幅減低。於其他區域形成SBD D1之情況之損失減低效果約0.2W程度，但於本實施型態8之情況，可實現約0.55W之損失減低。
然而，本發明者發現僅單純地加深溝16之構成，具有以下2個問題。
第一問題係有關障壁金屬層10a與p型半導體區域12之連接性。亦即，通常p型半導體區域12之雜質濃度為例如：~1017/cm3級，為了形成歐姆接觸，雜質濃度低。因此，無法實現墊BP1與p型半導體區域12之良好連接。
又，第二問題係由於n-型磊晶層5LEP之雜質濃度高，因此蕭特基接合部之漏洩電流大之問題。亦即於本實施型態8之構成，由於功率MOS Q2及SBD D1形成於相同區域，因此無法如前述實施型態1~7，形成深至功率MOS Q2之形成區域之n井，且無法實現於SBD D1之形成區域，使用低濃度之n-型磊晶層，形成蕭特基接觸之區分製作。在此，若於具有~1016/cm3程度之雜質濃度之n-型磊晶層，形成蕭特基接觸，SBD之漏洩電流將過大，漏洩電流所造成之損失變大。
因此，於本實施型態8，如圖58所示，應解決上述第一問題，於p型半導體區域12內，以相接於溝16之側面之方式，形成p+型半導體區域(第六半導體層)41，於該溝16之側面，進行障壁金屬層10a與p+型半導體區域41之歐姆接觸。藉此，可實現墊BP1與p型半導體區域12之良好連接。再者，p+型半導體區域41係形成為未到達通道(亦即溝14之側面)。若p+型半導體區域41形成至通道，將難以形成反轉層，而且臨限值電壓Vt增加，如本實施型態8，形成為未到達通道，可改善上述問題。
又，於本實施型態8，應解決上述第二問題，於溝(第二溝)16之底部側之障壁金屬層10a所相接之區域，形成n--型半導體區域(第五半導體區域)42，局部降低在蕭特基接合部之n-型磊晶層5LEP之雜質濃度。亦即，藉由n--型半導體區域42，於蕭特基接合部形成比n-型磊晶層5LEP高電阻之區域。藉此，可不增加開啟電阻而降低SBD D1之漏洩電流。
此情況，SBD D1亦可形成於圖11等所示之半導體晶片5b之功率MOS Q2之各單位電晶體格之形成區域LQR之複數條紋狀之閘極電極8G之所有鄰接之間，但亦可隔1個或隔複數線而配置。再者，墊BP1、6BP、閘極指叉6a、6b、閘極電極8G及閘極布線8L之平面佈局係與採用前述圖9~圖11、圖25~圖28所說明者相同。
其次，按照圖60之流程圖，藉由圖61~圖66說明本實施型態8之半導體晶片5b之製造方法之一例。又，為了比較，於圖67表示具有本發明者所檢討之SBD及MOS之半導體晶片之製造方法例之流程圖。
首先，如圖61所示，準備n+型矽單晶所組成之半導體晶圓(平面圓形狀之半導體基板5LS)，於其主面上，藉由磊晶法形成例如：2×1016/cm3程度之雜質濃度之n-型磊晶層5LEP(步驟200)。於發明者所檢討之圖67之步驟300，磊晶層之雜質濃度為例如：5×1015/cm3程度程 度之低濃度，於本實施型態8之方法，無須為了於功率MOS Q2之單位電晶體格之形成區域內形成SBD D1，而降低磊晶層5LEP之雜質濃度。
接著，於半導體晶圓之磊晶層5LEP，藉由離子注入法及其後之熱擴散處理，形成上述p井PWL1(步驟201)。於發明者所檢討之圖67，於p井PWL1之形成步驟201之前，為了減低功率MOS Q2之開啟電阻，於磊晶層5LEP形成深的n井NWL1(步驟300)。相對於此，於本實施型態8，如上述，由於無須降低磊晶層5LEP之雜質濃度，因此不需要深的n井，可刪除該形成步驟300。因此可縮短半導體晶片5b之製造時間，提高產出。
其後，於半導體晶圓之主面，形成到達磊晶層5LEP之溝14(步驟202)之後，於半導體晶圓主面之磊晶層5LEP表面，施加氧化處理，於包含溝14內之磊晶層5LEP之表面，形成閘極絕緣膜15(步驟203)。其後，於半導體晶圓之主面上，堆積例如：低電阻之多晶矽膜，並且埋入於溝14內。其後，藉由蝕刻法，將該多晶矽膜進行圖案化，於溝14內形成上述閘極電極8G，並且形成上述閘極布線8L(步驟204)。
其次，藉由在半導體晶圓之主面，將例如：硼等p型雜質進行離子注入並進行熱擴散，形成p型半導體區域12後(步驟205)，於半導體晶圓之主面，將例如：磷(P)或砷(As)等n型雜質進行離子注入並進行熱擴散，以便於閘極電極8G間之p型半導體區域12之上層，形成源極用之n+型半導體區域13(步驟206)。
接著，於半導體晶圓主面上，堆積絕緣層9a之後，於該絕緣層9a形成開口部9a1之後，如圖62所示，將該絕緣層9a作為離子注入遮罩，將例如：硼等p型雜質，離子注入於p型半導體區域12，並且於其後對於該雜質施加熱擴散處理，以便如圖63所示。於半導體晶圓之p型半導體區域12，形成平面上比上述開口部9a1寬廣之p+型半導體區 域41(步驟207)。於此熱擴散處理，宜使p+型半導體區域41不到達通道側(溝14之側面側)，以低溫施加短時間之熱處理。
其次，藉由將絕緣層9a作為蝕刻遮罩，將從該處露出之矽部分(亦即依序為n+型半導體區域13、p型半導體區域12、p+型半導體區域41、p型半導體區域12及n-型磊晶層5LEP之上部)進行蝕刻，如圖64所示，形成穿過p型半導體區域12，到達其下層之n-型磊晶層5LEP之溝16(步驟208)。從溝16之側面，露出上述p+型半導體區域41。
接著，如圖65所示，藉由將絕緣層9a作為離子注入遮罩，於溝16之底部將p型雜質進行離子注入，局部降低溝16底部之n-型磊晶層5LEP之n型雜質濃度。其後，藉由施加熱擴散處理，於溝16之底部區域，形成n--型半導體區域42(步驟209)。再者，於本實施型態8，由於已形成p+型半導體區域41，因此不需要圖67之p+選擇離子擴散步驟301。
其後，藉由對於絕緣層9a施加蝕刻處理，如圖66所示地擴大開口部9a1之開口寬。此階段之開口部9a1為上述接觸孔洞11c，從其底面露出n+型半導體區域13。接著，如圖58所示，從下層依序堆積障壁金屬層10a、金屬層10b(步驟210、211)，藉由蝕刻法將此進行圖案化，以便形成上述墊BP1、6BP及閘極指叉6a、6b。其後，於半導體晶圓背面，藉由蒸鍍例如：金(Au)，以形成背面電極LBE(步驟212)。此以後，經過經常之步驟，從半導體晶圓切出各個半導體晶片，製造出半導體晶片。
以上根據實施型態，具體地說明由本發明者所實現之發明，但本發明不限於前述實施型態，當然可在不脫離其要旨之範圍內進行各種變更。
例如：於前述實施型態，例示扁平封裝構造作為封裝構造，但不限於此，亦可採用例如：BGA(Ball Grid Array：球柵陣列)封裝構 造。
於以上說明，說明有關將本發明者所實現之發明，適用於其背景之利用領域之CPU或DSP之驅動用電源電路之情況，但不限於其，可進行各種適用，亦可適用於例如：其他電路之驅動用電源電路。
[產業上之利用可能性]
本發明可適用於半導體裝置之製造業。
5b‧‧‧半導體晶片
6a‧‧‧閘極指叉
6b‧‧‧閘極指叉
6BP‧‧‧接合墊
7E‧‧‧外部電極
BP1‧‧‧墊
D1‧‧‧蕭特基障壁二極體之形成區域
SDR‧‧‧蕭特基障壁二極體
WA‧‧‧金屬線

Claims (12)

  1. 一種半導體裝置，其包含半導體基板者，該半導體基板具有一對長邊及一對短邊，且包含形成有複數個功率MOSFET之複數個第一區域及形成有蕭特基障壁二極體之第二區域；其中前述複數個功率MOSFET之各個包含：閘極電極、源極區域及汲極區域；前述蕭特基障壁二極體包含：陽極電極及陰極電極；於前述半導體基板上，形成有：包含第一金屬層之第一閘極指叉，其係與前述閘極電極電性連接，且沿著前述一對長邊及前述一對短邊而延伸，並於俯視時圍著前述第一區域及前述第二區域，及包含前述第一金屬層之複數個第二閘極指叉，其係自前述第一閘極指叉之沿著前述一對長邊之各個而延伸的部分朝向前述第二區域延伸；藉由前述第一閘極指叉、前述第二閘極指叉、及前述第二區域而圍著前述複數個第一區域之各個；於前述複數個第一區域上及前述第二區域上，形成有與前述源極區域及前述陽極電極電性連接之第二金屬層；前述第二區域係以沿前述一對長邊之方向的長度比沿前述一對短邊之方向的長度長之方式配置。
  2. 如請求項1之半導體裝置，其中前述複數個第一區域係配置在沿前述一對長邊之方向。
  3. 如請求項2之半導體裝置，其中前述複個第一區域係於沿著前述一對短邊之方向，配置為至少2行，且配置為2行之前述複數個第一區域係藉由前述第二區域而被分 斷。
  4. 如請求項1~3任一項之半導體裝置，其中前述複數個功率MOSFET之前述閘極電極係分別埋入在形成於前述半導體基板之溝內而形成。
  5. 如請求項4之半導體裝置，其中前述複數個功率MOSFET之前述閘極電極係分別以沿前述一對長邊之方向的長度比沿前述一對短邊之方向的長度長之方式而形成。
  6. 如請求項5之半導體裝置，其中前述第一金屬層及前述第二金屬層分別包含鋁。
  7. 如請求項6之半導體裝置，其中前述閘極電極包含多晶矽膜。
  8. 一種半導體裝置，其係包括半導體基板者，該半導體基板具有一對長邊及一對短邊，且包含：各自形成有功率MOSFET之第一MOS區域和第二MOS區域、及形成有蕭特基障壁二極體之二極體區域；其中：前述功率MOSFET包含：閘極電極、源極區域及汲極區域；前述蕭特基障壁二極體包含：陽極電極及陰極電極；在沿著前述一對短邊之方向，配置為前述第一MOS區域、前述二極體區域、及前述第二MOS區域之順序；於前述半導體基板上形成有：包含第一金屬層之第一閘極指叉，其與前述閘極電極電性連接，且沿著前述一對長邊及前述一對短邊而延伸，並於俯視時圍著前述第一MOS區域、前述第二MOS區域及前述二極體區域，包含前述第一金屬層之複數個第二閘極指叉，其自前述第一閘極指叉之沿著前述一對長邊之一者而延伸的部分，向沿著前述一對短邊之方向延伸，及 包含前述第一金屬層之複數個第三閘極指叉，其自前述第一閘極指叉之沿著前述一對長邊之另一者而延伸的部分，向沿前述一對短邊之方向延伸；前述第一MOS區域係配置於前述複數個第二閘極指叉間；前述第二MOS區域係配置於前述複數個第三閘極指叉間；於前述第一MOS區域上、前述第二MOS區域上及前述二極體區域上，形成有與前述源極區域及前述陽極電極電性連接之第二金屬層；前述二極體區域係以沿前述一對長邊之方向的長度比沿前述一對短邊之方向的長度長之方式配置。
  9. 如請求項8之半導體裝置，其中前述功率MOSFET之前述閘極電極係埋入在形成於前述半導體基板之溝內而形成。
  10. 如請求項9之半導體裝置，其中前述閘極電極係延伸於沿前述一對長邊之方向。
  11. 如請求項8之半導體裝置，其中前述第一金屬層及前述第二金屬層分別包含鋁。
  12. 如請求項11之半導體裝置，其中前述閘極電極包含多晶矽膜。
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US8592904B2 (en) 2013-11-26
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US20170005089A1 (en) 2017-01-05
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US20060022298A1 (en) 2006-02-02
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