JP4895104B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4895104B2 JP4895104B2 JP2006186181A JP2006186181A JP4895104B2 JP 4895104 B2 JP4895104 B2 JP 4895104B2 JP 2006186181 A JP2006186181 A JP 2006186181A JP 2006186181 A JP2006186181 A JP 2006186181A JP 4895104 B2 JP4895104 B2 JP 4895104B2
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Description
Va =Vout −Vgs4 −Vgs5 ……(1)
Vb =Va +Vgs7 +Vgs6 ……(2)
Ib4=Ib3/2の時、Vgs4 =Vgs7 、Vgs5 =Vgs6となるので上記式(1)(2)により、Vo=Vbになる。ここで、Vgs4 〜Vgs7 は、MOSFETQ4〜Q7のゲート,ソース電圧である。
Claims (15)
- 第1半導体チップと、
第2半導体チップと、
第3半導体チップとが1つのパッケージに搭載され、
上記第1半導体チップは、第1パワーMOSFETであり、
上記第2半導体チップは、第2パワーMOSFETであり、
上記第3半導体チップは、
上記第1、第2パワーMOSFETを駆動する駆動回路と、
上記第1、第2パワーMOSFETで形成された出力電流が流れるようにされたインダクタとキャパシタで形成された直流電圧が、所望電圧になるようなスイッチング制御信号を生成し、上記駆動回路に出力する制御回路と、
上記駆動回路の動作に必要とされる第1内部電圧を形成する第1電源回路と、
上記制御回路の動作に必要とされる第2内部電圧を形成する第2電源回路とを含み、
上記第1パワーMOSFETは、第1電源端子の入力電圧から上記インダクタに流す電流を形成し、
上記第1、第2電源回路は、上記入力電圧を降圧してそれぞれ上記第1、第2内部電圧を形成する半導体装置。 - 請求項1において、
上記第1内部電圧は、上記第2内部電圧よりも高く設定される半導体装置。 - 請求項1において、
上記第1パワーMOSFETは、上記第1電源端子から上記インダクタに向けて電流を流すハイサイドMOSFETであり、
上記第2パワーMOSFETは、上記第1パワーMOSFETがオフ状態のときにオン状態となって回路の接地電位から上記インダクタに向けて電流を流すロウサイドMOSFETである半導体装置。 - 請求項3において、
上記第3半導体チップは、CMOS素子構造とされる半導体装置。 - 請求項4において、
電圧検出回路と、
上記スイッチング制御信号を形成するために用いられる基準電圧を形成する基準電圧発生回路と、
上記電圧検出回路及び基準電圧発生回路に対応された第3電源端子とを更に有する半導体装置。 - 請求項5において、
上記第1、第2パワーMOSFETは、電流経路が半導体チップの縦方向とされる縦型MOS構造であり、
上記半導体チップは、上記縦型MOS構造のセルの複数個から構成された第1パワーMOSFETと、上記第1パワーMOSFETに対してセル数が1/Nにされ、上記第1パワーMOSFETとゲート及びドレインが半導体基板上でそれぞれ共通にされたセンスMOSFETを有し、
上記制御回路は、上記センスMOSFETに流れる電流を用いて上記スイッチング制御信号を形成する半導体装置。 - 請求項6において、
上記第2パワーMOSFETは、上記縦型MOS構造のセルの複数個から構成され、
上記複数個のセルの素子形成領域内に、ソース−ドレイン間に設けられたSBDを有することを特徴とする半導体装置。 - 請求項7において、
上記スイッチング制御信号は、PWM信号であり、
上記制御回路は、
上記センスMOSFETに流れる電流を用いて生成された第1帰還信号と、上記インダクタとキャパシタで形成された直流電圧に対応した第2帰還信号とを用いて上記PWM信号を形成する半導体装置。 - 請求項8において、
上記制御回路は、
発振回路と、
パルス発生回路と、
上記発振回路の出力信号に対応した周期的信号を上記パルス発生回路に伝える第1信号伝達経路と、
上記発振回路の出力信号に対応した周期的信号を第1外部端子に伝える第2信号伝達経路と、
上記第1外部端子から入力された周期的信号を上記パルス発生回路に伝える第3信号伝達経路とを更に有し、
制御信号により上記第1信号伝達経路と上記第2信号伝達経路とを通して上記発振回路の出力信号に対応した周期的信号を上記パルス発生回路に伝える第1モードと、上記第3信号伝達経路を通して上記第1外部端子から入力された周期的信号を上記パルス発生回路に伝える第2モードとを備える半導体装置。 - 請求項9において、
上記第3信号伝達経路は、上記制御信号に対応して上記第2モードのときに上記第1外部端子から入力された周期的信号を同相で伝達する動作と、反転させて伝達する動作とを有する半導体装置。 - 請求項10において、
上記制御回路は、
上記第2帰還信号と基準電圧とを受けるエラーアンプと、
電圧比較回路と、
第3外部端子とを更に有し、
上記電圧比較回路は、エラーアンプの出力信号又は上記第3外部端子から供給された入力電圧のうちいずれか大きい方の電圧に対応した電圧と上記第1帰還信号とを比較して上記PWM信号を生成する半導体装置。 - 請求項11において、
上記第1パワーMOSFETと第2パワーMOSFETは、そのスイッチング制御により形成された上記直流電圧の最大電流が約20Aを含むようなサイズで形成される半導体装置。 - 請求項3において、
上記第1半導体チップと上記第3半導体チップが搭載基板上の約半分の四角の領域に並んで配置され、
上記第2半導体チップは、上記搭載基板上の残り約半分の四角の領域に配置された半導体装置。 - 請求項13において、
上記搭載基板の周辺部に外部端子に対応した複数個のパッドが設けられ、
上記第3半導体チップとの接続が行われる搭載基板のパッドは、上記第1半導体チップ又は第2半導体チップに対応した搭載基板の周辺部に設けられた第1パッドを含む半導体装置。 - 請求項14において、
上記第1パッドは、上記第1パワーMOSFETと第2パワーMOSFETとが接続される出力ノードと接続され、それと隣接してブートストラップ容量が接続される昇圧側の第2パッドが配置される半導体装置。
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