WO2016157394A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2016157394A1 WO2016157394A1 PCT/JP2015/060024 JP2015060024W WO2016157394A1 WO 2016157394 A1 WO2016157394 A1 WO 2016157394A1 JP 2015060024 W JP2015060024 W JP 2015060024W WO 2016157394 A1 WO2016157394 A1 WO 2016157394A1
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- semiconductor chip
- bonding material
- semiconductor
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- die pad
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used for, for example, a semiconductor device in which a plurality of semiconductor chips are arranged and packaged, and a manufacturing method thereof.
- a semiconductor device in the form of a semiconductor package can be manufactured by mounting a semiconductor chip on a die pad, electrically connecting pad electrodes and leads of the semiconductor chip via wires, and sealing them with resin.
- Patent Document 1 describes a technology related to a multi-chip package in which a power semiconductor chip and a logic chip are mounted on a substrate.
- the semiconductor device has the first semiconductor chip mounted on the conductive chip mounting portion via the first bonding material having insulation, and the second bonding material having conductivity.
- This is a resin-encapsulated semiconductor device having a second semiconductor chip mounted thereon.
- the first length of the portion covered with the first bonding material on the first side formed by intersecting the first side surface and the second side surface of the first semiconductor chip is the second length.
- the second side formed by intersecting the third side surface and the fourth side surface of the semiconductor chip is longer than the second length of the portion covered with the second bonding material.
- a method for manufacturing a semiconductor device includes: (a) mounting a first semiconductor chip on a conductive chip mounting portion via a first bonding material having an insulating property; A step of mounting a second semiconductor chip via a second bonding material having a property; (b) a sealing body for sealing at least a part of the first semiconductor chip, the second semiconductor chip, and the chip mounting portion; Forming a step.
- the first length of the portion covered with the first bonding material on the first side formed by intersecting the first side surface and the second side surface of the first semiconductor chip is the second length.
- the second side formed by intersecting the third side surface and the fourth side surface of the semiconductor chip is longer than the second length of the portion covered with the second bonding material.
- the reliability of the semiconductor device can be improved.
- FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;
- FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;
- FIG. 14 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13;
- FIG. 15 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14;
- It is a process flow figure which shows the detail of a die bonding process. It is a process flow figure which shows the detail of a die bonding process. It is a process flow figure which shows the detail of a die bonding process. It is a process flow figure which shows the detail of a die bonding process. It is a process flow figure which shows the detail of a die bonding process.
- FIG. 21 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 20;
- FIG. 22 is a cross-sectional view of the same semiconductor device as in FIG. 21 during a manufacturing step.
- FIG. 22 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 21;
- FIG. 24 is a cross-sectional view of the same semiconductor device as in FIG. 23 during a manufacturing step;
- FIG. 24 is a plan view of the semiconductor device in manufacturing process, following FIG. 23;
- FIG. 26 is a cross-sectional view of the same semiconductor device as in FIG. 25 during a manufacturing step;
- FIG. 26 is a plan view of the semiconductor device during a manufacturing step following that of FIG.
- FIG. 28 is a cross-sectional view of the same semiconductor device as in FIG. 27 during a manufacturing step. It is a top view in the manufacturing process of the semiconductor device which is one embodiment.
- FIG. 30 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 29; It is a circuit diagram of the semiconductor device which is one embodiment. It is principal part sectional drawing of the semiconductor chip used for the semiconductor device which is one Embodiment. It is sectional drawing of the semiconductor device of an examination example. 1 is an enlarged plan view of a part of a semiconductor device according to an embodiment; 1 is an enlarged plan view of a part of a semiconductor device according to an embodiment; It is a perspective view which expands and shows a part of semiconductor device which is one embodiment.
- FIG. 1 is an enlarged cross-sectional view illustrating a part of a semiconductor device according to an embodiment
- 1 is an enlarged cross-sectional view illustrating a part of a semiconductor device according to an embodiment
- It is a table
- hatching may be omitted even in a cross-sectional view for easy understanding of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
- FIG. 1 is a top view of a semiconductor device PKG according to an embodiment of the present invention
- FIGS. 2 to 4 are plan perspective views of the semiconductor device PKG
- FIG. 5 is a bottom view of the semiconductor device PKG
- FIG. 6 to 8 are cross-sectional views of the semiconductor device PKG.
- FIG. 2 shows a plan perspective view of the upper surface side of the semiconductor device PKG when the sealing portion MR is seen through.
- FIG. 3 is a plan perspective view of the upper surface side of the semiconductor device PKG when the wire BW is further seen through (omitted) in FIG.
- FIG. 4 is a plan perspective view of the upper surface side of the semiconductor device PKG when the semiconductor chips CP1 and CP2 are further seen through (omitted) in FIG. 1 to 4, the direction of the semiconductor device PKG is the same. 2 to 4, the position of the outer periphery of the sealing portion MR is indicated by a dotted line.
- the cross section of the semiconductor device PKG at the position of the AA line in FIGS. 1, 2 and 5 substantially corresponds to FIG. 6, and at the position of the BB line in FIGS.
- the cross section of the semiconductor device PKG substantially corresponds to FIG. 7, and the cross section of the semiconductor device PKG at the position of the line CC in FIGS. 1, 2 and 5 substantially corresponds to FIG.
- FIG. 9 is a partially enlarged plan perspective view in which a part of FIG. 2 is enlarged.
- the semiconductor device (semiconductor package) PKG of this embodiment shown in FIGS. 1 to 9 is a semiconductor device in the form of a resin-encapsulated semiconductor package, and here is a semiconductor device in the form of a QFP (Quad Flat Package). .
- QFP Quad Flat Package
- the semiconductor device PKG of the present embodiment shown in FIGS. 1 to 9 includes semiconductor chips CP1 and CP2, a die pad DP on which the semiconductor chips CP1 and CP2 are mounted, a plurality of leads LD formed of a conductor, a semiconductor
- Each of the chips CP1 and CP2 includes a plurality of wires BW that electrically connect the plurality of pad electrodes P1 and P2 and the plurality of leads LD, and a sealing portion MR that seals them.
- the sealing portion (sealing resin portion, sealing body) MR as a sealing body is made of, for example, a resin material such as a thermosetting resin material, and may include a filler.
- the sealing portion MR can be formed using an epoxy resin containing a filler.
- a biphenyl thermosetting resin to which a phenolic curing agent, silicone rubber, filler, or the like is added is used as a material for the sealing portion MR for the purpose of reducing stress. May be.
- the sealing portion MR includes an upper surface (front surface) MRa that is one main surface, a lower surface (back surface, bottom surface) MRb that is a main surface opposite to the upper surface MRa, and side surfaces MRc1 and MRc2 that intersect the upper surface MRa and the lower surface MRb. , MRc3, and MRc4 (see FIG. 1 and FIGS. 5 to 8). That is, the appearance of the sealing portion MR is a thin plate surrounded by the upper surface MRa, the lower surface MRb, and the side surfaces MRc1, MRc2, MRc3, MRc4. In plan view, each side surface MRc1, MRc2, MRc3, MRc4 of the sealing part MR can also be regarded as a side of the sealing part MR.
- the planar shape of the upper surface MRa and the lower surface MRb of the sealing portion MR is formed, for example, in a rectangular shape, and the corners of the rectangle (planar rectangle) can be rounded. In addition, an arbitrary corner can be dropped from the four corners of the rectangle (planar rectangle).
- the planar shapes of the upper surface MRa and the lower surface MRb of the sealing portion MR are rectangular, the planar shape (outer shape) intersecting with the thickness of the sealing portion MR is rectangular (square).
- the side surface MRc1 and the side surface MRc3 face each other
- the side surface MRc2 and the side surface MRc4 face each other
- the side surface MRc1 and the side surfaces MRc2 and MRc4 intersect each other.
- the side surface MRc3 and the side surfaces MRc2 and MRc4 intersect each other.
- the plurality of leads (lead portions) LD are made of a conductor, and are preferably made of a metal material such as copper (Cu) or a copper alloy.
- Each of the plurality of leads LD is sealed in the sealing portion MR, and the other part protrudes from the side surface of the sealing portion MR to the outside of the sealing portion MR.
- a portion of the lead LD positioned in the sealing portion MR is referred to as an inner lead portion
- a portion of the lead LD positioned outside the sealing portion MR is referred to as an outer lead portion.
- the semiconductor device PKG of the present embodiment has a structure in which a part (outer lead part) of each lead LD protrudes from the side surface of the sealing part MR.
- the following description is based on this structure.
- a configuration in which each lead LD hardly protrudes from the side surface of the sealing portion MR and a part of each lead LD is exposed on the lower surface MRb of the sealing portion MR QFN type configuration. Etc. can also be adopted.
- the plurality of leads LD include a plurality of leads LD disposed on the side surface MRc1 side of the sealing portion MR, a plurality of leads LD disposed on the side surface MRc2 side of the sealing portion MR, and a side surface MRc3 side of the sealing portion MR. And a plurality of leads LD arranged on the side surface MRc4 side of the sealing portion MR.
- Each outer lead portion of the plurality of leads LD arranged on the side surface MRc1 side of the sealing portion MR protrudes from the side surface MRc1 of the sealing portion MR to the outside of the sealing portion MR. Further, each outer lead portion of the plurality of leads LD disposed on the side surface MRc2 side of the sealing portion MR protrudes from the side surface MRc2 of the sealing portion MR to the outside of the sealing portion MR. Further, each outer lead portion of the plurality of leads LD disposed on the side surface MRc3 side of the sealing portion MR protrudes from the side surface MRc3 of the sealing portion MR to the outside of the sealing portion MR. Further, each outer lead portion of the plurality of leads LD disposed on the side surface MRc4 side of the sealing portion MR protrudes from the side surface MRc4 of the sealing portion MR to the outside of the sealing portion MR.
- each lead LD is bent so that the lower surface in the vicinity of the end of the outer lead portion is positioned substantially on the same plane as the lower surface MRb of the sealing portion MR.
- the outer lead portion of the lead LD functions as an external connection terminal portion (external terminal) of the semiconductor device PKG.
- the die pad (chip mounting portion, tab) DP is a chip mounting portion on which the semiconductor chip CP1 and the semiconductor chip CP2 are mounted.
- the planar shape of the die pad DP is formed in a rectangular shape, for example.
- the semiconductor chip CP1 and the semiconductor chip CP2 are arranged side by side on the die pad DP, the sealing portion MR seals a part of the die pad DP, and the plurality of leads LD are arranged around the die pad DP. .
- the die pad DP includes a side (side surface) DP1 on the side surface MRc1, a side (side surface) DP2 on the side surface MRc2, a side (side surface) DP3 on the side surface MRc3, and a side (side surface) DP4 on the side surface MRc4 side.
- a side (side surface) DP1 of the die pad DP is a side (side surface) along the side surface MRc1 of the sealing portion MR
- a side (side surface) DP2 of the die pad DP is a side (side surface) along the side surface MRc2 of the sealing portion MR.
- the side (side surface) DP3 of the die pad DP is the side (side surface) along the side surface MRc3 of the sealing portion MR, and the side (side surface) DP4 of the die pad DP is along the side surface MRc4 of the sealing portion MR. It is a side (side).
- the plurality of leads LD arranged on the side surface MRc1 side of the sealing portion MR are arranged (arranged) along the side DP1 of the die pad DP, and the plurality of leads LD arranged on the side surface MRc2 side of the sealing portion MR are Arranged (arranged) along the side DP2 of the die pad DP.
- the plurality of leads LD disposed on the side surface MRc3 side of the sealing portion MR are disposed (arranged) along the side DP3 of the die pad DP, and the plurality of leads LD disposed on the side surface MRc4 side of the sealing portion MR.
- a plurality of leads LD are arranged (arranged) along the side surface MRc1 of the sealing portion MR.
- a plurality of leads LD are arranged (arranged) along the side surface MRc2 of the sealing portion MR.
- a plurality of leads LD are arranged (arranged) along the side surface MRc3 of the sealing portion MR between the side DP3 of the die pad DP and the side surface MRc3 of the sealing portion MR.
- a plurality of leads LD are arranged (arranged) along the side surface MRc4 of the sealing portion MR.
- the lower surface (back surface) of the die pad DP is exposed at the lower surface MRb of the sealing portion MR.
- the die pad DP is not exposed on the upper surface MRa of the sealing portion MR.
- the die pad DP is made of a conductor and is preferably made of a metal material such as copper (Cu) or a copper alloy. It is more preferable that the die pad DP and the plurality of leads LD constituting the semiconductor device PKG are formed of the same material (the same metal material). As a result, a lead frame in which the die pad DP and the plurality of leads LD are coupled can be easily manufactured, and the semiconductor device PKG using the lead frame can be easily manufactured.
- a metal material such as copper (Cu) or a copper alloy.
- the suspension leads TL are integrally formed at the four corners of the rectangle that constitutes the planar shape of the die pad DP.
- Each suspension lead TL is integrally formed with the die pad DP using the same material as the die pad DP.
- a suspension lead TL is integrally formed at each of the four corners of the outer edge of the die pad DP, and the end of each suspension lead TL opposite to the side connected to the die pad DP is a planar rectangular sealing portion MR.
- the inside of the sealing portion MR extends until reaching the four corners (corner portions).
- the suspension lead TL has a portion protruding from the sealing portion MR after the formation of the sealing portion MR, and cut surfaces (end surfaces) generated by cutting the suspension lead TL are exposed at the four corner side surfaces of the sealing portion MR. ing.
- the semiconductor chip CP1 On the upper surface (main surface) of the die pad DP, the semiconductor chip CP1 is mounted with its front surface (main surface, upper surface) facing up and its back surface (lower surface) facing the die pad DP ( FIG. 2, FIG. 3, FIG. 6, FIG. 7 and FIG. 9).
- the semiconductor chip CP2 On the upper surface (main surface) of the die pad DP, the semiconductor chip CP2 is mounted with its front surface (main surface, upper surface) facing up and its back surface (lower surface) facing the die pad DP. (See FIGS. 2, 3, 6, 8, and 9).
- the region where the semiconductor chip CP1 is mounted and the region where the semiconductor chip CP2 is mounted are separated from each other. Therefore, the semiconductor chip CP1 and the semiconductor chip CP2 are separated from each other in plan view. is doing.
- the semiconductor chip CP1 and the semiconductor chip CP2 are arranged side by side on the upper surface of the die pad DP. That is, the semiconductor chip CP1 and the semiconductor chip CP2 are not stacked on each other, and are arranged on the upper surface of the die pad DP so as to be separated from each other.
- the planar dimensions (planar area) of the die pad DP are larger than the planar dimensions (planar areas) of the semiconductor chips CP1 and CP2, and the semiconductor chip CP1 and the semiconductor chip CP2 are included in the upper surface of the die pad DP in plan view. However, the semiconductor chip CP1 and the semiconductor chip CP2 do not overlap.
- the back surface of the semiconductor chip CP1 is bonded and bonded to the upper surface of the die pad DP via a bonding material (bonding material layer, adhesive layer) BD1, and the back surface of the semiconductor chip CP2 is bonded to the bonding material (bonding material layer, adhesive). Layer) It is bonded and bonded to the upper surface of the die pad DP via the BD2 (see FIGS. 6 to 8).
- the semiconductor chips CP1 and CP2 are sealed in the sealing portion MR and are not exposed from the sealing portion MR.
- the semiconductor chip CP1 has a back electrode BE formed on the back surface (main surface bonded to the die pad DP) (see FIGS. 6 and 7). Therefore, the bonding material BD1 for bonding the semiconductor chip CP1 has conductivity, and the back electrode BE of the semiconductor chip CP1 is bonded and fixed to the die pad DP via the conductive bonding material BD1. And electrically connected. Therefore, a desired potential can be supplied from the die pad DP to the back electrode BE of the semiconductor chip CP1 through the conductive bonding material BD1.
- the back electrode BE of the semiconductor chip CP1 is electrically connected to the drain of a power MOSFET (corresponding to a power MOSFET Q1 described later) formed in the semiconductor chip CP1.
- the bonding material BD1 for example, a conductive paste type bonding material (adhesive) such as silver (Ag) paste can be suitably used. Further, as the conductive paste type bonding material for the bonding material BD1, a thermosetting bonding material can be suitably used. However, in the manufactured semiconductor device PKG, the bonding material BD1 is already cured.
- a silver (Ag) plating layer GM is formed in a region where the semiconductor chip CP1 is mounted.
- the silver plating layer GM is formed on a part of the upper surface of the die pad DP, and the semiconductor chip CP1 is included in the silver plating layer GM in plan view.
- the semiconductor chip CP1 is mounted on and bonded to the silver plating layer GM on the upper surface of the die pad DP via a conductive bonding material BD1. That is, the back electrode BE of the semiconductor chip CP1 is bonded and fixed to the silver plating layer GM on the upper surface of the die pad DP via the conductive bonding material BD1, and is electrically connected. Therefore, the back electrode BE of the semiconductor chip CP1 is electrically connected to the die pad DP via the conductive bonding material BD1 and the silver plating layer GM.
- the silver plating layer GM can be omitted. If the silver plating layer GM is not provided, the semiconductor is disposed on the die pad DP made of copper (Cu) or copper (Cu) alloy via the bonding material BD1. The chip CP1 is mounted. However, it is more preferable to provide a silver plating layer GM on a part of the upper surface of the die pad DP and mount the semiconductor chip CP1 on the silver plating layer GM via the bonding material BD1. When an oxide layer is formed on the upper surface of the die pad DP made of copper (Cu) or a copper (Cu) alloy, and the semiconductor chip CP1 is mounted on the region where the oxide layer is formed via the bonding material BD1.
- the connection resistance between them may be increased.
- the surface of the silver plating layer GM is less oxidized than the surface of the die pad DP, a silver plating layer GM is provided on the upper surface of the die pad DP, and a semiconductor is bonded to the silver plating layer GM via the bonding material BD1. If the chip CP1 is mounted, the back electrode BE of the semiconductor chip CP1 and the die pad DP can be accurately electrically connected with low resistance.
- the bonding material BD2 for bonding the semiconductor chip CP2 does not have conductivity but has insulation. That is, the bonding material BD2 is made of an insulating bonding material. Thereby, the die pad DP and the semiconductor chip CP2 are insulated via the insulating bonding material BD2, and the potential supplied from the die pad DP to the back surface electrode BE of the semiconductor chip CP1 via the conductive bonding material BD1 It is no longer supplied to the back surface of the chip CP2.
- an insulating paste-type bonding material (adhesive) can be suitably used.
- a thermosetting bonding material can be suitably used as the insulating paste type bonding material for the bonding material BD2 is already cured.
- the silver plating layer GM is not formed in the region where the semiconductor chip CP2 is mounted on the upper surface of the die pad DP. Therefore, the semiconductor chip CP2 is mounted and bonded via the insulating bonding material BD2 on the upper surface of the die pad DP in the region where the silver plating layer GM is not formed.
- the die pad DP On the upper surface of the die pad DP, it is also possible to provide a silver plating layer such as a silver plating layer GM in the region where the semiconductor chip CP2 is mounted, and to mount the semiconductor chip CP2 on the silver plating layer via the bonding material BD2. It is. However, the upper surface of the die pad DP is not provided with a silver plating layer such as the silver plating layer GM in the region where the semiconductor chip CP2 is mounted, and the bonding material is formed on the upper surface of the die pad DP in the region where the silver plating layer is not formed. It is more preferable to mount the semiconductor chip CP2 via the BD2.
- the semiconductor chip CP2 it is more preferable to mount the semiconductor chip CP2 on the exposed surface of the die pad DP made of copper or copper alloy via the bonding material BD2. This is because the adhesion (adhesion strength) between the sealing part MR and the die pad DP is higher than the adhesion (adhesion strength) between the silver plating layer GM and the sealing part MR. For the semiconductor chip CP2 that does not need to be electrically connected to the die pad DP, high adhesion between the sealing portion MR and the die pad DP can be ensured by not providing the silver plating layer GM in the mounting region.
- the semiconductor chip CP1 that needs to be electrically connected to the die pad DP is provided with a silver plating layer GM in the mounting region, thereby providing an electrical connection between the back electrode BE of the semiconductor chip CP1 and the die pad DP. Reliability can be improved.
- the die pad DP can also have a function as a heat sink for dissipating heat generated in the semiconductor chip CP1.
- the heat generated in the semiconductor chip CP1 is conducted to the die pad DP through the bonding material BD1, and can be dissipated outside the semiconductor device PKG from the lower surface (back surface) of the die pad DP exposed from the sealing portion MR. Since the bonding material BD1 interposed between the semiconductor chip CP1 and the die pad DP has conductivity, the thermal conductivity is higher than that of the insulating bonding material BD2 interposed between the semiconductor chip CP2 and the die pad DP. The rate is high.
- the heat generation amount of the semiconductor chip CP2 is smaller than the heat generation amount of the semiconductor chip CP1.
- the semiconductor chip CP1 includes a power transistor through which a large current flows, whereas the semiconductor chip CP2 does not include such a power transistor and flows through the semiconductor chip CP1. This is because the current flowing through the semiconductor chip CP2 is smaller than the current. For this reason, even if the bonding material BD2 interposed between the semiconductor chip CP2 and the die pad DP has an insulating property and the thermal conductivity is lowered, problems related to the heat generation of the semiconductor chip CP2 hardly occur.
- the semiconductor chips CP1 and CP2 are formed by, for example, forming various semiconductor elements or semiconductor integrated circuits on the main surface of a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then separating the semiconductor substrate into each semiconductor chip by dicing or the like. Manufactured.
- the semiconductor chips CP1 and CP2 have a rectangular (quadrangle) planar shape that intersects their thickness.
- the semiconductor chip CP1 is an IPD (Intelligent Power Device) chip. Therefore, although details will be described later, the semiconductor chip CP1 has a power transistor (corresponding to a power MOSFET Q1 described later) and a control circuit (corresponding to a control circuit CLC described later) for controlling the power transistor.
- the semiconductor chip CP2 is a microcomputer chip. Therefore, the semiconductor chip CP2 includes a circuit that controls the semiconductor chip CP1 (particularly, the control circuit CLC of the semiconductor chip CP1), and includes, for example, an arithmetic circuit (CPU) and a memory circuit.
- the semiconductor chip CP2 can be used as a control chip (control semiconductor chip) for controlling the semiconductor chip CP1. That is, the semiconductor chip CP2 is a semiconductor chip for controlling the semiconductor chip CP1.
- the semiconductor chip CP1 has a larger planar area than the semiconductor chip CP2, and the difference in the planar area is as follows. That is, it is desirable to make the outer size of the semiconductor chip CP2 as small as possible in consideration of the overall dimensions of the semiconductor device PKG.
- a power transistor is formed in the semiconductor chip CP1, and in this power transistor, it is desired to reduce the on-resistance generated in the transistor as much as possible. The on-resistance can be reduced by widening the channel width of a plurality of unit transistor cells that constitute the power transistor. For this reason, the outer size of the semiconductor chip CP1 is larger than the outer size of the semiconductor chip CP2.
- a plurality of pad electrodes (pads, bonding pads, terminals) P1 are formed on the surface (main surface, upper surface) of the semiconductor chip CP1 (see FIGS. 2, 3, 6, 7, and 9).
- a plurality of pad electrodes (pads, bonding pads, terminals) P2 are formed on the surface (main surface, upper surface) of the semiconductor chip CP2 (see FIGS. 2, 3, 6, 8, and 9). ).
- the “pad electrode” may be simply referred to as “pad”.
- the main surface on the side on which the plurality of pad electrodes P1 are formed is called the surface of the semiconductor chip CP1 among the two main surfaces positioned on the opposite sides, and is opposite to this surface.
- the main surface facing the die pad DP is referred to as the back surface of the semiconductor chip CP1.
- the main surface on the side where the plurality of pad electrodes P2 are formed out of the two main surfaces located on the opposite sides is called the surface of the semiconductor chip CP2, and is opposite to this surface.
- the main surface facing the die pad DP is referred to as the back surface of the semiconductor chip CP2.
- the surface of the semiconductor chip CP1 has a rectangular planar shape (see FIGS. 3 and 9). Therefore, the semiconductor chip CP1 has four side surfaces SM1, SM2, SM3, and SM4 that connect the front surface of the semiconductor chip CP1 and the back surface of the semiconductor chip CP1. That is, the semiconductor chip CP1 has a surface that is one main surface, a back surface that is a main surface opposite to the front surface, and side surfaces SM1, SM2, SM3, and SM4 that intersect the front surface and the back surface. .
- the side surface SM1 and the side surface SM3 are located on opposite sides
- the side surface SM2 and the side surface SM4 are located on opposite sides
- the side surface SM1 and the side surface SM3 are parallel to each other
- the side surface SM4 is parallel to each other
- the side surface SM1 is orthogonal to the side surfaces SM2 and SM4
- the side surface SM3 is orthogonal to the side surfaces SM2 and SM4.
- the side surfaces SM1, SM2, SM3, and SM4 of the semiconductor chip CP1 can be regarded as the sides of the semiconductor chip CP1.
- the surface of the semiconductor chip CP2 has a rectangular planar shape (see FIGS. 3 and 9). Therefore, the semiconductor chip CP2 has four side surfaces SM5, SM6, SM7, and SM8 that connect the front surface of the semiconductor chip CP2 and the back surface of the semiconductor chip CP2. That is, the semiconductor chip CP2 has a surface that is one main surface, a back surface that is a main surface opposite to the front surface, and side surfaces SM5, SM6, SM7, and SM8 that intersect the front surface and the back surface. .
- each side surface SM5, SM6, SM7, SM8 of the semiconductor chip CP2 can also be regarded as a side of the semiconductor chip CP2.
- the semiconductor chip CP1 and the semiconductor chip CP2 are mounted on the upper surface of the die pad DP so that the side surface SM3 of the semiconductor chip CP1 and the side surface SM5 of the semiconductor chip CP2 face each other (see FIGS. 3 and 9).
- the side surface SM3 of the semiconductor chip CP1 and the side surface SM5 of the semiconductor chip CP2 are opposed to each other, but the side surface SM3 of the semiconductor chip CP1 and the side surface SM5 of the semiconductor chip CP2 can be substantially parallel.
- the side surface SM1 is a side surface along the side surface MRc1 of the sealing portion MR and the side DP1 of the die pad DP
- the side surface SM2 is the side surface along the side surface MRc2 of the sealing portion MR and the side DP2 of the die pad DP.
- the side surface SM3 is a side surface along the side surface MRc3 of the sealing portion MR and the side DP3 of the die pad DP
- the side surface SM4 is along the side surface MRc4 of the sealing portion MR and the side DP4 of the die pad DP.
- the side surface SM5 is a side surface along the side surface MRc1 of the sealing portion MR and the side DP1 of the die pad DP
- the side surface SM6 is along the side surface MRc2 of the sealing portion MR and the side DP2 of the die pad DP.
- the side surface SM7 is a side surface along the side surface MRc3 of the sealing portion MR and the side DP3 of the die pad DP
- the side surface SM8 is along the side surface MRc4 of the sealing portion MR and the side DP4 of the die pad DP.
- the semiconductor chip CP1 is disposed on the side closer to the side surface MRc1 of the sealing portion MR, and the semiconductor chip CP2 is disposed on the side closer to the side surface MRc3 of the sealing portion MR. ing. That is, on the upper surface of the die pad DP, of the semiconductor chips CP1 and CP2, the semiconductor chip CP1 is disposed on the side closer to the side DP1 of the die pad DP, and the semiconductor chip CP2 is disposed on the side closer to the side DP3 of the die pad DP. .
- the side surface SM1 of the semiconductor chip CP1 faces the inner lead portions of the plurality of leads LD disposed on the side surface MRc1 side of the sealing portion MR
- the side surface SM2 of the semiconductor chip CP1 is the side surface of the sealing portion MR.
- the side surface SM3 of the semiconductor chip CP1 faces the side surface SM5 of the semiconductor chip CP2, and the side surface SM4 of the semiconductor chip CP1 faces the inner lead portions of the plurality of leads LD arranged on the side surface MRc4 side of the sealing portion MR. is doing.
- the side surface SM5 of the semiconductor chip CP2 faces the side surface SM3 of the semiconductor chip CP1
- the side surface SM6 of the semiconductor chip CP2 is the inner side of the plurality of leads LD disposed on the side surface MRc2 side of the sealing portion MR. It faces the lead part.
- the side surface SM7 of the semiconductor chip CP2 faces the inner lead portions of the plurality of leads LD arranged on the side surface MRc3 side of the sealing portion MR
- the side surface SM8 of the semiconductor chip CP2 is on the side surface MRc4 side of the sealing portion MR. Is opposed to the inner lead portions of the plurality of leads LD.
- the plurality of pad electrodes P1, P2 of the semiconductor chips CP1, CP2 and the plurality of leads LD are electrically connected through a plurality of wires (bonding wires) BW, respectively, and the plurality of pad electrodes of the semiconductor chip CP1 P1 and the plurality of pad electrodes P2 of the semiconductor chip CP2 are electrically connected to each other through a plurality of wires BW.
- the plurality of pad electrodes P1 of the semiconductor chip CP1 are electrically connected to the pad electrode P1 electrically connected to the lead LD via the wire BW and to the pad electrode P2 of the semiconductor chip CP2 via the wire BW.
- the plurality of pad electrodes P2 of the semiconductor chip CP2 are electrically connected to the pad electrode P2 electrically connected to the lead LD via the wire BW and to the pad electrode P1 of the semiconductor chip CP1 via the wire BW.
- the semiconductor device PKG includes a plurality of wires BW.
- the plurality of wires BW includes a wire BW that electrically connects the pad electrode P1 of the semiconductor chip CP1 and the lead LD, and the semiconductor chip CP2.
- the wire BW electrically connects the pad electrode P2 and the lead LD, and the wire BW electrically connects the pad electrode P1 of the semiconductor chip CP1 and the pad electrode P2 of the semiconductor chip CP2.
- the plurality of pad electrodes P1 disposed along the side surface SM1 are the plurality of leads LD disposed on the side surface MRc1 side of the sealing portion MR. Are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P1 formed on the surface of the semiconductor chip CP1 are the plurality of pads LD disposed on the side surface MRc2 side of the sealing portion MR. Are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P1 arranged along the side surface SM4 are the plurality of leads LD arranged on the side surface MRc4 side of the sealing portion MR. Are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P2 formed on the surface of the semiconductor chip CP2 are the plurality of pads LD disposed on the side surface MRc2 side of the sealing portion MR. Are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P2 disposed along the side surface SM7 are the plurality of leads LD disposed on the side surface MRc3 side of the sealing portion MR. Are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P2 formed on the surface of the semiconductor chip CP2 are the plurality of pads LD disposed on the side surface MRc4 side of the sealing portion MR. Are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P1 formed on the surface of the semiconductor chip CP1 the plurality of pad electrodes P1 arranged along the side surface SM3 and the plurality of pad electrodes P2 formed on the surface of the semiconductor chip CP2
- the plurality of pad electrodes P2 arranged along the side surface SM5 are electrically connected to each other via a plurality of wires BW.
- the plurality of pad electrodes P1 formed on the surface of the semiconductor chip CP1 include a plurality of source pad electrodes P1S (see FIG. 9).
- a plurality of source pad electrodes P1S are arranged along the side surface SM1, and each is electrically connected to the lead LD arranged on the side surface MRc1 side of the sealing portion MR via the wire BW. It is connected. Therefore, the source pad electrode P1S is included in the pad electrode P1 electrically connected to the lead LD via the wire BW.
- the source pad electrode P1S is a source pad electrode (pad, bonding pad), and is electrically connected to the source of a power transistor (corresponding to a power MOSFET Q1 described later) formed in the semiconductor chip CP1.
- a plurality of source pad electrodes P1S can be arranged along the side surface SM1 on the surface of the semiconductor chip CP1, but can also be arranged at some distance from the side surface SM1.
- the wire (bonding wire) BW is a conductive connecting member, and more specifically, a conductive wire. Since the wire BW is made of metal, it can also be regarded as a metal wire (metal thin wire).
- the wire BW is sealed in the sealing portion MR and is not exposed from the sealing portion MR. In each lead LD, the connection location of the wire BW is an inner lead portion located in the sealing portion MR.
- all the wires BW can have the same thickness (diameter).
- the thickness (diameter) of the wire BW connecting the source pad electrode P1S of the semiconductor chip CP1 and the lead LD is It is more preferable to make it larger than the thickness (diameter) of the other wire BW. That is, among the plurality of wires BW (corresponding to the wire BW shown in FIG.
- the thickness (diameter) of the wire BW connected to the source pad electrode P1S is set to other than the source pad electrode P1S. It is more preferable to make it larger than the thickness (diameter) of the wire BW connected to the pad electrodes P1, P2. The reason for doing so is as follows.
- the wire BW connecting the source pad electrode P1S of the semiconductor chip CP1 and the lead LD flows a larger current than the other wires BW, so that the resistance is reduced by increasing the thickness (diameter). Loss can be reduced.
- the thickness (diameter) of the wire BW is reduced.
- the dimensions of the pad electrodes P1 and P2 connected to the wire BW can be reduced, which is advantageous for downsizing the semiconductor chips CP1 and CP2.
- the diameter of the wire BW connected to the source pad electrode P1S is about 35 ⁇ m
- the diameter of the wire BW connected to the pad electrodes P1, P2 other than the source pad electrode P1S is about 20 ⁇ m. Can do.
- wire BW As the wire BW, a gold (Au) wire, a copper (Cu) wire, an aluminum (Al) wire, or the like can be suitably used.
- the wire BW connected to the source pad electrode P1S is increased in thickness (diameter) and is connected to the pad electrodes P1 and P2 other than the source pad electrode P1S using a copper wire.
- the thickness (diameter) can be reduced and a gold wire can be used. That is, the wire BW connected to the source pad electrode P1S and the wire BW connected to the pad electrodes P1, P2 other than the source pad electrode P1S are made of different materials, and the former has a large diameter copper (Cu ) Wire, with the latter being a gold (Au) wire with a small diameter.
- the manufacturing cost of the semiconductor device PKG can be suppressed.
- a gold (Au) wire is used for the wire BW having a small diameter (that is, the wire BW connected to the pad electrodes P1 and P2 other than the source pad electrode P1S), thereby connecting the wire BW. Even if the dimensions of P1 and P2 are reduced, the wire BW can be easily and accurately connected to the small pad electrodes P1 and P2. This is because a gold wire is easier to connect to a small pad than a copper wire. Thereby, the connection reliability of the wire BW can be improved while suppressing the manufacturing cost.
- FIG. 10 is a process flow diagram showing manufacturing steps of the semiconductor device PKG shown in FIGS. 11 to 15 are sectional views of the semiconductor device PKG during the manufacturing process. 11 to 15 show cross sections corresponding to FIG.
- the lead frame LF and the semiconductor chips CP1 and CP2 are prepared (step S1 in FIG. 10).
- the lead frame LF includes a frame frame (not shown), a plurality of leads LD coupled to the frame frame, and a die pad DP coupled to the frame frame via a plurality of suspension leads TL. Are integrated.
- step S1 the preparation of the lead frame LF, the preparation of the semiconductor chip CP1, and the preparation of the semiconductor chip CP2 may be performed in any order, or may be performed simultaneously.
- the semiconductor chips CP1 and CP2 are die bonded, and the semiconductor chip CP1 is mounted on the die pad DP of the lead frame via the conductive bonding material BD1, and bonded. Further, the semiconductor chip CP2 is mounted on the die pad DP of the lead frame via the insulating bonding material BD2 and bonded (step S2 in FIG. 10). Since the back surface electrode BE is formed on the back surface of the semiconductor chip CP1, in step S2, the back surface electrode BE of the semiconductor chip CP1 is bonded to the die pad DP via the conductive bonding material BD1. Step S2 will be described in more detail later.
- step S2 the wire bonding process is performed as shown in FIG. 13 (step S3 in FIG. 10).
- step S3 between the plurality of pad electrodes P1 of the semiconductor chip CP1 and the plurality of leads LD of the lead frame LF, between the plurality of pad electrodes P2 of the semiconductor chip CP2 and the plurality of leads LD of the lead frame LF, and The plurality of pad electrodes P1 of the semiconductor chip CP1 and the plurality of pad electrodes P2 of the semiconductor chip CP2 are electrically connected through the plurality of wires BW, respectively.
- step S3 when the thickness (diameter) of the wire BW connecting the source pad electrode P1S of the semiconductor chip CP1 and the lead LD is larger than the thickness (diameter) of the other wires BW, step S3 is performed. Then, it is preferable to perform the wire bonding process in two stages. That is, first, wire bonding using a wire BW having a large diameter is performed as the first step, and then wire bonding using a wire BW having a small diameter is performed as the second step.
- wire bonding is performed on the wire BW shown in FIG.
- the plurality of source pad electrodes P1S of the semiconductor chip CP1 and the plurality of leads LD are electrically connected to each other via the wires BW having a large diameter.
- wire bonding is performed on the wire BW shown in FIG.
- the plurality of pad electrodes P1 of CP1 and the plurality of pad electrodes P2 of the semiconductor chip CP2 are electrically connected through wires BW having a small diameter.
- step S3 wire bonding using a wire BW having a large diameter is performed first, and then wire bonding using a wire BW having a small diameter is performed, whereby the wire BW in the wire bonding process of step S3. Can reduce the possibility of deformation.
- step S4 resin sealing is performed by a molding process (resin molding process), and the semiconductor chips CP1 and CP2 and the plurality of wires BW connected thereto are sealed by the sealing portion MR as shown in FIG. Step S4 in FIG.
- the semiconductor chips CP1 and CP2 the die pad DP, the inner lead portions of the plurality of leads LD, the plurality of wires BW, and the sealing portion MR that seals the suspension leads TL are formed.
- the leads LD and the suspension leads TL are cut at predetermined positions outside the sealing portion MR.
- the lead frame LF is separated from the frame of the lead frame LF (step S5 in FIG. 10).
- step S6 in FIG. 10 the outer lead portion of the lead LD protruding from the sealing portion MR is bent (lead processing, lead molding) (step S6 in FIG. 10).
- the semiconductor device PKG as shown in FIGS. 1 to 9 is manufactured.
- FIGS. 16 to 19 are process flow diagrams showing details of the die bonding step of step S2 in the process flow of FIG. 20 to 30 are plan views or cross-sectional views in the manufacturing process of the semiconductor device PKG. 20, FIG. 20, FIG. 23, FIG. 25, FIG. 27, FIG. 29 and FIG. 30 are plan views, and FIG. 22, FIG. 24, FIG. A cross-section corresponding to 6 is shown. Note that the cross-sectional view taken along line A1-A1 in FIG. 20 corresponds to FIG. 11, the cross-sectional view taken along line A1-A1 in FIG. 21 corresponds to FIG. 22, and the cross-sectional view taken along line A1-A1 in FIG. 24, the sectional view taken along line A1-A1 in FIG. 25 corresponds to FIG. 26, and the sectional view taken along line A1-A1 in FIG. 27 corresponds to FIG.
- FIG. 20 shows a plan view of the lead frame LF before performing the die bonding process of step S2, and shows a plan view of a region from which one semiconductor device PKG is obtained.
- 21, FIG. 23, FIG. 25, FIG. 27, FIG. 29 and FIG. 30 show the same planar area as FIG.
- Step S2 can be performed specifically as shown in FIG.
- the insulating bonding material BD2 is supplied to the region where the semiconductor chip CP2 is to be mounted on the upper surface of the die pad DP (step S2a in FIG. 16).
- the semiconductor chip CP2 is mounted on the upper surface of the die pad DP via the bonding material BD2 (step S2b in FIG. 16).
- the bonding material BD2 is preferably made of an insulating paste type bonding material (adhesive). In steps S2a and S2b, the bonding material BD2 has not yet been cured, and has a viscous paste.
- an insulating paste type bonding material adheresive
- insulating spacers insulating particles, insulating spacer particles
- the insulating spacer contained in the bonding material BD2 is made of, for example, a methacrylic acid ester copolymer, and the size (average particle diameter) can be set to about 10 to 40 ⁇ m, for example. Thereby, the thickness of the bonding material BD2 interposed between the semiconductor chip CP2 and the die pad DP can be set to about 10 to 40 ⁇ m, for example.
- the conductive bonding material BD1 is supplied to the region where the semiconductor chip CP1 is to be mounted on the upper surface of the die pad DP (step S2c in FIG. 16).
- the semiconductor chip CP1 is mounted on the upper surface of the die pad DP via the bonding material BD1 (step S2d in FIG. 16).
- the bonding material BD1 is preferably made of a conductive paste-type bonding material (adhesive) such as silver (Ag) paste.
- adhesive such as silver (Ag) paste.
- the bonding material BD1 has not yet been cured and is a paste having viscosity.
- a conductive paste type bonding material (adhesive) containing insulating spacers (insulating particles, insulating spacer particles) is used as the bonding material BD1. Since the insulating spacer included in the bonding material BD1 is interposed between the semiconductor chip CP1 and the die pad DP, a space between the semiconductor chip CP1 and the die pad DP can be secured. That is, the distance between the semiconductor chip CP1 and the die pad DP is approximately the same as the size (diameter) of the insulating spacer included in the bonding material BD1.
- the bonding material BD1 interposed between the semiconductor chip CP1 and the die pad DP it is possible to prevent the bonding material BD1 interposed between the semiconductor chip CP1 and the die pad DP from being thinned, and the bonding material BD1 having a desired thickness is formed between the semiconductor chip CP1 and the die pad DP. Can intervene.
- the thickness of the bonding material BD1 interposed between the semiconductor chip CP1 and the die pad DP becomes thin, there is a concern that cracks due to thermal stress or the like are likely to occur in the bonding material BD1 between the semiconductor chip CP2 and the die pad DP. However, such a concern can be eliminated by interposing an insulating spacer in the bonding material BD1.
- the size (average particle diameter) of the insulating spacer included in the bonding material BD1 can be set to about 10 to 20 ⁇ m, for example. Accordingly, the thickness of the bonding material BD1 interposed between the semiconductor chip CP1 and the die pad DP can be set to about 10 to 20 ⁇ m, for example.
- step S2e heat treatment
- the bonding material BD2 supplied in step S2a and the bonding material BD1 supplied in step S2c are both thermosetting bonding materials, the bonding materials BD1 and BD2 are cured by performing heat treatment in step S2e. be able to.
- the semiconductor chip CP1 is mounted and fixed on the die pad DP of the lead frame via the bonding material BD1
- the semiconductor chip CP2 is mounted and fixed on the die pad DP of the lead frame via the bonding material BD2.
- step S2 the die bonding process of step S2 can be performed.
- Step S2 can also be performed as shown in FIG.
- the insulating bonding material BD2 is supplied to the region where the semiconductor chip CP2 is to be mounted on the upper surface of the die pad DP (step S2a in FIG. 17).
- the material of the bonding material BD2 is the same as that described in the case of FIGS.
- the semiconductor chip CP2 is mounted on the upper surface of the die pad DP via the bonding material BD2 (step S2b in FIG. 17).
- step S2e1 in FIG. 17 If the bonding material BD2 supplied in step S2a is a thermosetting bonding material, the bonding material BD2 can be cured by performing heat treatment in step S2e1.
- the semiconductor chip CP2 is mounted and fixed on the die pad DP of the lead frame via the bonding material BD2.
- the conductive bonding material BD1 is supplied to the region where the semiconductor chip CP1 is to be mounted on the upper surface of the die pad DP (step S2c in FIG. 16).
- the material of the bonding material BD1 is the same as that described in the case of FIGS.
- the semiconductor chip CP1 is mounted on the upper surface of the die pad DP via the bonding material BD1 (step S2d in FIG. 17).
- step S2e2 heat treatment
- the bonding material BD1 supplied in step S2c is a thermosetting bonding material
- the bonding material BD1 can be cured by performing heat treatment in step S2e2.
- the semiconductor chip CP1 is mounted and fixed on the die pad DP of the lead frame via the bonding material BD1.
- step S2 the die bonding process of step S2 can be performed.
- FIGS. 21 and 22 illustrate the case where the bonding material BD2 is supplied onto the die pad DP from the nozzle (the nozzle for supplying the bonding material BD2) in step S2a.
- FIGS. 25 and 26 illustrate the nozzle ( The case where the bonding material BD1 is supplied onto the die pad DP from the nozzle for supplying the bonding material BD1 is illustrated.
- the bonding material BD2 can be supplied (printed) onto the die pad DP by a printing method, and such a case is shown in FIG.
- step S2c the bonding material BD1 can be supplied (printed) on the die pad DP by a printing method, and such a case is shown in FIG.
- 21 and 29 are plan views, but in order to make the drawings easier to see, the bonding material BD2 supplied on the die pad DP is hatched, and FIGS. 25 and 30 are also plan views. However, in order to make the drawing easy to see, the bonding material BD1 supplied on the die pad DP is hatched.
- 21 and 29, the position where the semiconductor chip CP2 is mounted in step S2b (scheduled mounting position of the semiconductor chip CP2) is indicated by a dotted line.
- the position where the semiconductor chip CP1 is mounted in step S2d (scheduled mounting position of the semiconductor chip CP1) is indicated by a dotted line.
- the process flow of FIG. 16 differs from the process flow of FIG. 17 in the case of the process flow of FIG. 16 in which the bonding material BD1 and the bonding material BD2 are cured in the same process (same heat treatment process).
- the curing of the bonding material BD1 and the curing of the bonding material BD2 are performed in separate steps. That is, in the case of the process flow of FIG. 16, the bonding material BD1 and the bonding material BD2 are cured by the heat treatment in step S2e.
- the bonding material BD1 is cured in step S2e2.
- the bonding material BD2 is cured by the heat treatment in step S2e1.
- steps S2a and S2b are performed and the semiconductor chip CP2 is mounted on the upper surface of the die pad DP via the bonding material BD2.
- steps S2c and S2d are performed, and the semiconductor chip CP1 is mounted on the upper surface of the die pad DP via the bonding material BD1.
- FIG. 18 corresponds to the case where the order of steps S2a and S2b and steps S2c and S2d is changed in the process flow of FIG. 16, and steps S2c and S2d are performed first, and then steps S2a and S2b are performed.
- FIG. 19 shows the process flow of FIG. 17 in which the order of steps S2a, S2b, S2e1 and steps S2c, S2d, S2e2 is changed, and after step S2c, step S2d, and step S2e2 are performed, step S2a, This corresponds to the case where step S2b and step S2e1 are performed.
- any of the process flow of FIG. 16, the process flow of FIG. 17, the process flow of FIG. 18, and the process flow of FIG. 19 can be used.
- step S2a and step S2b are performed first, and then step S2c and step S2d are performed. Is preferred. The reason is as follows.
- the semiconductor chip CP1 has the back electrode BE, and it is necessary to electrically connect the back electrode BE to the die pad DP.
- the semiconductor chip CP2 does not have a back surface electrode and needs to be electrically insulated without being electrically connected to the die pad DP.
- the die bonding material for the semiconductor chip CP1 here, the bonding material BD1
- the bonding material for the semiconductor chip CP2 here, the bonding material BD2
- the bonding material BD2 has insulating properties.
- the bonding material BD1 adheres to the semiconductor chip CP2 mounting region in the die pad DP and the semiconductor chip CP2 is mounted thereon, the semiconductor chip CP2 Insulation between the semiconductor chip CP2 and the die pad DP may be electrically connected (short-circuited).
- the semiconductor chip CP2 and the die pad DP are electrically connected (short-circuited)
- the semiconductor device in which such a phenomenon has occurred is removed in the inspection process after manufacturing, and thus the manufacturing yield of the semiconductor device. This leads to an increase in the manufacturing cost of the semiconductor device. For this reason, it is necessary to prevent the conductive die bonding material (in this case, the bonding material BD1) from adhering to the region where the semiconductor chip CP2 is to be mounted in the die pad DP as much as possible.
- the semiconductor chip CP1 is mounted on the upper surface of the die pad DP through the conductive bonding material BD1 by performing Steps S2c and S2d. Therefore, in a state where the semiconductor chip CP2 is already mounted on the upper surface of the die pad DP via the insulating bonding material BD2, in step S2c, a conductive die bonding material (here, the bonding material BD1) is formed on the upper surface of the die pad DP. ) Will be supplied.
- step S2 it is preferable to perform each step in the order shown in the process flow of FIG. 16 or the process flow of FIG. 17, that is, after step S2a and step S2b are performed first, It is preferable to perform S2c and step S2d.
- the time required for performing the curing process of the bonding material BD1 after supplying the bonding material BD1 on the die pad DP is shortened to some extent, so that the bonding is performed before performing the curing process of the bonding material BD1. It can suppress or prevent that the solvent in material BD1 volatilizes. Also from this viewpoint, the process flow of FIG. 16 and the process flow of FIG. 17 are preferable.
- the process flow in FIG. 16 and the process flow in FIG. 17 are performed from the mounting process (step S2d) of the semiconductor chip CP1 to the curing process (step S2e) of the bonding material BD1.
- step S2e2 can be shortened.
- the solvent in the bonding material BD1 is removed before the bonding material BD1 is cured (steps S2e, S2e2).
- step S2e1 the curing step of the bonding material BD2
- step S2e2 the curing step of the bonding material BD1
- step S2e2 the curing process for the bonding material BD2 and the curing process for the bonding material BD1 are performed in the same process (step S2e).
- step S2e the process flow of FIG. 16 can reduce the number of manufacturing steps of the semiconductor device PKG. Therefore, the manufacturing cost of the semiconductor device PKG can be suppressed. In addition, the throughput of the semiconductor device PKG can be improved.
- step S2e1 the heat treatment temperature for curing the bonding material BD1 and the heat treatment temperature for curing the bonding material BD2 are determined. Be the same.
- the process flow of FIG. 17 performs the curing process (step S2e1) of the bonding material BD2 and the curing process (step S2e2) of the bonding material BD1 separately, and thus heat treatment for curing the bonding material BD1.
- the temperature (heat treatment temperature in step S2e2) and the heat treatment temperature for curing the bonding material BD2 (heat treatment temperature in step S2e1) can be made different.
- the bonding material BD2 can be cured at an optimum heat treatment temperature for curing the bonding material BD2 in step S2e1, and the bonding material BD1 is cured in step S2e2.
- the bonding material BD1 can be cured at an optimum heat treatment temperature.
- FIG. 31 is a circuit diagram (circuit block diagram) of the semiconductor device PKG.
- the semiconductor device PKG of the present embodiment includes the semiconductor chips CP1 and CP2.
- a power MOSFET Metal Oxide Semiconductor Semiconductor Field Effect Transistor
- Q1 Metal Oxide Semiconductor Semiconductor Field Effect Transistor
- sense MOSFET Q2 for detecting a current flowing through the power MOSFET Q1
- control circuit CLC a control circuit for switching.
- the power MOSFET Q1 can function as a power transistor for switching.
- the MOSFET is not only a MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor: MIS field effect transistor) using an oxide film (silicon oxide film) as a gate insulating film, but also an oxide film (silicon oxide film). MISFETs using other insulating films as gate insulating films are also included.
- MISFET Metal-Insulator-Semiconductor-Field-Effect-Transistor
- the control circuit CLC includes a driver circuit (drive circuit) that drives the power MOSFET Q1 and the sense MOSFET Q2. For this reason, the control circuit CLC controls the potential of the gate of the power MOSFET Q1 (corresponding to a gate electrode 8 described later) in accordance with a signal supplied to the control circuit CLC from the outside of the semiconductor chip CP1, and operates the power MOSFET Q1. Can be controlled. That is, the gate of the power MOSFET Q1 is connected to the control circuit CLC, and the power MOSFET Q1 is turned on by supplying an on signal (a gate voltage that turns on the power MOSFET Q1) from the control circuit CLC to the gate of the power MOSFET Q1. And can be.
- the power MOSFET Q1 When the power MOSFET Q1 is turned on by supplying an ON signal from the control circuit CLC to the gate of the power MOSFET Q1, the voltage of the power source BAT is output from the power MOSFET Q1 and supplied to the load LOD.
- the power MOSFET Q1 When the power MOSFET Q1 is turned off by supplying an off signal to the gate of the power MOSFET Q1 from the control circuit CLC (or stopping the supply of the on signal), the supply of voltage from the power source BAT to the load LOD is stopped.
- Such on / off control of the power MOSFET Q1 of the semiconductor chip CP1 is performed by the control circuit CLC of the semiconductor chip CP1.
- the semiconductor device PKG can function as a semiconductor device for a switch that performs on / off switching of voltage application from the power source BAT to the load LOD.
- the power MOSFET Q1 of the semiconductor chip CP1 can function as a switching element.
- the power MOSFET Q1 can be regarded as an output circuit.
- any electronic device or electronic component that is desired to be connected to the power source BAT through the semiconductor device PKG for switching can be applied.
- a motor, a lamp, a heater, or the like can be used as the load LOD.
- a sense MOSFET Q2 for current detection is provided in the semiconductor chip CP1 of the semiconductor device PKG.
- the current flowing through the power MOSFET Q1 is detected by the sense MOSFET Q2, and the power MOSFET Q1 is controlled according to the current flowing through the sense MOSFET Q2.
- the control circuit CLC controls the gate voltage of the power MOSFET Q1 to The current of the MOSFET Q1 is limited to a predetermined value or less, or the power MOSFET Q1 is forcibly turned off. Thereby, it is possible to prevent an excessive current from flowing through the power MOSFET Q1, and it is possible to protect the semiconductor device PKG and an electronic device using the same.
- the sense MOSFET Q2 has a common drain and gate with the power MOSFET Q1. That is, since the drain of the power MOSFET Q1 and the drain of the sense MOSFET Q2 formed in the semiconductor chip CP1 are both electrically connected to the back electrode BE of the semiconductor chip CP1, they are electrically connected to each other. . Therefore, the back electrode BE of the semiconductor chip CP1 is a back electrode for the drains of the power MOSFET Q1 and the sense MOSFET Q2.
- the back electrode BE of the semiconductor chip CP1 to which the drains of the power MOSFET Q1 and the sense MOSFET Q2 are connected is connected to the terminal TE1 of the semiconductor device PKG.
- the die pad DP corresponds to the terminal TE1.
- the same potential is supplied from the terminal TE1 (that is, the die pad DP) of the semiconductor device PKG to the drain of the sense MOSFET Q2 and the drain of the power MOSFET Q1 through the bonding material BD1 and the back electrode BE of the semiconductor chip CP1. .
- the terminal TE1 (die pad DP) is connected to a power source (battery) BAT arranged outside the semiconductor device PKG
- the voltage of the power source BAT is connected to the junction from the terminal TE1 (that is, the die pad DP) of the semiconductor device PKG.
- the material BD1 and the back electrode BE of the semiconductor chip CP1 are supplied to the drain of the power MOSFET Q1 and the drain of the sense MOSFET Q2.
- the sense MOSFET Q2 and the power MOSFET Q1 are electrically connected to each other, and the common gate is connected to the control circuit CLC. From the control circuit CLC, the gate of the sense MOSFET Q2 and the gate of the power MOSFET Q1. Are supplied with the same gate signal (gate voltage). Specifically, the gate (gate electrode) of the sense MOSFET Q2 and the gate (gate electrode) of the power MOSFET Q1 formed in the semiconductor chip CP1 are connected to the control circuit CLC in the semiconductor chip CP1 via the internal wiring of the semiconductor chip CP1. Is electrically connected.
- the source of the sense MOSFET Q2 is not common with the source of the power MOSFET Q1, and the source of the power MOSFET Q1 and the source of the sense MOSFET Q2 are not short-circuited.
- the source of the power MOSFET Q1 is connected to a terminal TE2 of the semiconductor device PKG, and this terminal TE2 is connected to a load LOD arranged outside the semiconductor device PKG. That is, the source of the power MOSFET Q1 is connected to the load LOD.
- the lead LD electrically connected to the source pad electrode P1S of the semiconductor chip CP1 via the wire BW corresponds to the terminal TE2.
- the source of the power MOSFET Q1 formed in the semiconductor chip CP1 is electrically connected to the source pad electrode P1S of the semiconductor chip CP1 via the internal wiring of the semiconductor chip CP1, and this source pad electrode P1S is electrically connected to a terminal TE2 (lead LD) via a wire BW, and a load LOD is connected to the terminal TE2 (lead LD).
- the power MOSFET Q1 is turned on (conductive state) by supplying an on signal from the control circuit CLC to the gate of the power MOSFET Q1, the voltage of the power supply BAT is supplied to the load LOD via the power MOSFET Q1 in the on state. Will be.
- the source of the sense MOSFET Q2 is connected to the control circuit CLC. Specifically, the source of the sense MOSFET Q2 formed in the semiconductor chip CP1 is electrically connected to the control circuit CLC in the semiconductor chip CP1 via the internal wiring of the semiconductor chip CP1.
- the symbol D1 indicates the drain of the power MOSFET Q1
- the symbol S1 indicates the source of the power MOSFET Q1
- the symbol D2 indicates the drain of the sense MOSFET Q2
- the symbol S2 indicates the source of the sense MOSFET Q2. Yes.
- the sense MOSFET Q2 is formed in the semiconductor chip CP1 together with the power MOSFET Q1, and this sense MOSFET Q2 is formed so as to form a current mirror circuit with the power MOSFET Q1 in the semiconductor chip CP1, and is, for example, 1/20000 of the power MOSFET Q1. It has the size of This size ratio can be changed as required.
- control circuit CLC formed in the semiconductor chip CP1 is electrically connected to some pad electrodes P1 among the plurality of pad electrodes P1 of the semiconductor chip CP1 through the internal wiring of the semiconductor chip CP1.
- the plurality of pad electrodes P1 of the semiconductor chip CP1 include an input pad electrode, an output pad electrode, and a ground pad electrode. From these pad electrodes P1, signals (input signals) and control signals are input to the control circuit CLC. A ground potential is input or supplied, and a signal (output signal) output from the control circuit CLC is output from these pad electrodes P1.
- Each pad electrode P1 of the semiconductor chip CP1 is electrically connected to the lead LD or the pad electrode P2 of the semiconductor chip CP2 via the wire BW. That is, the pad electrode P1 of the semiconductor chip CP1 includes a pad electrode P1 electrically connected to the lead LD via the wire BW and a pad electrode electrically connected to the pad electrode P2 of the semiconductor chip CP2 via the wire BW. There is P1.
- the semiconductor chip CP2 is a microcomputer chip (control chip), and can function as a control semiconductor chip for controlling the operation of the semiconductor chip CP1.
- FIG. 31 does not show a circuit in the semiconductor chip CP2, but actually, a circuit for controlling the semiconductor chip CP1 (a circuit in the semiconductor chip CP1) is formed in the semiconductor chip CP2. That is, a circuit for controlling the control circuit CLC formed in the semiconductor chip CP1 is formed in the semiconductor chip CP2.
- the internal circuit of the semiconductor chip CP2 is electrically connected to the plurality of pad electrodes P2 of the semiconductor chip CP2 via the internal wiring of the semiconductor chip CP2.
- Each pad electrode P2 of the semiconductor chip CP2 is electrically connected to the lead LD or the pad electrode P1 of the semiconductor chip CP1 via the wire BW. That is, the pad electrode P2 of the semiconductor chip CP2 includes a pad electrode P2 electrically connected to the lead LD via the wire BW and a pad electrode electrically connected to the pad electrode P1 of the semiconductor chip CP1 via the wire BW.
- P2 of the semiconductor chip CP2 includes a pad electrode P2 electrically connected to the lead LD via the wire BW and a pad electrode electrically connected to the pad electrode P1 of the semiconductor chip CP1 via the wire BW.
- the plurality of leads LD connected to the semiconductor chip CP2 via the wires BW include an input lead, an output lead, and a ground lead. From these leads LD to the internal circuit of the semiconductor chip CP2 A signal (input signal) or a ground potential is input or supplied, and a signal (output signal) output from the internal circuit of the semiconductor chip CP2 is output from these leads LD.
- any of the plurality of leads LD connected to the semiconductor chip CP2 via the wire BW is connected to the power source BAT arranged outside the semiconductor device PKG via the regulator REG.
- the voltage of the power supply BAT is converted to a voltage suitable as the power supply voltage of the semiconductor chip CP2 by the regulator REG, then supplied to the lead LD connected to the regulator REG, and the semiconductor chip via the wire BW connected to the lead LD. It is supplied to CP2.
- Some pad electrodes P2 of the plurality of pad electrodes P2 of the semiconductor chip CP2 are electrically connected to some pad electrodes P1 of the plurality of pad electrodes P1 of the semiconductor chip CP1 through wires BW, respectively.
- the internal circuit of the semiconductor chip CP1 is connected to the internal circuit of the semiconductor chip CP1 via the pad electrode P2, the wire BW (the wire BW connecting the pad electrodes P1 and P2) of the semiconductor chip CP2, and the pad electrode P1 of the semiconductor chip CP1. For example, it can be electrically connected to the control circuit CLC).
- the lead LD electrically connected to the semiconductor chip CP2 and the lead LD electrically connected to the semiconductor chip CP1 can be electrically connected outside the semiconductor device PKG.
- the semiconductor device PKG is mounted on a wiring board (mounting board), and in this wiring board, a lead LD electrically connected to the semiconductor chip CP2 and a lead LD electrically connected to the semiconductor chip CP1 It can be electrically connected via the wiring of the wiring board.
- the internal circuit of the semiconductor chip CP2 is transferred to the internal circuit (for example, the control circuit CLC) of the semiconductor chip CP1 via the wiring outside the semiconductor device PKG (for example, the wiring of the wiring board on which the semiconductor device PKG is mounted). It can also be electrically connected.
- the internal circuit of the semiconductor chip CP1 corresponds to a circuit formed in the semiconductor chip CP1
- the internal circuit of the semiconductor chip CP2 corresponds to a circuit formed in the semiconductor chip CP2.
- the internal wiring of the semiconductor chip CP1 corresponds to the wiring formed in the semiconductor chip CP1
- the internal wiring of the semiconductor chip CP2 corresponds to the wiring formed in the semiconductor chip CP2.
- FIG. 32 is a fragmentary cross-sectional view of the semiconductor chip CP1, and a fragmentary cross-sectional view of a region (power MOSFET formation region) where the transistors constituting the power MOSFET Q1 are formed in the semiconductor chip CP1 is shown.
- a region (planar region) in which the transistor constituting the power MOSFET Q1 is formed is referred to as a power MOSFET formation region.
- a region (planar region) where the transistors constituting the sense MOSFET Q2 are formed is referred to as a sense MOSFET formation region.
- a region (planar region) where the control circuit CLC is formed is referred to as a control circuit formation region.
- the semiconductor chips CP1 and CP2 are arranged side by side on the die pad DP so that the control circuit formation region of the semiconductor chip CP1 is closer to the semiconductor chip CP2 than the power MOSFET formation region of the semiconductor chip CP1.
- FIG. 32 illustrates the cross-sectional structure of the power MOSFET formation region, but the cross-sectional structure of the sense MOSFET formation region is basically the same as the structure of FIG.
- the source wiring M2S is covered with the protective film 13 and is not exposed.
- the power MOSFET Q1 is formed on the main surface of the semiconductor substrate 1 constituting the semiconductor chip CP1.
- the semiconductor substrate 1 constituting the semiconductor chip CP1 is made of n-type single crystal silicon into which an n-type impurity such as arsenic (As) is introduced, for example.
- Semiconductor substrate (so-called epitaxial wafer) in which an epitaxial layer (semiconductor layer) made of n ⁇ -type single crystal silicon having a lower impurity concentration is formed on a substrate body made of n-type single crystal silicon substrate as semiconductor substrate 1 It is also possible to use.
- a field insulating film (not shown) made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 1.
- a plurality of unit transistor cells constituting the power MOSFET Q1 are formed in the active region surrounded by the field insulating film, and the power MOSFET Q1 includes the plurality of unit transistors provided in the power MOSFET formation region. It is formed by connecting cells in parallel.
- a plurality of unit transistor cells constituting the sense MOSFET Q2 are formed in the active region surrounded by the field insulating film, and the sense MOSFET Q2 includes the plurality of unit MOSFET cells provided in the sense MOSFET formation region. It is formed by connecting unit transistor cells in parallel.
- the individual unit transistor cells formed in the power MOSFET formation region and the individual unit transistor cells formed in the sense MOSFET formation region basically have the same structure (configuration).
- the area of the region is different from that of the sense MOSFET formation region, and the area of the sense MOSFET formation region is smaller than the area of the power MOSFET formation region. Therefore, the number of unit transistor cells connected differs between the power MOSFET Q1 and the sense MOSFET Q2, and the number of unit transistor cells connected in parallel constituting the sense MOSFET Q2 is the number of unit transistor cells connected in parallel constituting the power MOSFET Q1. Less than.
- Each unit transistor cell in the power MOSFET formation region and the sense MOSFET formation region is formed of, for example, an n-channel MOSFET having a trench gate structure.
- the semiconductor substrate 1 has a function as a drain region of the unit transistor cell.
- a drain back electrode (back drain electrode, drain electrode) BE is formed on the entire back surface of the semiconductor substrate 1 (semiconductor chip CP1).
- the back electrode BE is formed by, for example, stacking a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer in order from the back surface of the semiconductor substrate 1.
- the back electrode BE of the semiconductor chip CP1 is joined to and electrically connected to the die pad DP via the joining material BD1.
- the p-type semiconductor region 3 formed in the semiconductor substrate 1 functions as a channel formation region of the unit transistor cell. Furthermore, the n + type semiconductor region 4 formed on the p type semiconductor region 3 has a function as a source region of the unit transistor cell. Accordingly, the semiconductor region 4 is a source semiconductor region.
- a p + type semiconductor region 5 is formed above the p type semiconductor region 3 and adjacent to the n + type semiconductor region 4. The impurity concentration of the p + type semiconductor region 5 is higher than the impurity concentration of the p type semiconductor region 3.
- a groove (trench) 6 extending from the main surface of the semiconductor substrate 1 in the thickness direction of the semiconductor substrate 1 is formed. Groove 6 extends through the n + -type semiconductor region 3 from the upper surface of the semiconductor region 4 of the semiconductor region 4 and the p-type n + -type are formed so as to terminate in the semiconductor substrate 1 in the lower layer.
- a gate insulating film 7 made of silicon oxide or the like is formed on the bottom and side surfaces of the trench 6.
- a gate electrode 8 made of doped polysilicon or the like is embedded in the trench 6 with a gate insulating film 7 interposed therebetween. The gate electrode 8 has a function as a gate electrode of the unit transistor cell.
- An interlayer insulating film 9 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrode 8. Contact holes (through holes) are formed in the interlayer insulating film 9, and conductive plugs (via portions) 10 are embedded in the contact holes formed in the interlayer insulating film 9.
- a wiring M1 is formed on the interlayer insulating film 9 in which the plug 10 is embedded.
- the wiring M1 is a wiring in the first wiring layer.
- An interlayer insulating film 11 is formed on the interlayer insulating film 9 so as to cover the wiring M1.
- a through hole (through hole) is formed in the interlayer insulating film 11, and a conductive plug (via portion) 12 is embedded in each through hole formed in the interlayer insulating film 11.
- a wiring M2 and a pad electrode (bonding pad) P1 are formed on the interlayer insulating film 11 in which the plug 12 is embedded.
- the wiring M2 is a wiring of the second wiring layer.
- the wiring M1 is made of a conductive film, specifically made of a metal film, and preferably made of an aluminum film or an aluminum alloy film.
- the wiring M2 and the pad electrode P1 are made of a conductive film, specifically, a metal film, preferably an aluminum film or an aluminum alloy film.
- the wiring M1 includes a gate wiring (not shown) and a source wiring M1S.
- the wiring M2 includes a gate wiring (not shown) and a source wiring M2S.
- the source n + -type semiconductor region 4 is electrically connected to the source wiring M1S through the plug 10 disposed on the semiconductor region 4, and the p + -type semiconductor region 5 is connected to the source wiring M1S.
- the source line M1S is electrically connected to the source line M2S via the plug 12 disposed between the source line M1S and the source line M2S.
- the p + type semiconductor region 5 Since the p + type semiconductor region 5 has the same conductivity type as the p type semiconductor region 3 and is in contact with the p type semiconductor region 3, the p + type semiconductor region 5 is electrically connected to the p type semiconductor region 3. It is connected to the. Therefore, the source wiring M2S is electrically connected to the source n + type semiconductor region 4 through the plug 12, the source wiring M1S, and the plug 10, and also to the p-type semiconductor region 3 for channel formation. Electrically connected.
- the source wiring M2S electrically connected to the source of the power MOSFET Q1 is formed in almost the entire power MOSFET formation region, and a part thereof is from the opening 14 of the protective film 13.
- the exposed pad electrode P1S is formed by the exposed portion of the source wiring M2S.
- the source wiring M2S electrically connected to the source of the sense MOSFET Q2 is formed in almost the entire sense MOSFET formation region and is covered with the protective film 13. , Not exposed.
- Source wirings M1S and M2S electrically connected to the source of the sense MOSFET Q2 are electrically connected to a control circuit CLC formed in the semiconductor chip CP1.
- the source wirings M1S and M2S electrically connected to the source of the power MOSFET Q1 and the source wirings M1S and M2S electrically connected to the source of the sense MOSFET Q2 are not electrically connected and are separated. .
- the plurality of gate electrodes 8 formed in the power MOSFET formation region and the sense MOSFET formation region are electrically connected to each other, and the plug 10, the gate wiring (not shown) of the wiring M ⁇ b> 1, and the plug 12.
- a gate wiring (not shown) of the wiring M2 is electrically connected to a control circuit CLC formed in the semiconductor chip CP1.
- An insulating protective film (insulating film) 13 is formed on the interlayer insulating film 11 so as to cover the wiring M2 and the pad electrode.
- the protective film 13 is made of, for example, a resin film such as polyimide resin.
- This protective film 13 is the uppermost film of the semiconductor chip CP1.
- a plurality of openings 14 are formed in the protective film 13, and a part of the conductor pattern constituting the pad electrode P ⁇ b> 1 or a part of the source wiring M ⁇ b> 2 ⁇ / b> S is exposed from each opening 14.
- the source pad electrode P1S is formed by the source wiring M2S exposed from the opening 14 of the protective film 13, and the pad electrodes P1 other than the source pad electrode P1S are conductors formed in the same layer as the wiring M2. It is formed by a pattern (a conductor pattern for the pad electrode P1 electrode).
- the conductor pattern (not shown in FIG. 32) constituting the pad electrode P1 other than the source pad electrode P1S is formed in the same layer and in the same process as the wiring M2, and has, for example, a rectangular planar shape. .
- a metal layer may be formed on the surface of the pad electrode P1 (including the source pad electrode P1S) exposed from the opening 14 by plating or the like.
- a plurality of source pad electrodes P1S which are source pad electrodes of the power MOSFET Q1, are separated from each other by the uppermost protective film 13, but are connected to each other through the source wiring M2S and the source wiring M1S. Electrically connected.
- the operating currents of the unit transistors of the power MOSFET Q1 and the sense MOSFET Q2 are gated between the n-type semiconductor substrate 1 for drain and the n + -type semiconductor region 4 for source. It flows in the thickness direction of the semiconductor substrate 1 along the side surface of the electrode 8 (that is, the side surface of the groove 6). That is, the channel is formed along the thickness direction of the semiconductor chip CP1.
- the semiconductor chip CP1 is a semiconductor chip in which a vertical MOSFET having a trench gate structure is formed, and the power MOSFET Q1 and the sense MOSFET Q2 are each formed by a trench gate type MISFET.
- the vertical MOSFET corresponds to a MOSFET in which a current between the source and the drain flows in the thickness direction of the semiconductor substrate (a direction substantially perpendicular to the main surface of the semiconductor substrate).
- a plurality of transistors and wirings M1 and M2 constituting the control circuit CLC are formed in the control circuit formation region RG4, but illustration and description thereof are omitted here.
- the semiconductor chip CP1 can incorporate a plurality of the power MOSFETs Q1.
- FIG. 33 is a cross-sectional view of a semiconductor device (semiconductor package) PKG101 of the study example examined by the present inventors, and shows a cross-sectional view corresponding to FIG.
- the semiconductor device PKG101 of the examination example shown in FIG. 33 has two die pads DP101 and DP102, and the semiconductor chip CP101 is mounted on one of the die pads DP101 via the bonding material BD101, and the other A semiconductor chip CP102 is mounted on the die pad DP102 via a bonding material BD102.
- the die pad DP101 and the die pad DP102 are not integrally formed, but are electrically separated. That is, the die pads DP101 and DP102 are sealed in the sealing portion MR, but the die pad DP101 and the die pad DP102 are electrically separated by interposing a part of the sealing portion MR therebetween. . Further, the lower surfaces of the die pads DP101 and DP102 are exposed on the back surface of the sealing portion MR.
- a back electrode BE is formed on the back surface of the semiconductor chip CP1, and the bonding material BD101 has conductivity. For this reason, the back surface electrode BE of the semiconductor chip CP1 is electrically connected to the die pad DP101 via the conductive bonding material BD101.
- the bonding material BD102 may have conductivity or insulating properties.
- the die pad DP102 and the die pad DP101 are electrically separated, the voltage supplied from the die pad DP101 to the back electrode BE of the semiconductor chip CP1 via the conductive bonding material BD101 is not supplied to the die pad DP102. . Therefore, since the bonding material BD102 has conductivity, even if the back surface of the semiconductor chip CP102 is electrically connected to the die pad DP102, the voltage supplied to the back surface electrode BE of the semiconductor chip CP1 is applied to the back surface of the semiconductor chip CP102. Since the supply is not required, there is no problem in the operation of the semiconductor chip CP2.
- the die pad DP101 for mounting the semiconductor chip CP1 and the die pad DP102 for mounting the semiconductor chip CP2 are required, and the die pad DP101 and the die pad DP102 need to be separated by the sealing portion MR. Plane dimensions increase. This is disadvantageous for downsizing of the semiconductor device PKG101.
- the number of the leads LD is reduced by the large number of suspension leads. This is disadvantageous in increasing the number of pins (the number of leads LD) of the semiconductor device PKG101. In addition, an increase in the number of suspension leads also causes an increase in the planar dimensions of the semiconductor device PKG101.
- the versatility of the lead frame used for manufacturing the semiconductor device PKG101 is reduced, and the manufacturing of the semiconductor device PKG101 is reduced. This will increase the cost.
- the semiconductor chip CP1 and the semiconductor chip CP2 are mounted on a common die pad DP.
- the planar size of the semiconductor device PKG of the present embodiment can be reduced as compared with the semiconductor device PKG101 of the examination example illustrated in FIG. 33, and thus the semiconductor device PKG can be reduced in size.
- the number of suspension leads can be reduced in the semiconductor device PKG of the present embodiment as compared with the semiconductor device PKG101 of the study example shown in FIG. For this reason, the number of pins (the number of leads LD) of the semiconductor device PKG can be increased.
- cracks may occur in the sealing portion MR between the die pad DP101 and the die pad DP102 that may occur in the semiconductor device PKG101 of the examination example shown in FIG. 33. Since it is not PKG, the reliability of the semiconductor device PKG can be improved.
- the semiconductor device PKG of the present embodiment it is not necessary to design the die pads DP101 and DP102 in accordance with the dimensions of the semiconductor chips CP1 and CP2, so that a general-purpose lead frame used for manufacturing the semiconductor device PKG is used. Therefore, the manufacturing cost of the semiconductor device PKG can be reduced. Further, since the size of the die pad DP can be made larger than the size of the die pad DP101 without increasing the size of the semiconductor device PKG, the heat generated in the semiconductor chip CP1 is transferred from the die pad DP to the outside of the semiconductor device PKG. The heat dissipation characteristics of the semiconductor device PKG can be improved.
- the semiconductor chip CP1 and the semiconductor chip CP2 are arranged side by side on a conductive die pad, and of the semiconductor chips CP1 and CP2, the semiconductor chip CP1 is mounted on the die pad DP via a conductive bonding material BD1, and the semiconductor chip CP2 is mounted on the die pad DP via an insulating bonding material BD2.
- the semiconductor chip CP1 has a back electrode BE, and it is necessary to electrically connect the back electrode BE of the semiconductor chip CP1 to the die pad DP through the bonding material BD1.
- the bonding material BD1 which is a die bonding material for the semiconductor chip CP1
- a desired voltage can be supplied to the back surface electrode BE of the semiconductor chip CP1 through the die pad DP and the bonding material BD1.
- the semiconductor chip CP2 does not have a back electrode.
- the voltage supplied to the back surface electrode BE of the semiconductor chip CP1 via the die pad DP and the bonding material BD1 is not supplied to the semiconductor chip CP1. Therefore, it is desirable to electrically insulate the semiconductor chip CP2 and the die pad DP. Therefore, the bonding material BD2 which is a die bonding material for the semiconductor chip CP2 needs to have insulating properties without having conductivity.
- the semiconductor chips CP1 and CP2 are mounted on the die pad DP, the conductive bonding material BD1 is used as the die bonding material for the semiconductor chip CP1, and the insulating bonding material BD2 is used as the die bonding material for the semiconductor chip CP2. Used. Accordingly, a desired voltage (for example, the voltage of the power supply BAT) can be supplied to the back surface electrode BE of the semiconductor chip CP1 via the die pad DP and the bonding material BD1, and the voltage is supplied to the back surface electrode of the semiconductor chip CP2. Therefore, both the semiconductor chip CP1 and the semiconductor chip CP2 can be accurately operated.
- a desired voltage for example, the voltage of the power supply BAT
- An insulating bonding material BD2 is interposed between the semiconductor chip CP2 and the die pad DP and is electrically insulated.
- the semiconductor chip CP2 and the die pad are used. It is desirable to increase the breakdown voltage between the DP. For example, if the breakdown voltage between the semiconductor chip CP2 and the die pad DP is low, there is a possibility that electrostatic breakdown, which is breakdown due to electrostatic discharge (ESD), occurs between the semiconductor chip CP2 and the die pad DP. is there. In order to prevent electrostatic breakdown, it is desirable to increase the breakdown voltage between the semiconductor chip CP2 and the die pad DP as much as possible.
- the withstand voltage means an insulation withstand voltage.
- the gap between the semiconductor chip CP2 and the die pad DP102 is used. Electrostatic breakdown can occur.
- the die pad DP101 mounting the semiconductor chip CP1 and the die pad DP102 mounting the semiconductor chip CP2 are separated, so that the semiconductor chip CP2 is conductive. It can be mounted on the die pad DP102 via the die bonding material (the bonding material BD102).
- the semiconductor chip CP2 and the die pad DP102 are electrically connected via the conductive die bonding material (the bonding material BD102), the charge is charged at the junction between the semiconductor chip CP2 and the die pad DP102. No electrostatic discharge occurs between the semiconductor chip CP2 and the die pad DP102, and therefore no electrostatic breakdown occurs. Therefore, in the semiconductor device PKG101 of the examination example shown in FIG. 33, it is not necessary to worry about the withstand voltage between the semiconductor chip CP2 and the die pad DP102.
- the semiconductor device PKG does not have the semiconductor chip CP1, and only the semiconductor chip CP2 is mounted on the die pad DP without mounting the semiconductor chip CP1.
- the semiconductor chip CP2 can be mounted on the die pad DP via a conductive die bonding material (for example, silver paste) instead of the insulating bonding material BD2.
- a conductive die bonding material for example, silver paste
- the semiconductor chip CP2 and the die pad DP are electrically connected via the conductive die bonding material, no charge is charged at the junction between the semiconductor chip CP2 and the die pad DP, and the semiconductor chip CP2 There is no electrostatic discharge between the die pad DP and therefore no electrostatic breakdown occurs. For this reason, it is not necessary to worry about the withstand voltage between the semiconductor chip CP2 and the die pad DP.
- the semiconductor chip CP1 having the back electrode BE is mounted side by side on the common die pad DP together with the semiconductor chip CP2.
- the die bonding material (here, the bonding material BD2) for the semiconductor chip CP2 is conductive. It is necessary to have an insulating property.
- the semiconductor chip CP2 and the die pad DP are insulated via an insulating die bonding material (here, the bonding material BD2), a charge may be charged at the bonding portion between the semiconductor chip CP2 and the die pad DP. There is a risk that electrostatic discharge may occur between the semiconductor chip CP2 and the die pad DP, resulting in electrostatic breakdown.
- the breakdown voltage between the semiconductor chip CP2 and the die pad DP is increased as much as possible so that electrostatic breakdown does not occur between the semiconductor chip CP2 and the die pad DP. It is desirable to do. Therefore, in order to prevent electrostatic breakdown between the semiconductor chip CP2 and the die pad DP, it is considerably higher than the voltage (for example, about several tens of volts) supplied to the back electrode BE of the semiconductor chip CP1 during the normal operation of the semiconductor device PKG. Even if a high voltage (for example, 2000 V or more) is applied between the semiconductor chip CP2 and the die pad DP, it is desired that the semiconductor chip CP2 and the die pad DP do not break down.
- a high voltage for example, 2000 V or more
- FIG. 34 and 35 are enlarged plan perspective views showing a part of the semiconductor device PKG.
- FIG. 34 shows an enlarged view of the semiconductor chip CP2 mounted on the die pad DP via the bonding material BD2
- FIG. 35 shows the semiconductor chip mounted on the die pad DP via the bonding material BD1.
- CP1 is shown enlarged.
- FIG. 34 and FIG. 35 the sealing portion MR and the wire BW are seen through as in FIG. Therefore, in FIG. 34, the semiconductor chip CP2 and the bonding material BD2 are illustrated, and in FIG. 35, the semiconductor chip CP1 and the bonding material BD1 are illustrated.
- FIGS. 36 and 37 are enlarged perspective views showing a part of the semiconductor device PKG, but the sealing portion MR is seen through.
- FIG. 36 corresponds to a perspective view when the semiconductor chip CP2 is viewed from any one of the arrows F1, F2, F3, and F4 in FIG. 34
- FIG. 37 shows the arrows H1, H2, and FIG.
- This corresponds to a perspective view when the semiconductor chip CP1 is viewed from either direction of H3 and H4.
- FIG. 36 shows a perspective view of the side SD2 of the semiconductor chip CP2 as viewed from the front
- FIG. 37 shows a perspective view of the side SD1 of the semiconductor chip CP1 as viewed from the front.
- FIG. 38 and 39 are cross-sectional views showing an enlarged part of the semiconductor device PKG.
- 38 corresponds to a cross-sectional view of any of the E1-E1, E2-E2, E3-E3, and E4-E4 lines of FIG. 34
- FIG. 39 shows the G1-G1 line, G2- of FIG. This corresponds to a cross-sectional view of any of the G2, G3-G3, and G4-G4 lines. Therefore, FIG. 38 shows a cross section along the side SD2 of the semiconductor chip CP2, and FIG. 39 shows a cross section along the side SD1 of the semiconductor chip CP1.
- This inventor originates from the fact that when the semiconductor chip CP1 and the semiconductor chip CP2 are mounted on the common die pad DP, it is necessary to use an insulating die bonding material as the die bonding material for the semiconductor chip CP2. Therefore, since there is a risk that electrostatic breakdown occurs between the semiconductor chip CP2 and the die pad DP, it was examined to increase the breakdown voltage between the semiconductor chip CP2 and the die pad DP. As a result, it has been found that it is effective to cover the side SD2 of the semiconductor chip CP2 with the insulating bonding material BD2 as much as possible in order to increase the breakdown voltage between the semiconductor chip CP2 and the die pad DP.
- the side (corner) SD2 of the semiconductor chip CP2 corresponds to a side (corner) formed by intersecting two side surfaces of the semiconductor chip CP2 (see FIGS. 34, 36, and 38). Since the semiconductor chip CP2 has four side surfaces SM5, SM6, SM7, and SM8, there are also four sides SD2 formed by crossing adjacent side surfaces (SM5, SM6, SM7, SM8). That is, on the side SD2 of the semiconductor chip CP2, a side SD2 (SD2a) formed by intersecting the side surface SM5 and the side surface SM6, and a side SD2 (SD2b) formed by intersecting the side surface SM6 and the side surface SM7. There are a side SD2 (SD2c) formed by intersecting the side surface SM7 and the side surface SM8, and a side SD2 (SD2d) formed by intersecting the side surface SM8 and the side surface SM5.
- a side SD2 formed by intersecting the side surface SM5 and the side surface SM6 is referred to as a side SD2a with reference sign SD2a, and a side formed by intersecting the side surface SM6 and the side surface SM7.
- SD2 is referred to as a side SD2b with a reference SD2b.
- a side SD2 formed by intersecting the side surface SM7 and the side surface SM8 is referred to as a side SD2c with a reference symbol SD2c, and a side SD2 formed by intersecting the side surface SM8 and the side surface SM5. Is referred to as a side SD2d with a reference SD2d.
- the side SD2a exists between the side surface SM5 and the side surface SM6, the side SD2b exists between the side surface SM6 and the side surface SM7, the side SD2c exists between the side surface SM7 and the side surface SM8, and the side SD2d.
- the side (corner) SD1 of the semiconductor chip CP1 corresponds to a side (corner) formed by intersecting two side surfaces of the semiconductor chip CP1 (see FIGS. 35, 37, and 39). Since the semiconductor chip CP1 has four side surfaces SM1, SM2, SM3, and SM4, there are also four sides SD1 formed by intersecting adjacent side surfaces (SM1, SM2, SM3, SM4). That is, the side SD1 of the semiconductor chip CP1 has a side SD1 (SD1a) formed by intersecting the side surface SM1 and the side surface SM2, and a side SD1 (SD1b) formed by intersecting the side surface SM2 and the side surface SM3. There are a side SD1 (SD1c) formed by intersecting the side surface SM3 and the side surface SM4, and a side SD1 (SD1d) formed by intersecting the side surface SM4 and the side surface SM1.
- a side SD1 formed by crossing the side surface SM1 and the side surface SM2 is referred to as a side SD1a with a reference symbol SD1a, and a side formed by crossing the side surface SM2 and the side surface SM3.
- SD1 is referred to as a side SD1b with a reference SD1b.
- a side SD1 formed by intersecting the side surface SM3 and the side surface SM4 is referred to as a side SD1c with a reference symbol SD1c, and a side SD1 formed by intersecting the side surface SM4 and the side surface SM1. Is referred to as a side SD1d with a reference SD1d.
- the side SD1a exists between the side surface SM1 and the side surface SM2, the side SD1b exists between the side surface SM2 and the side surface SM3, the side SD1c exists between the side surface SM3 and the side surface SM4, and the side SD1d.
- the side surface SM4 and the side surface SM1 exists between the side surface SM1 and the side surface SM2
- the path where dielectric breakdown such as electrostatic breakdown occurs between the semiconductor chip CP2 and the die pad DP is not in the bonding material BD2, but mainly in the bonding material BD2 and the sealing portion MR.
- the interface (boundary surface) KM was found to be KM. That is, in FIG. 38, the leak path between the semiconductor chip CP2 and the die pad DP is the interface KM between the bonding material BD2 and the sealing portion MR, and the bonding sandwiched between the semiconductor chip CP2 and the die pad DP.
- the inside of the material BD2 is unlikely to be a leak path.
- the electric field tends to concentrate in the semiconductor chip CP2.
- the electric field tends to concentrate on the side SD2 of the semiconductor chip CP2, and in particular, the electric field tends to concentrate on the lower end LE of the side SD2 of the semiconductor chip CP2.
- the lower end LE of the side SD2 of the semiconductor chip CP2 is shown in FIG. 36 and FIG. 38.
- the distance to the interface KM can be increased.
- the gap between the bonding material BD2 and the sealing portion MR is between the lower end LE of the side SD2 of the semiconductor chip CP2 and the die pad DP. It is possible to suppress or prevent the occurrence of dielectric breakdown such as electrostatic breakdown through the interface KM. For this reason, the breakdown voltage between the semiconductor chip CP2 and the die pad DP can be improved. Therefore, the reliability of the semiconductor device PKG can be improved.
- the length L2 of the portion covered with the bonding material BD2 in the side SD2 of the semiconductor chip CP2 is increased, the side of the semiconductor chip CP2 along the interface KM between the bonding material BD2 and the sealing portion MR.
- the distance L3 from SD2 to the die pad DP can be increased. That is, even if the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is changed, the angle ⁇ formed by the interface KM and the upper surface of the die pad DP does not change much.
- the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is used. It is necessary to increase the length L2 of the covered portion. That is, if the length L2 is increased, the distance L3 from the side SD2 of the semiconductor chip CP2 along the interface KM to the die pad DP can be increased, so that a high voltage is applied between the semiconductor chip CP2 and the die pad DP. When this is done, it is possible to suppress or prevent the occurrence of dielectric breakdown such as electrostatic breakdown between the semiconductor chip CP2 and the die pad DP via the interface KM. For this reason, the breakdown voltage between the semiconductor chip CP2 and the die pad DP can be improved. Therefore, the reliability of the semiconductor device PKG can be improved.
- the withstand voltage (insulation withstand voltage per unit distance) of the material constituting the bonding material BD2 is higher than the withstand voltage (withstand voltage per unit distance) of the material constituting the sealing portion MR. This is because it is necessary to select a material for the sealing part MR in consideration of the ease of forming the sealing part MR in the sealing process (molding process).
- the bonding material BD2 is not a sealing body, so that it is easy to devise the material of the bonding material BD2, and it is possible to select a material having a high withstand voltage.
- the side SD2 of the semiconductor chip CP2 that tends to concentrate an electric field is higher between the semiconductor chip CP2 and the die pad DP than the side SD2 of the semiconductor chip CP2 and the die pad DP that are covered with the bonding material BD2 having a high breakdown voltage.
- a voltage it is easy to suppress the occurrence of dielectric breakdown such as electrostatic breakdown between the semiconductor chip CP2 and the die pad DP.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is increased, the side SD2 of the semiconductor chip CP2 on which the electric field tends to concentrate is covered with the bonding material BD2 having a high withstand voltage.
- the ratio of the parts can be increased.
- increasing the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is effective in increasing the breakdown voltage between the semiconductor chip CP2 and the die pad DP.
- the bonding material BD1 which is a die bonding material for the semiconductor chip CP1 has conductivity. If a part of the conductive die bonding material adheres to the surface of the semiconductor chip CP1, there is a risk of causing a short circuit between the pad electrodes P1 of the semiconductor chip CP1. This reduces the reliability of the semiconductor device PKG and reduces the manufacturing yield of the semiconductor device PKG. For this reason, it is necessary to prevent the conductive die bonding material from adhering to the surface of the semiconductor chip CP1 as much as possible.
- the length L1 of the portion covered with the bonding material BD1 in the side SD1 of the semiconductor chip CP1 is preferable to reduce the length L1 of the portion covered with the bonding material BD1 in the side SD1 of the semiconductor chip CP1. This is because, as the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1 increases, the possibility that a part of the conductive bonding material BD1 adheres to the surface of the semiconductor chip CP1 increases. Because it becomes. Therefore, by reducing the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1, a part of the conductive bonding material BD1 may adhere to the surface of the semiconductor chip CP1. Can be lowered.
- an insulating die bonding material is used for the semiconductor chip CP2.
- the die bonding material BD2 adheres to the surface of the semiconductor chip CP2
- the die bonding material is insulative, so that an electrical short circuit between the pad electrodes P2 occurs. it dose not connect.
- a part of the insulating die bonding material adhering to the surface of the semiconductor chip CP2 causes a problem as compared to a part of the conductive die bonding material adhering to the surface of the semiconductor chip CP1. Hateful.
- the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is larger than the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1.
- the length L2 of the portion covered with is increased (that is, L2> L1).
- the semiconductor device PKG of the present embodiment includes a conductive die pad DP (chip mounting portion) and a semiconductor mounted on the die pad DP via an insulating bonding material BD2 (first bonding material).
- a chip CP2 (first semiconductor chip) and a semiconductor chip CP1 (second semiconductor chip) mounted on the die pad DP via a conductive bonding material BD1 (second bonding material) are provided.
- the semiconductor device PKG further includes a sealing portion MR (sealing body) that seals at least a part of the semiconductor chip CP1, the semiconductor chip CP2, and the die pad DP.
- the semiconductor chip CP1 has a back electrode BE, and the back electrode BE of the semiconductor chip CP1 is electrically connected to the die pad DP via the bonding material BD1. Then, the length L2 (first length) of the portion covered with the bonding material BD2 in the side SD2 (first side) formed by intersecting the first side surface and the second side surface of the semiconductor chip CP2. Is the length L1 (second length) of the portion covered with the bonding material BD1 in the side SD1 (second side) formed by intersecting the third side surface and the fourth side surface of the semiconductor chip CP1. (L2> L1).
- the semiconductor chip CP2 mounted with the insulating bonding material BD2 increases the breakdown voltage between the semiconductor chip CP2 and the die pad DP. Therefore, the length L2 is made larger than the length L1.
- the semiconductor chips CP1 and CP2 mounted on the common die pad DP for the semiconductor chip CP1 mounted with the conductive bonding material BD1, a part of the conductive bonding material BD1 adheres to the surface of the semiconductor chip CP1. In order to prevent this, the length L1 is made smaller than the length L2.
- the withstand voltage between the semiconductor chip CP2 and the die pad DP can be improved, so that it is possible to suppress or prevent the occurrence of dielectric breakdown such as electrostatic breakdown between the semiconductor chip CP2 and the die pad DP.
- the semiconductor chip CP2 uses an insulating die bonding material, so it is important to improve the breakdown voltage between the semiconductor chip CP1 and the die pad DP. Since a conductive die bonding material is used, it is important to prevent the conductive die bonding material from adhering to the surface of the semiconductor chip CP1.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is larger than the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1 (
- the semiconductor chip CP1 is mounted on the common die pad DP with a conductive die bonding material and the semiconductor chip CP2 is mounted with an insulating die bonding material
- the semiconductor chip CP2 is mounted between the semiconductor chip CP2 and the die pad DP
- the technical idea of the present embodiment that the relationship of L2> L1 should be satisfied cannot be reached. This is because it is a general idea to prevent the die bonding material from adhering to the surface of the semiconductor chip, whether the die bonding material is conductive or insulating.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 is made as small as possible. This is a fair idea.
- the inventor has the semiconductor chip CP2 and the die pad DP.
- the length L2 is increased.
- it is more conductive than the insulating die bonding material attached to the surface of the semiconductor chip.
- the length L1 is reduced in consideration of the possibility that a major problem such as a short circuit between the pad electrodes P1 may occur when a sticking die bonding material adheres.
- the side SD2 of the semiconductor chip CP2 has four sides SD2a, SD2b, SD2c, and SD2d
- the side SD1 of the semiconductor chip CP1 has four sides SD1a, SD1b, SD1c, and SD1d.
- the withstand voltage is lowered between the side and the die pad DP. End up.
- the length L2 of the portion covered with the bonding material BD2 is large in any of the four sides SD2a, SD2b, SD2c, SD2d of the semiconductor chip CP2, and thereby the semiconductor chip CP2 and the die pad DP It becomes possible to accurately increase the breakdown voltage between the two.
- the conductive surface is formed on the surface of the semiconductor chip CP1.
- a part of the bonding material BD1 may adhere.
- it is desirable that the length L1 of the portion covered with the bonding material BD1 is small, so that the surface of the semiconductor chip CP1 is electrically conductive. It is possible to accurately prevent a part of the adhesive bonding material BD1 from adhering.
- L2> L1 is preferably satisfied by any combination of the four sides SD2a, SD2b, SD2c, SD2d of the semiconductor chip CP2 and the four sides SD1a, SD1b, SD1c, SD1d of the semiconductor chip CP1. .
- the length L2 of the portion covered with the bonding material BD2 on the side SD2a, the length L2 of the portion covered with the bonding material BD2 on the side SD2b, and the bonding material BD2 on the side SD2c are covered.
- the smallest value is referred to as a minimum value L2min.
- the length L1 of the portion covered with the bonding material BD1 on the side SD1a, the length L1 of the portion covered with the bonding material BD1 on the side SD1b, and the bonding material BD1 on the side SD1c are covered.
- the largest value of the length L1 of the portion and the length L1 of the portion covered with the bonding material BD1 on the side SD1d is referred to as a maximum value L1max.
- the minimum value L2min is preferably larger than the maximum value L1max (that is, L2min> L1max). That is, the minimum value L2min of the length L2 of the portion covered with the bonding material BD2 on the sides SD2a, SD2b, SD2c, SD2d of the semiconductor chip CP2 is the bonding material BD1 on the sides SD1a, SD1b, SD1c, SD1d of the semiconductor chip CP1. It is preferable that the length L1 of the covered portion is larger than the maximum value L1max (L2min> L1max).
- the breakdown voltage between the semiconductor chip CP2 and the die pad DP can be improved accurately, and a part of the conductive bonding material BD1 can be accurately suppressed or adhered to the surface of the semiconductor chip CP1. Can be prevented. Therefore, it is possible to accurately improve the overall reliability of the semiconductor device PKG.
- the withstand voltage between the semiconductor chip CP2 and the die pad DP can be improved by increasing the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is not less than 1/2 of the thickness T2 of the semiconductor chip CP2 (that is, L2 ⁇ T2 ⁇ 1/2) is preferable (see FIG. 38).
- the length L2 of the portion covered with the bonding material BD2 is equal to or greater than 1/2 of the thickness T2 of the semiconductor chip CP2 (that is, L2 ⁇ (T2 ⁇ 1/2) is more preferable. That is, it is more preferable if the minimum value L2min is equal to or greater than 1 ⁇ 2 of the thickness T2 of the semiconductor chip CP2 (that is, L2min ⁇ T2 ⁇ 1/2).
- the withstand voltage between the semiconductor chip CP2 and the die pad DP can be improved more accurately, so that it is possible to more accurately prevent dielectric breakdown such as electrostatic breakdown between the semiconductor chip CP2 and the die pad DP. It can be suppressed or prevented. Therefore, the reliability of the semiconductor device PKG can be improved more accurately.
- the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1 is preferably less than 1 ⁇ 2 of the thickness T1 of the semiconductor chip CP1 (ie, L1 ⁇ T1 ⁇ 1/2). It is more preferable that the thickness is equal to or less than 1 ⁇ 4 of the thickness T1 of the semiconductor chip CP1 (that is, L1 ⁇ T1 ⁇ 1/4) (see FIG. 39).
- the length L1 of the portion covered with the bonding material BD1 is less than 1 ⁇ 2 of the thickness T1 of the semiconductor chip CP1 (that is, L1 ⁇ (T1 ⁇ 1/2) is more preferable, and it is more preferable if it is 1/4 or less of the thickness T1 of the semiconductor chip CP1 (that is, L1 ⁇ T1 ⁇ 1/4).
- the maximum value L1max is less than 1 ⁇ 2 of the thickness T1 of the semiconductor chip CP1 (that is, L1max ⁇ T1 ⁇ 1 ⁇ 2), and is 1 ⁇ 4 or less of the thickness T1 of the semiconductor chip CP1 (that is, L1max).
- ⁇ T1 ⁇ 1/4) is more preferable.
- this embodiment has a very large effect when applied when the pressure resistance (pressure resistance per unit distance) of the bonding material BD2 is larger than the pressure resistance (pressure resistance per unit distance) of the sealing portion MR.
- this embodiment is applied when the breakdown voltage of the sealing portion MR (withstand pressure per unit distance) is smaller than that of the bonding material BD2 (withstand pressure per unit distance), the effect is extremely large. .
- the sealing portion MR it is necessary to select a material in consideration of the ease of forming the sealing portion MR in the sealing process (molding process), and the material of the sealing portion MR is changed in consideration of the withstand voltage.
- the bonding material BD2 is not a sealed body, it is easy to devise the material of the bonding material BD2, and it is possible to select a material having a high withstand voltage. Therefore, when attention is paid to the pressure resistance of each member of the semiconductor device PKG, it is assumed that the pressure resistance of the sealing portion MR (pressure resistance per unit distance) is smaller than the pressure resistance of the bonding material BD2 (pressure resistance per unit distance).
- the breakdown voltage (breakdown voltage per unit distance) of the sealing portion MR is, for example, about 10 to 30 kV / mm, and the breakdown voltage (breakdown voltage per unit distance) of the bonding material BD2 is, for example, about 80 to 150 kV / mm.
- the withstand voltage (withstand pressure per unit distance) of the sealing portion MR is smaller than the withstand pressure (withstand pressure per unit distance) of the bonding material BD2, electrostatic breakdown occurs at the interface KM between the bonding material BD2 and the sealing portion MR. Such a dielectric breakdown is likely to occur.
- the length L2 of the portion covered with the bonding material BD2 in the side SD2 of the semiconductor chip CP2 is increased as described above, so that the space between the bonding material BD2 and the sealing portion MR is increased. It is possible to suppress or prevent the occurrence of dielectric breakdown such as electrostatic breakdown due to the interface KM as a leak path.
- FIG. 40 shows a table showing an example of the effect of the present embodiment.
- Sample A and sample B shown in FIG. 40 correspond to the case where the state of the bonding material BD2 is changed in the semiconductor device PKG. That is, in both sample A and sample B, the thickness T2 of the semiconductor chip CP2 is about 400 ⁇ m.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is about 60 ⁇ m, and the distance L3 is also small, reflecting that the length L2 is small.
- the distance L3 is about 85 ⁇ m.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is 250 ⁇ m, and the distance L3 is large reflecting the large length L2, and the distance L3 is about 320 ⁇ m.
- the withstand voltage between the semiconductor chip CP2 and the die pad DP was about 1300V, but in the case of sample B, even if 5000V is applied, the insulation between the semiconductor chip CP2 and the die pad DP is insulated. No breakdown occurred, and the withstand voltage between the semiconductor chip CP2 and the die pad DP was 5000V or higher.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is preferably increased to be 1/2 or more of the thickness T2 of the semiconductor chip CP2 (L2 ⁇ T2 ⁇ 1). / 2), the dielectric strength between the semiconductor chip CP2 and the die pad DP can be improved, and the reliability of the semiconductor device can be improved.
- the required breakdown voltage (ESD standard) between the semiconductor chip CP2 and the die pad DP is V1
- the breakdown voltage per unit distance of the sealing portion MR is V2
- the breakdown voltage per unit distance of the bonding material BD2 is V3.
- the distance (interval) between the chip CP2 and the die pad DP is L4
- the following formula (1) V2 ⁇ L3 ⁇ V1
- the following equation (2) V3 ⁇ L4 ⁇ V1 Formula (2)
- the distance (interval) L4 between the semiconductor chip CP2 and the die pad DP also corresponds to the thickness of the bonding material BD2 at a portion interposed between the die pad DP and the semiconductor chip CP2.
- the distance L3 is preferably about 150 ⁇ m or more. That is, the length L2 may be increased until the distance L3 is about 150 ⁇ m or more. Accordingly, since the above formula (1) is satisfied, the withstand voltage between the semiconductor chip CP2 and the die pad DP through the interface KM between the semiconductor chip CP2 and the die pad DP can be set to the required withstand voltage V1 or more. .
- the distance L4 is preferably about 23 ⁇ m or more. That is, it is preferable that the thickness of the bonding material BD2 at a portion interposed between the die pad DP and the semiconductor chip CP2 is about 23 ⁇ m or more.
- the breakdown voltage between the semiconductor chip CP2 and the die pad DP via the bonding material BD2 between the semiconductor chip CP2 and the die pad DP is set to be equal to or higher than the required breakdown voltage V1. it can.
- the breakdown voltage between the semiconductor chip CP2 and the die pad DP is set to be equal to or higher than the required breakdown voltage V1. be able to.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is set to be longer than the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1.
- step S2a After supplying the insulating bonding material BD2 on the die pad DP in step S2a, the semiconductor chip CP2 is mounted on the die pad DP via the bonding material BD2 in step S2b.
- the bonding material BD2 is also supplied to the position where the four corners of the semiconductor chip CP2 overlap in plan view. (See FIGS. 21 and 29).
- step S2b shows the state immediately after performing step S2a, and therefore step S2b has not yet been performed.
- FIG. 21 the case where the bonding material BD2 is supplied onto the die pad DP from the nozzle for supplying the bonding material is shown.
- the bonding material BD2 is supplied onto the die pad DP by the printing method. The case is shown. 21 and 29, the position where the semiconductor chip CP2 is mounted in step S2b is indicated by a dotted line.
- the bonding material BD2 is supplied onto the die pad DP from the nozzle in step S2a, the bonding material BD2 is locally disposed on the upper surface of the die pad DP. Therefore, when supplying the bonding material BD2 from the nozzle, it is preferable to supply (arrange) the bonding material BD2 at a plurality of locations on the upper surface of the die pad DP. In the case of FIG. 21, on the upper surface of the die pad DP, The bonding material BD2 is supplied (arranged) at nine locations.
- step S2b semiconductor chip CP2 mounting region
- step S2a bonding material BD2 protrudes from the region where the semiconductor chip CP2 is to be mounted in step S2b (semiconductor chip CP2 mounting region), and the four corners of the semiconductor chip CP2 to be mounted later in plan view. Also in the overlapping position, the bonding material BD2 is supplied (arranged) in step S2a.
- the region where the semiconductor chip CP2 is to be mounted corresponds to a region that overlaps the semiconductor chip CP2 in plan view when the semiconductor chip CP2 is mounted on the die pad DP in step S2b, and in FIG. 21 and FIG. It corresponds to the area surrounded by.
- the bonding material BD2 is supplied onto the die pad DP by the printing method in step S2a, the bonding material BD2 is not locally disposed on the upper surface of the die pad DP, but relatively Arranged over a large area.
- the region where the bonding material BD2 is supplied (arranged) includes the region where the semiconductor chip CP2 is to be mounted in step S2b (semiconductor chip CP2 mounting region). .
- step S2a a part of the bonding material BD2 protrudes from the region where the semiconductor chip CP2 is to be mounted, and the bonding material BD2 is supplied (arranged) in step S2a also at a position where the four corners of the semiconductor chip CP2 to be mounted later overlap in plan view.
- step S2b the semiconductor chip CP2 is mounted at the position indicated by the dotted line in FIGS.
- step S2b the semiconductor chip CP2 is mounted on the die pad DP in a state in which the bonding material BD2 is already disposed at a position overlapping the four corners of the semiconductor chip CP2 in plan view. That is, when the semiconductor chip CP2 is mounted on the die pad DP in step S2b, the bonding material BD2 is supplied in advance in step S2a also to the position where the four corners of the semiconductor chip CP2 overlap in plan view.
- the lower ends LE of the four sides SD2a, SD2b, SD2c, SD2d of the semiconductor chip CP2 are buried in the bonding material BD2 disposed on the die pad DP. It will be. Since the lower portions of the four sides SD2a, SD2b, SD2c, SD2d of the semiconductor chip CP2 are buried in the bonding material BD2 and covered with the bonding material BD2, the sides SD2a, SD2b of the semiconductor chip CP2 are covered. , SD2c, SD2d, the length L2 of the portion covered with the bonding material BD2 can be increased. Accordingly, the breakdown voltage between the semiconductor chip CP2 and the die pad DP can be improved, and the occurrence of dielectric breakdown such as electrostatic breakdown can be suppressed or prevented between the semiconductor chip CP2 and the die pad DP. .
- step S2c after supplying the conductive bonding material BD1 on the die pad DP in step S2c, the semiconductor chip CP1 is mounted on the die pad DP via the bonding material BD1 in step S2d.
- the bonding material BD1 is not supplied to the position where the four corners of the semiconductor chip CP1 overlap in plan view ( FIG. 25 and FIG. 30).
- 25 and 30 show the state immediately after performing step S2c, and therefore step S2d has not been performed yet.
- 25 shows the case where the bonding material BD1 is supplied onto the die pad DP from the nozzle for supplying the bonding material.
- the bonding material BD1 is supplied onto the die pad DP by the printing method. The case is shown.
- the position where the semiconductor chip CP1 is mounted in step S2d is indicated by a dotted line.
- the bonding material BD1 since the bonding material BD1 is supplied onto the die pad DP from the nozzle in step S2c, the bonding material BD1 is locally disposed on the upper surface of the die pad DP. For this reason, when supplying the bonding material BD1 from the nozzle, it is preferable to supply (place) the bonding material BD1 at a plurality of locations on the upper surface of the die pad DP. In the case of FIG. 25, on the upper surface of the die pad DP, The bonding material BD1 is supplied (arranged) at five locations. At this time, the bonding material BD1 does not protrude from the region where the semiconductor chip CP1 is to be mounted (semiconductor chip CP1 mounting region) in step S2d.
- the region where the bonding material BD1 is supplied (arranged) is included in the region where the semiconductor chip CP1 is to be mounted.
- the bonding material BD1 is supplied (arranged) inside the region where the semiconductor chip CP1 is to be mounted, and the bonding material BD1 is not supplied (arranged) to the outer periphery of the region where the semiconductor chip CP1 is to be mounted. Therefore, in the case of FIG. 25, the bonding material BD1 is not supplied (arranged) in step S2c at the position where the four corners of the semiconductor chip CP1 to be mounted later in plan view overlap.
- the region where the semiconductor chip CP1 is to be mounted corresponds to a region that overlaps the semiconductor chip CP1 in a plan view when the semiconductor chip CP1 is mounted on the die pad DP in step S2d, and in FIG. 25 and FIG. It corresponds to the area surrounded by.
- the bonding material BD1 since the bonding material BD1 is supplied onto the die pad DP by the printing method in step S2c, the bonding material BD1 is not locally disposed on the upper surface of the die pad DP, but relatively Arranged over a large area.
- the bonding material BD1 is supplied (arranged) on the die pad DP by the printing method in step S2c, the bonding material BD1 is removed from the region where the semiconductor chip CP1 is to be mounted (semiconductor chip CP1 mounting region) in step S2d. I try not to stick out. That is, in plan view, the region where the bonding material BD1 is supplied (arranged) is included in the region where the semiconductor chip CP1 is to be mounted.
- step S2c the bonding material BD1 is supplied (arranged) inside the region where the semiconductor chip CP1 is to be mounted, and the bonding material BD1 is not supplied (arranged) to the outer periphery of the region where the semiconductor chip CP1 is to be mounted. For this reason, also in FIG. 30, the bonding material BD1 is not supplied (arranged) in step S2c to the position where the four corners of the semiconductor chip CP1 to be mounted later in a plan view overlap.
- FIG. 25 and FIG. 30 are common in that the four corners of the semiconductor chip CP1 mounting scheduled area indicated by the dotted line do not overlap with the bonding material BD1 supplied on the die pad DP in step S2c in plan view. It is.
- step S2d the semiconductor chip CP1 is mounted at the position indicated by the dotted line in FIGS.
- step S2d the semiconductor chip CP1 is mounted on the die pad DP in a state where the bonding material BD1 is not disposed at a position overlapping the four corners of the semiconductor chip CP1 in plan view.
- the bonding material BD1 is not supplied in step S2c to the position where the four corners of the semiconductor chip CP1 overlap in plan view. It is further preferable that the region where the bonding material BD2 is supplied (arranged) on the die pad DP in step S2c is included in the region where the semiconductor chip CP2 is to be mounted.
- the bonding material BD1 is unlikely to wet the side surfaces SM1, SM2, SM3, SM4 and the sides SD1a, SD1b, SD1c, SD1d of the semiconductor chip CP1.
- Side surfaces SM1, SM2, SM3, and SM4 and sides SD1a, SD1b, SD1c, and SD1d of CP1 are not easily covered with the bonding material BD1.
- the length L1 of the portion covered with the bonding material BD1 on each of the sides SD1a, SD1b, SD1c, SD1d of the semiconductor chip CP1 can be reduced, and one surface of the conductive bonding material BD1 is formed on the surface of the semiconductor chip CP1. It can suppress or prevent that a part adheres.
- the bonding material BD2 is also supplied in step S2a to the position where the four corners of the semiconductor chip CP2 overlap in plan view. I have to.
- the length L2 of the portion covered with the bonding material BD2 in each of the sides SD2a, SD2b, SD2c, SD2d of the semiconductor chip CP2 can be increased.
- the bonding material BD1 is not supplied in step S2c to the position where the four corners of the semiconductor chip CP1 overlap in plan view.
- the region where the bonding material BD2 is supplied (arranged) on the die pad DP in step S2c is a region that overlaps the semiconductor chip CP2 in plan view when the semiconductor chip CP2 is mounted on the die pad DP in step S2b (that is, mounting the semiconductor chip CP2). It is more preferable if it is included in the planned area. Thereby, the length L1 of the part covered with the bonding material BD1 in each of the sides SD1a, SD1b, SD1c, SD1d of the semiconductor chip CP1 can be reduced.
- the length L2 of the portion covered with the bonding material BD2 on the side SD2 of the semiconductor chip CP2 is larger than the length L1 of the portion covered with the bonding material BD1 on the side SD1 of the semiconductor chip CP1 (L2> L1).
- the structure can be realized easily and accurately.
- this embodiment is particularly effective when a paste-type bonding material is used for both the bonding material BD1 and the bonding material BD2. That is, the effect is particularly great when a conductive paste-type bonding material is used as the conductive bonding material BD1 and an insulating paste-type bonding material is used as the insulating bonding material BD2.
- both of the bonding materials BD1 and BD2 are paste-type bonding materials
- both of the bonding materials BD1 and BD2 have a property that the side surface of the semiconductor chip can be easily applied.
- the coating amount of the bonding material BD1 and the coating amount of the bonding material BD2 are approximately the same.
- both the lengths L1 and L2 are small, as described above, the small length L2 lowers the withstand voltage between the semiconductor chip CP2 and the die pad DP, and the static between the semiconductor chip CP2 and the die pad DP.
- both the lengths L1 and L2 are large, as described above, a part of the conductive bonding material BD1 adheres to the surface of the semiconductor chip CP1 because the length L1 is large as described above. There is concern. These deteriorate the overall reliability of the semiconductor device.
- the bonding materials BD1 and BD2 both have a property that the side surface of the semiconductor chip is easily painted.
- the coating amount is increased for the insulating bonding material BD2, and the coating amount is suppressed and the coating amount is decreased for the conductive bonding material BD1.
- the length L2 is made larger than the length L1 (L2> L1). For this reason, the length L2 can be increased and the length L1 can be decreased.
- the length L2 can be set to 1/2 or more of the thickness T2 of the semiconductor chip CP2.
- the length L1 is set to be equal to that of the semiconductor chip CP1.
- the length L1 can be less than 1 ⁇ 2 of the thickness T1, and more preferably, the length L1 can be 1 ⁇ 4 or less of the thickness T1 of the semiconductor chip CP1.
- the length L2 since the length L2 is large, the withstand voltage between the semiconductor chip CP2 and the die pad DP is increased, and electrostatic breakdown between the semiconductor chip CP2 and the die pad DP is suppressed or prevented.
- the length L1 since the length L1 is small, it is possible to suppress or prevent a part of the conductive bonding material BD1 from adhering to the surface of the semiconductor chip CP1. Therefore, the overall reliability of the semiconductor device can be improved.
- the conductive bonding material BD1 is a conductive paste type bonding material such as silver (Ag) paste
- the side surfaces SM1, SM2, SM3, and SM4 of the semiconductor chip CP1 and the sides SD1a, SD1b, SD1c, and SD1d are bonded. Since the material BD1 tends to wet up, a part of the conductive bonding material BD1 may adhere to the surface of the semiconductor chip CP1.
- the conductive bonding material BD1 is a conductive paste type bonding material such as silver (Ag) paste
- the side surfaces SM1, SM2, SM3, and SM4 of the semiconductor chip CP1 and the sides SD1a, SD1b, SD1c, and SD1d It is particularly important to prevent the bonding material BD1 from getting wet. Therefore, when the bonding material BD1 is a conductive paste type bonding material, when the semiconductor chip CP1 is mounted on the die pad DP in step S2d, the bonding is performed in step S2c at a position where the four corners of the semiconductor chip CP1 overlap in plan view. It is very important that the material BD1 is not supplied.
- the bonding material BD1 is prevented from protruding from the region where the semiconductor chip CP1 is to be mounted, and the region where the bonding material BD1 is supplied (arranged) is the semiconductor chip. It is preferable to be included in the CP1 mounting planned area. By doing so, even if the bonding material BD2 is a conductive paste type bonding material that easily wets the side surface of the semiconductor chip CP1, the bonding material BD2 is the side surface SM1, SM2, SM3, SM4 or the side SD1a of the semiconductor chip CP1. , SD1b, SD1c, SD1d can be prevented from getting wet. Thereby, it is possible to accurately suppress or prevent a part of the conductive bonding material BD1 from adhering to the surface of the semiconductor chip CP1.
- solder material As the conductive bonding material BD1.
- a solder material it is necessary to provide a flux cleaning step after solder reflow. This means an increase in the number of assembly processes (number of manufacturing processes).
- lead-rich high melting point solder having a melting point higher than the reflow temperature at the time of mounting. This means that it goes against the lead-free semiconductor device PKG.
- a conductive paste type bonding material such as a silver (Ag) paste rather than a solder material as the conductive bonding material BD1.
- a conductive paste-type bonding material such as silver (Ag) paste, the number of assembly steps (number of manufacturing steps) can be reduced compared to the case of using a solder material, and an environmentally friendly semiconductor device PKG can be realized. Can do.
Abstract
Description
本発明の一実施の形態の半導体装置を図面を参照して説明する。
図1は、本発明の一実施の形態である半導体装置PKGの上面図であり、図2~図4は、半導体装置PKGの平面透視図であり、図5は、半導体装置PKGの下面図(裏面図)であり、図6~図8は、半導体装置PKGの断面図である。図2には、封止部MRを透視したときの半導体装置PKGの上面側の平面透視図が示されている。また、図3は、図2において、更にワイヤBWを透視(省略)したときの半導体装置PKGの上面側の平面透視図が示されている。また、図4は、図3において、更に半導体チップCP1,CP2を透視(省略)したときの半導体装置PKGの上面側の平面透視図が示されている。なお、図1~図4では、半導体装置PKGの向きは同じである。また、図2~図4では、封止部MRの外周の位置を点線で示してある。また、図1、図2および図5のA-A線の位置での半導体装置PKGの断面が、図6にほぼ対応し、図1、図2および図5のB-B線の位置での半導体装置PKGの断面が、図7にほぼ対応し、図1、図2および図5のC-C線の位置での半導体装置PKGの断面が、図8にほぼ対応している。また、図9は、図2の一部を拡大した部分拡大平面透視図である。
次に、上記図1~図9に示される半導体装置PKGの製造工程について説明する。図10は、上記図1~図9に示される半導体装置PKGの製造工程を示すプロセスフロー図である。図11~図15は、半導体装置PKGの製造工程中の断面図である。なお、図11~図15には、上記図6に相当する断面が示されている。
上記ステップS2のダイボンディング工程の詳細について、図面を参照して説明する。図16~図19は、上記図10のプロセスフローのうち、ステップS2のダイボンディング工程の詳細を示すプロセスフロー図である。また、図20~図30は、半導体装置PKGの製造工程中の平面図または断面図である。図20~図30のうち、図20、図21、図23、図25、図27、図29および図30は、平面図であり、図22、図24、図26および図28は、上記図6に相当する断面が示されている。なお、図20のA1-A1線の断面図が、上記図11に対応し、図21のA1-A1線の断面図が、図22に対応し、図23のA1-A1線の断面図が、図24に対応し、図25のA1-A1線の断面図が、図26に対応し、図27のA1-A1線の断面図が、図28に対応している。
次に、図31を参照しながら、半導体装置PKGの回路構成について説明する。図31は、半導体装置PKGの回路図(回路ブロック図)である。
次に、半導体チップCP1の構造について説明する。
図33は、本発明者が検討した検討例の半導体装置(半導体パッケージ)PKG101の断面図であり、上記図6に相当する断面図が示されている。
そこで、本実施の形態の半導体装置PKGでは、半導体チップCP1と半導体チップCP2とを共通のダイパッドDP上に搭載している。
半導体チップCP2とダイパッドDPとの間には、絶縁性の接合材BD2が介在しており、電気的に絶縁されているが、半導体装置PKGの信頼性を高めるためには、半導体チップCP2とダイパッドDPとの間の耐圧を高めることが望ましい。例えば、半導体チップCP2とダイパッドDPとの間の耐圧が低いと、半導体チップCP2とダイパッドDPとの間で、静電気放電(ESD:Electro-Static Discharge)による破壊である静電破壊が生じる可能性がある。静電破壊が生じないようにするためには、半導体チップCP2とダイパッドDPとの間の耐圧をできるだけ高めることが望ましい。なお、耐圧とは、絶縁耐圧を意味する。
図34および図35は、半導体装置PKGの一部を拡大して示す平面透視図である。図34には、ダイパッドDP上に接合材BD2を介して搭載された半導体チップCP2が拡大して示され、また、図35には、ダイパッドDP上に接合材BD1を介して搭載された半導体チップCP1が拡大して示されている。但し、図34および図35では、上記図3と同様に、封止部MRおよびワイヤBWを透視している。このため、図34では、半導体チップCP2と接合材BD2が図示され、図35では、半導体チップCP1と接合材BD1が図示されている。
一方、半導体チップCP1については、導電性の接合材BD1を介してダイパッドDP上に搭載されているため、半導体チップCP1の裏面電極BEとダイパッドDPとは、導電性の接合材BD1を介して導通しており、半導体チップCP1とダイパッドDPとの間で静電破壊のような絶縁破壊が生じることはない。このため、半導体チップCP1とダイパッドDPとの間の耐圧を気にする必要はない。従って、半導体チップCP1の辺SD1における接合材BD1で覆われた部分の長さL1を大きくする必要はない。
そこで、本実施の形態では、主要な特徴のうちの一つとして、半導体チップCP1の辺SD1における接合材BD1で覆われた部分の長さL1よりも、半導体チップCP2の辺SD2における接合材BD2で覆われた部分の長さL2を大きくしている(すなわちL2>L1)。
V2×L3≧V1 ・・・式(1)
と、次の式(2)
V3×L4≧V1 ・・・式(2)
とが成り立つことが好ましい。なお、半導体チップCP2とダイパッドDPとの間の距離(間隔)L4は、ダイパッドDPと半導体チップCP2との間に介在する部分の接合材BD2の厚みにも対応している。
3 p型の半導体領域
4 n+型の半導体領域
5 p+型の半導体領域
6 溝
7 ゲート絶縁膜
8 ゲート電極
9,11 層間絶縁膜
10,12 プラグ
13 保護膜
14 開口部
BAT 電源
BD1,BD2 接合材
BE 裏面電極
BW ワイヤ
CLC 制御回路
CP1,CP2 半導体チップ
DP ダイパッド
GM 銀メッキ層
KM 界面
LD リード
LE 下端
LF リードフレーム
LOD 負荷
M1,M2 配線
M1S,M2S ソース配線
MR 封止部
MRa 上面
MRb 下面
MRc1,MRc2,MRc3,MRc4 側面
P1,P2 パッド電極
P1S ソース用パッド電極
PKG 半導体装置
Q1 パワーMOSFET
Q2 センスMOSFET
REG レギュレータ
SM1,SM2,SM3,SM4,SM5,SM6,SM7,SM8 側面
SD1,SD1a,SD1b,SD1c,SD1d 辺
SD2,SD2a,SD2b,SD2c,SD2d 辺
TL 吊りリード
Claims (20)
- 導電性を有するチップ搭載部と、
前記チップ搭載部上に、絶縁性を有する第1接合材を介して搭載された第1半導体チップと、
前記チップ搭載部上に、導電性を有する第2接合材を介して搭載された第2半導体チップと、
前記第1半導体チップ、前記第2半導体チップ、および前記チップ搭載部の少なくとも一部を封止する封止体と、
を備える半導体装置であって、
前記第2半導体チップは、裏面電極を有し、前記第2半導体チップの前記裏面電極が、前記第2接合材を介して前記チップ搭載部と電気的に接続され、
前記第1半導体チップの第1側面と第2側面とが交差して形成される第1の辺における、前記第1接合材で覆われた部分の第1の長さは、前記第2半導体チップの第3側面と第4側面とが交差して形成される第2の辺における、前記第2接合材で覆われた部分の第2の長さよりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
複数のリードと、
複数のワイヤと、
を更に有し、
前記封止体は、前記複数のリードのそれぞれの一部と、前記複数のワイヤとを封止し、
前記複数のワイヤは、前記第1半導体チップの複数の第1パッド電極と前記複数のリードのうちの複数の第1リードとを電気的に接続する複数の第1ワイヤと、前記第2半導体チップの複数の第2パッド電極と前記複数のリードのうちの複数の第2リードとを電気的に接続する複数の第2ワイヤと、を含む、半導体装置。 - 請求項1記載の半導体装置において、
前記第1の長さは、前記第1半導体チップの厚みの1/2以上である、半導体装置。 - 請求項3記載の半導体装置において、
前記第2の長さは、前記第2半導体チップの厚みの1/2未満である、半導体装置。 - 請求項4記載の半導体装置において、
前記第2の長さは、前記第2半導体チップの厚みの1/4以下である、半導体装置。 - 請求項1記載の半導体装置において
前記第1接合材の耐圧は、前記封止体の耐圧よりも大きい、半導体装置。 - 請求項1記載の半導体装置において
前記第1接合材は、絶縁性ペースト型接合材である、半導体装置。 - 請求項7記載の半導体装置において
前記第2接合材は、導電性ペースト型接合材である、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体チップは、パワートランジスタを含み、
前記第1半導体チップは、前記第2半導体チップを制御する、半導体装置。 - 請求項1記載の半導体装置において、
前記チップ搭載部の上面の一部に銀メッキ層が形成され、
前記第2半導体チップは、前記チップ搭載部の前記銀メッキ層上に、前記第2接合材を介して搭載され、
前記第1半導体チップは、前記銀メッキ層が形成されていない領域の前記チップ搭載部上に、前記第1接合材を介して搭載されている、半導体装置。 - (a)導電性を有するチップ搭載部上に、絶縁性を有する第1接合材を介して第1半導体チップを搭載し、導電性を有する第2接合材を介して第2半導体チップを搭載する工程、
(b)前記第1半導体チップ、前記第2半導体チップ、および前記チップ搭載部の少なくとも一部を封止する封止体を形成する工程、
を有し、
前記(a)工程では、前記第1半導体チップと前記第2半導体チップとは、前記チップ搭載部上に並んで配置され、
前記第2半導体チップは、裏面電極を有し、前記第2半導体チップの前記裏面電極が、前記第2接合材を介して前記チップ搭載部と電気的に接続され、
前記第1半導体チップの第1側面と第2側面とが交差して形成される第1の辺における、前記第1接合材で覆われた部分の第1の長さは、前記第2半導体チップの第3側面と第4側面とが交差して形成される第2の辺における、前記第2接合材で覆われた部分の第2の長さよりも大きい、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において
前記(a)工程は、
(a1)前記チップ搭載部上に前記第1接合材を供給する工程、
(a2)前記(a1)工程後、前記チップ搭載部上に、前記第1接合材を介して前記第1半導体チップを搭載する工程、
(a3)前記チップ搭載部上に前記第2接合材を供給する工程、
(a4)前記(a3)工程後、前記チップ搭載部上に、前記第2接合材を介して前記第2半導体チップを搭載する工程、
を含む、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において
前記(a3)工程は、前記(a2)工程の後に行われる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において
前記(a)工程は、
(a5)前記(a4)工程後、前記第1接合材および前記第2接合材を硬化させる工程、
を更に含む、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において
前記(a)工程は、
(a6)前記(a2)工程後、前記第1接合材を硬化させる工程、
(a7)前記(a4)工程後、前記第2接合材を硬化させる工程、
を更に含む、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において
前記(a1)工程では、
前記(a2)工程で前記チップ搭載部上に前記第1半導体チップを搭載した際に、平面視において前記第1半導体チップの四隅が重なる位置にも、前記第1接合材が供給される、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において
前記(a3)工程では、
前記(a4)工程で前記チップ搭載部上に前記第2半導体チップを搭載した際に、平面視において前記第2半導体チップの四隅が重なる位置には、前記第2接合材が供給されない、半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において
前記(a3)工程で前記チップ搭載部上における前記第2接合材が供給された領域は、
前記(a4)工程で前記チップ搭載部上に前記第2半導体チップを搭載した際に、平面視において前記第2半導体チップに重なる領域に内包されている、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において
前記第1接合材は、絶縁性ペースト型接合材である、半導体装置の製造方法。 - 請求項19記載の半導体装置の製造方法において
前記第2接合材は、導電性ペースト型接合材である、半導体装置の製造方法。
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