JPWO2016157394A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JPWO2016157394A1 JPWO2016157394A1 JP2017508911A JP2017508911A JPWO2016157394A1 JP WO2016157394 A1 JPWO2016157394 A1 JP WO2016157394A1 JP 2017508911 A JP2017508911 A JP 2017508911A JP 2017508911 A JP2017508911 A JP 2017508911A JP WO2016157394 A1 JPWO2016157394 A1 JP WO2016157394A1
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- semiconductor chip
- bonding material
- semiconductor
- semiconductor device
- die pad
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- Engineering & Computer Science (AREA)
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Abstract
Description
本発明の一実施の形態の半導体装置を図面を参照して説明する。
図1は、本発明の一実施の形態である半導体装置PKGの上面図であり、図2〜図4は、半導体装置PKGの平面透視図であり、図5は、半導体装置PKGの下面図(裏面図)であり、図6〜図8は、半導体装置PKGの断面図である。図2には、封止部MRを透視したときの半導体装置PKGの上面側の平面透視図が示されている。また、図3は、図2において、更にワイヤBWを透視(省略)したときの半導体装置PKGの上面側の平面透視図が示されている。また、図4は、図3において、更に半導体チップCP1,CP2を透視(省略)したときの半導体装置PKGの上面側の平面透視図が示されている。なお、図1〜図4では、半導体装置PKGの向きは同じである。また、図2〜図4では、封止部MRの外周の位置を点線で示してある。また、図1、図2および図5のA−A線の位置での半導体装置PKGの断面が、図6にほぼ対応し、図1、図2および図5のB−B線の位置での半導体装置PKGの断面が、図7にほぼ対応し、図1、図2および図5のC−C線の位置での半導体装置PKGの断面が、図8にほぼ対応している。また、図9は、図2の一部を拡大した部分拡大平面透視図である。
次に、上記図1〜図9に示される半導体装置PKGの製造工程について説明する。図10は、上記図1〜図9に示される半導体装置PKGの製造工程を示すプロセスフロー図である。図11〜図15は、半導体装置PKGの製造工程中の断面図である。なお、図11〜図15には、上記図6に相当する断面が示されている。
上記ステップS2のダイボンディング工程の詳細について、図面を参照して説明する。図16〜図19は、上記図10のプロセスフローのうち、ステップS2のダイボンディング工程の詳細を示すプロセスフロー図である。また、図20〜図30は、半導体装置PKGの製造工程中の平面図または断面図である。図20〜図30のうち、図20、図21、図23、図25、図27、図29および図30は、平面図であり、図22、図24、図26および図28は、上記図6に相当する断面が示されている。なお、図20のA1−A1線の断面図が、上記図11に対応し、図21のA1−A1線の断面図が、図22に対応し、図23のA1−A1線の断面図が、図24に対応し、図25のA1−A1線の断面図が、図26に対応し、図27のA1−A1線の断面図が、図28に対応している。
次に、図31を参照しながら、半導体装置PKGの回路構成について説明する。図31は、半導体装置PKGの回路図(回路ブロック図)である。
次に、半導体チップCP1の構造について説明する。
図33は、本発明者が検討した検討例の半導体装置(半導体パッケージ)PKG101の断面図であり、上記図6に相当する断面図が示されている。
そこで、本実施の形態の半導体装置PKGでは、半導体チップCP1と半導体チップCP2とを共通のダイパッドDP上に搭載している。
半導体チップCP2とダイパッドDPとの間には、絶縁性の接合材BD2が介在しており、電気的に絶縁されているが、半導体装置PKGの信頼性を高めるためには、半導体チップCP2とダイパッドDPとの間の耐圧を高めることが望ましい。例えば、半導体チップCP2とダイパッドDPとの間の耐圧が低いと、半導体チップCP2とダイパッドDPとの間で、静電気放電(ESD:Electro-Static Discharge)による破壊である静電破壊が生じる可能性がある。静電破壊が生じないようにするためには、半導体チップCP2とダイパッドDPとの間の耐圧をできるだけ高めることが望ましい。なお、耐圧とは、絶縁耐圧を意味する。
図34および図35は、半導体装置PKGの一部を拡大して示す平面透視図である。図34には、ダイパッドDP上に接合材BD2を介して搭載された半導体チップCP2が拡大して示され、また、図35には、ダイパッドDP上に接合材BD1を介して搭載された半導体チップCP1が拡大して示されている。但し、図34および図35では、上記図3と同様に、封止部MRおよびワイヤBWを透視している。このため、図34では、半導体チップCP2と接合材BD2が図示され、図35では、半導体チップCP1と接合材BD1が図示されている。
一方、半導体チップCP1については、導電性の接合材BD1を介してダイパッドDP上に搭載されているため、半導体チップCP1の裏面電極BEとダイパッドDPとは、導電性の接合材BD1を介して導通しており、半導体チップCP1とダイパッドDPとの間で静電破壊のような絶縁破壊が生じることはない。このため、半導体チップCP1とダイパッドDPとの間の耐圧を気にする必要はない。従って、半導体チップCP1の辺SD1における接合材BD1で覆われた部分の長さL1を大きくする必要はない。
そこで、本実施の形態では、主要な特徴のうちの一つとして、半導体チップCP1の辺SD1における接合材BD1で覆われた部分の長さL1よりも、半導体チップCP2の辺SD2における接合材BD2で覆われた部分の長さL2を大きくしている(すなわちL2>L1)。
V2×L3≧V1 ・・・式(1)
と、次の式(2)
V3×L4≧V1 ・・・式(2)
とが成り立つことが好ましい。なお、半導体チップCP2とダイパッドDPとの間の距離(間隔)L4は、ダイパッドDPと半導体チップCP2との間に介在する部分の接合材BD2の厚みにも対応している。
3 p型の半導体領域
4 n+型の半導体領域
5 p+型の半導体領域
6 溝
7 ゲート絶縁膜
8 ゲート電極
9,11 層間絶縁膜
10,12 プラグ
13 保護膜
14 開口部
BAT 電源
BD1,BD2 接合材
BE 裏面電極
BW ワイヤ
CLC 制御回路
CP1,CP2 半導体チップ
DP ダイパッド
GM 銀メッキ層
KM 界面
LD リード
LE 下端
LF リードフレーム
LOD 負荷
M1,M2 配線
M1S,M2S ソース配線
MR 封止部
MRa 上面
MRb 下面
MRc1,MRc2,MRc3,MRc4 側面
P1,P2 パッド電極
P1S ソース用パッド電極
PKG 半導体装置
Q1 パワーMOSFET
Q2 センスMOSFET
REG レギュレータ
SM1,SM2,SM3,SM4,SM5,SM6,SM7,SM8 側面
SD1,SD1a,SD1b,SD1c,SD1d 辺
SD2,SD2a,SD2b,SD2c,SD2d 辺
TL 吊りリード
Claims (20)
- 導電性を有するチップ搭載部と、
前記チップ搭載部上に、絶縁性を有する第1接合材を介して搭載された第1半導体チップと、
前記チップ搭載部上に、導電性を有する第2接合材を介して搭載された第2半導体チップと、
前記第1半導体チップ、前記第2半導体チップ、および前記チップ搭載部の少なくとも一部を封止する封止体と、
を備える半導体装置であって、
前記第2半導体チップは、裏面電極を有し、前記第2半導体チップの前記裏面電極が、前記第2接合材を介して前記チップ搭載部と電気的に接続され、
前記第1半導体チップの第1側面と第2側面とが交差して形成される第1の辺における、前記第1接合材で覆われた部分の第1の長さは、前記第2半導体チップの第3側面と第4側面とが交差して形成される第2の辺における、前記第2接合材で覆われた部分の第2の長さよりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
複数のリードと、
複数のワイヤと、
を更に有し、
前記封止体は、前記複数のリードのそれぞれの一部と、前記複数のワイヤとを封止し、
前記複数のワイヤは、前記第1半導体チップの複数の第1パッド電極と前記複数のリードのうちの複数の第1リードとを電気的に接続する複数の第1ワイヤと、前記第2半導体チップの複数の第2パッド電極と前記複数のリードのうちの複数の第2リードとを電気的に接続する複数の第2ワイヤと、を含む、半導体装置。 - 請求項1記載の半導体装置において、
前記第1の長さは、前記第1半導体チップの厚みの1/2以上である、半導体装置。 - 請求項3記載の半導体装置において、
前記第2の長さは、前記第2半導体チップの厚みの1/2未満である、半導体装置。 - 請求項4記載の半導体装置において、
前記第2の長さは、前記第2半導体チップの厚みの1/4以下である、半導体装置。 - 請求項1記載の半導体装置において
前記第1接合材の耐圧は、前記封止体の耐圧よりも大きい、半導体装置。 - 請求項1記載の半導体装置において
前記第1接合材は、絶縁性ペースト型接合材である、半導体装置。 - 請求項7記載の半導体装置において
前記第2接合材は、導電性ペースト型接合材である、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体チップは、パワートランジスタを含み、
前記第1半導体チップは、前記第2半導体チップを制御する、半導体装置。 - 請求項1記載の半導体装置において、
前記チップ搭載部の上面の一部に銀メッキ層が形成され、
前記第2半導体チップは、前記チップ搭載部の前記銀メッキ層上に、前記第2接合材を介して搭載され、
前記第1半導体チップは、前記銀メッキ層が形成されていない領域の前記チップ搭載部上に、前記第1接合材を介して搭載されている、半導体装置。 - (a)導電性を有するチップ搭載部上に、絶縁性を有する第1接合材を介して第1半導体チップを搭載し、導電性を有する第2接合材を介して第2半導体チップを搭載する工程、
(b)前記第1半導体チップ、前記第2半導体チップ、および前記チップ搭載部の少なくとも一部を封止する封止体を形成する工程、
を有し、
前記(a)工程では、前記第1半導体チップと前記第2半導体チップとは、前記チップ搭載部上に並んで配置され、
前記第2半導体チップは、裏面電極を有し、前記第2半導体チップの前記裏面電極が、前記第2接合材を介して前記チップ搭載部と電気的に接続され、
前記第1半導体チップの第1側面と第2側面とが交差して形成される第1の辺における、前記第1接合材で覆われた部分の第1の長さは、前記第2半導体チップの第3側面と第4側面とが交差して形成される第2の辺における、前記第2接合材で覆われた部分の第2の長さよりも大きい、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において
前記(a)工程は、
(a1)前記チップ搭載部上に前記第1接合材を供給する工程、
(a2)前記(a1)工程後、前記チップ搭載部上に、前記第1接合材を介して前記第1半導体チップを搭載する工程、
(a3)前記チップ搭載部上に前記第2接合材を供給する工程、
(a4)前記(a3)工程後、前記チップ搭載部上に、前記第2接合材を介して前記第2半導体チップを搭載する工程、
を含む、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において
前記(a3)工程は、前記(a2)工程の後に行われる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において
前記(a)工程は、
(a5)前記(a4)工程後、前記第1接合材および前記第2接合材を硬化させる工程、
を更に含む、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において
前記(a)工程は、
(a6)前記(a2)工程後、前記第1接合材を硬化させる工程、
(a7)前記(a4)工程後、前記第2接合材を硬化させる工程、
を更に含む、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において
前記(a1)工程では、
前記(a2)工程で前記チップ搭載部上に前記第1半導体チップを搭載した際に、平面視において前記第1半導体チップの四隅が重なる位置にも、前記第1接合材が供給される、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において
前記(a3)工程では、
前記(a4)工程で前記チップ搭載部上に前記第2半導体チップを搭載した際に、平面視において前記第2半導体チップの四隅が重なる位置には、前記第2接合材が供給されない、半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において
前記(a3)工程で前記チップ搭載部上における前記第2接合材が供給された領域は、
前記(a4)工程で前記チップ搭載部上に前記第2半導体チップを搭載した際に、平面視において前記第2半導体チップに重なる領域に内包されている、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において
前記第1接合材は、絶縁性ペースト型接合材である、半導体装置の製造方法。 - 請求項19記載の半導体装置の製造方法において
前記第2接合材は、導電性ペースト型接合材である、半導体装置の製造方法。
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CN107078067A (zh) | 2017-08-18 |
US10037932B2 (en) | 2018-07-31 |
US10347567B2 (en) | 2019-07-09 |
JP6364543B2 (ja) | 2018-07-25 |
US20180315685A1 (en) | 2018-11-01 |
TWI675418B (zh) | 2019-10-21 |
US20170221800A1 (en) | 2017-08-03 |
TW201703136A (zh) | 2017-01-16 |
WO2016157394A1 (ja) | 2016-10-06 |
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