CN100343987C - 具有金属板和半导体芯片的半导体器件 - Google Patents

具有金属板和半导体芯片的半导体器件 Download PDF

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Publication number
CN100343987C
CN100343987C CNB2004100877556A CN200410087755A CN100343987C CN 100343987 C CN100343987 C CN 100343987C CN B2004100877556 A CNB2004100877556 A CN B2004100877556A CN 200410087755 A CN200410087755 A CN 200410087755A CN 100343987 C CN100343987 C CN 100343987C
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chip
metallic plate
solder
heat sink
solder layer
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Expired - Fee Related
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CNB2004100877556A
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CN1612331A (zh
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中濑好美
坂本善次
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Denso Corp
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Denso Corp
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Abstract

一种半导体器件，包括：半导体芯片(10)；第一金属板(20)，通过第一焊料层(51)布置在芯片(10)的一侧上；第二金属板(40)，通过第二焊料层(52)布置在芯片(10)的另一侧上；第三金属板(30)，通过第三焊料层(53)布置在第二金属板(40)上；支撑装置(80、85、87)，用于保持芯片(10)与第一金属板(20)之间距离和芯片(10)与第二金属板(40)之间距离中的至少一个；以及多余焊料容纳装置(90)，用于在第三焊料层(53)包括多余焊料时容纳多余焊料，其中多余焊料容纳装置(90)为凹槽(90)，所述凹槽(90)被布置在和第二金属板(40)的外部周围对应的一部分第三金属板(30)上。

Description

具有金属板和半导体芯片的半导体器件
技术领域
本发明涉及一种具有第一金属板、半导体芯片、第二及第三金属板、且各层依次层叠的半导体器件。
背景技术
日本专利申请公开号No.2003-110064公开了一种具有半导体芯片和第一到第三金属层(即板)的半导体器件。第一金属层通过第一焊料层被结合到半导体芯片，使得第一金属层起着电极和热辐射板的作用。第二金属层通过第二焊料层被结合到半导体芯片，第二金属层被布置成与第一金属层相对。第三金属层通过第三焊料层被结合到第二金属层，并且第三金属层被布置成与半导体芯片相对。因此，在该器件中，第一到第三焊料层被分别布置在第一金属层和半导体芯片之间、芯片和第二金属层之间、以及第二和第三金属层之间。第一到第三焊料层采用这样的方式制作，使得焊料箔被夹在其间，然后焊料箔被加热到焊料的熔点。这样，焊料箔熔化，使得两个部件与焊料结合在一起。
然而，在每个焊料层中，焊料箔的供应量总是或多或少。这是由于半导体芯片和/或金属层的尺寸变化可能会导致焊料的多余或不足。特别地，焊料箔的量可能会缺乏或多余。当焊料量过量时，多余的焊料溢出，使得多余的焊料粘附到器件的其它部件，例如导线。因此，可能出现电路短路。这样，多余的焊料粘附到其它部件，从而形成一个焊料桥。因此器件可能会被损坏。另一方面，当焊料量不足时，焊料层的厚度不够。从而降低了结合的可靠性。此外还降低了热辐射性能。
发明内容
考虑上述问题，本发明的一个目的是提供具有第一金属板、半导体芯片、第二及第三金属板，且各层和焊料层依次层叠的半导体器件。特别地，各焊料层的厚度得到充分地保证，使得器件的各个部件被牢固地结合在一起。
本发明提供一种半导体器件，包括：
半导体芯片；第一金属板，通过第一焊料层布置在芯片(10)的一侧上；
第二金属板，通过第二焊料层布置在芯片的另一侧上；
第三金属板，通过第三焊料层布置在第二金属板上；
支撑装置，用于保持芯片与第一金属板之间距离和芯片与第二金属板之间距离中的至少一个；以及
多余焊料容纳装置，用于在第三焊料层包括多余焊料时容纳多余焊料，
其中多余焊料容纳装置为凹槽，所述凹槽被布置在和第二金属板的外部周围对应的一部分第三金属板上。
在上述器件中，充分保证各个焊料层的厚度，使得器件中的各个部件被牢固地结合在一起。特别地，各个焊料层的厚度可以通过支撑装置被适当地控制。此外，构成器件的各个部件的变型可以得到补偿，以便可以适当控制器件的尺寸。
优选地，支撑装置被布置在芯片和第一金属板之间以及芯片和第二金属板之间，使得芯片到第一金属板及芯片到第二金属板之间的距离被设定为一个预定的距离。更为优选地，该预定距离由支撑装置的尺寸定义。
附图说明
通过参考附图，从下述的详细描述中，本发明的上述及其它目标、特点及优点将变得更为明显。附图中：
图1示出了根据本发明的第一实施方案的半导体器件的截面示意图；
图2示出了根据本发明的第二实施方案的半导体器件的截面示意图；
图3示出了根据本发明的第三实施方案的半导体器件的截面示意图。
具体实施方式
(第一实施方案)
根据本发明第一实施方案的一种半导体器件S1如图1所示。器件S1包括半导体芯片10，作为第一金属层的下热沉(heat sink)20，作为第二金属层的热沉块40，以及作为第三金属层的上热沉30。第一到第三焊料层51-53被分别布置和结合在下热沉20与芯片10之间、芯片10与热沉块40之间、及热沉块40与上热沉30之间。
芯片10中产生的热量通过第二焊料层52、热沉块40、第三焊料层53及上热沉30，从芯片10的上方辐射出去。芯片10中产生的热量还通过第一焊料层51和下热沉20，从芯片10的下方辐射出去。芯片10为，例如，功率器件，诸如IGBT(即绝缘栅双极晶体管)或半导体闸流管。然而，芯片10可包括其它电子部件。
芯片10的形状，例如，可以是矩形的薄板。此外，下热沉20、上热沉30和热沉块40是由具有良好导电性和导热性的金属制成。例如，它们由铜合金或铝合金制成。这里，热沉块40可以由铁合金制成。下热沉20和上热沉30通过焊料层51-53及热沉块40被电连接到芯片10的电极，例如集电极和发射极。下热沉20呈矩形板状。特别地，下热沉20由金属板制成，使得下热沉20充当第一金属板，即第一金属层。下端子21由下热沉20朝芯片10的左侧突出，如图1所示。热沉块40略小于芯片10，呈矩形板状。特别地，热沉块40由金属板制成，使得热沉块40充当第二金属板，即第二金属层。上热沉30为矩形板状。特别地，上热沉30由金属板制成，使得上热沉30充当第三金属板，即第三金属层。上端子31由上热沉30朝芯片10的左侧突出，如图1所示。
上热沉20的上端子21和下热沉30的下端子31连接芯片10和外部电路。因此，上热沉20和下热沉30充当电极及热辐射板，使得热沉20、30辐射芯片10内产生的热量，且热沉20、30连接芯片10和外部电路。
作为信号引线的引线框60被布置在芯片10的周围。芯片10和引线框60通过导线70被电连接。导线70通过导线结合方法制成。导线70由金或铝制成。在器件S1中，支撑装置80被布置在芯片10和下热沉20之间，及芯片10和热沉块40之间。支撑装置80保持其间距离恒定。此外，多余焊料容纳装置90被布置在上热沉30上。多余焊料容纳装置90容纳从第三焊料层53溢出的多余焊料。
支撑装置80由预先嵌入在第一和第二焊料层51、52内的金属球80制成。尽管支撑装置80被布置在芯片10和下热沉20之间及芯片10和热沉块40之间，但支撑装置80可以被布置在芯片10与下热沉20之间和芯片10与热沉块40之间的至少一个间隔处。在这种情况下，作为支撑装置80的金属球至少被嵌入在焊料层51、52的其中一个内。金属球80优选由具有高热阻和具有适当可加工性的材料制成。例如，金属球80由诸如镍和铜的金属颗粒制成。金属球80可以由涂覆的陶瓷球制成，其表面通过电镀方法来涂敷。优选地，金属球80具有比焊料层51-53高的熔点。
多余焊料容纳装置90为一个在上热沉30表面上制成的凹槽。特别地，凹槽90被布置在对应于热沉块40的外部周围的一部分上热沉30上。凹槽90通过压力加工或切削加工方法制成。凹槽90的截面为方形。然而，凹槽90的截面也可以是诸如V形或者U形的其它形状。凹槽90被制成连续的环形槽，使得凹槽90对应于热沉块40的整个外部周围。然而，凹槽90可以为不连续的环形凹槽。
接下来，按如下过程制作半导体器件S1。首先，使用焊接方法，通过第一焊料层51，将芯片10结合到下热沉20。然后，热沉块40也使用焊接方法通过第二焊料层52被结合到芯片10。在这种情况下，芯片10通过包括金属球80作为支撑装置的焊料箔被层叠在下热沉20的表面上。此外，热沉块40通过包括金属球80的焊料箔被层叠在芯片10上。金属球80被均匀地布置在焊料箔上。为制备包括金属球80的焊料箔，金属球80被混合到焊料浆中，使得焊料浆被制成具有金属球80的焊料箔。或者金属球80被预先分散在焊料箔上，以制成包括金属球80的焊料箔。此外，金属球80被预先分散在多个焊料箔的其中之一上，然后，其它焊料箔被层叠在具有金属球80的焊料箔上，以制成包括金属球80的焊料箔。
在这之后，通过加热器(即回流设备)加热焊料箔到焊料的熔点，使焊料箔熔化。然后，熔化的焊料箔被冷却、硬化。当熔化的焊料箔硬化后，形成第一焊料层51和第二焊料层52。这里，第一或第二焊料层51、52的厚度由金属球80的尺寸定义。因此，芯片10和下热沉20被结合到第一焊料层51，芯片10和热沉块40被结合到第二焊料层52。
然后，芯片10的信号端子，例如栅衬垫和引线框60通过导线结合的方法而被结合，使得信号端子和引线框60被结合并且与导线70电连接。然后，上热沉30通过焊接方法被结合到热沉块40上。在这种情况下，上热沉30通过焊料箔被层叠在热沉块40上，接着，焊料箔被加热器加热并且熔化。随后，熔化的焊料箔被冷却和硬化。这里，焊料箔的量是被过量提供的，即大于所要求的焊料箔的量。这是因为，器件S1的各个部件的变化被热沉块40和上热沉30之间的间隔所补偿。因此，即使当部件的尺寸变得更小时，由于存在多余的焊料，也不会发生焊料不足的情况。当部件的尺寸变得更大时，出现焊料量多余。然而，为防止电路短路，作为凹槽90的多余焊料容纳装置90被形成在上热沉30上。因此，多余的焊料流到凹槽90中，使得多余的焊料不会流出。这样，防止了电路短路。也就是说，没有产生焊料桥。
熔化的焊料箔被硬化，使得上热沉30和热沉块40被结合到第三焊料层53。下热沉20、半导体芯片10、热沉块40即上热沉30被结合及电连接到焊料层51-53。此外，它们还以热学方式与焊料层51-53连接。这样，就完成了半导体器件S1。
这里，器件S1具有如下特性。器件S1包括金属球80，作为支撑装置用于保持芯片10和下热沉20之间和/或芯片10和热沉块40之间为一预定距离。这样，第一或第二焊料层51、52的厚度通过金属球80被确保为一个适当的厚度。此外，作为多余焊料容纳装置的凹槽90被形成于上热沉30上。凹槽90容纳来自第三焊料层53的多余焊料。因此，即使当焊料量过量时，熔化的且从第三焊料层53流出的多余焊料流入凹槽90，使得多余焊料不会流出。器件S1沿厚度方向的尺寸可以通过第三焊料层53的厚度来调整。第三焊料层53的量可被过量增加，以便提高第三焊料层53的厚度的自由度。因此，通过控制第三焊料层53的厚度，器件S1的整体尺寸可以被适当地控制。特别地，构成器件S1的部件尺寸的制作变化可以被热沉块40与上热沉30之间的间隔补偿。这里，部件的制作变化为，例如，芯片10的厚度变化，热沉20、30和热沉块40的厚度变化，或第一与第二焊料层51、52的厚度变化。
这样，第一和第二焊料层51、52的厚度可以被适当地控制，以便提高器件S1的可靠性。此外，多余焊料可以被容纳在凹槽90中，以便防止发生短路。再者，提高了器件S1的热辐射性能。
这里，凹槽90被形成在上热沉30上的原因在于，使得第三焊料层53与芯片10独立地布置。这样，第三焊料层53没有接触芯片10。因此，即使多余焊料从凹槽90流出，多余焊料难于粘附芯片10。与芯片10接触的第一和第二焊料层51、52对于防止提供多余焊料是必须的。因此，通过金属球80来保持焊料层51、52的厚度是防止焊料桥的有效途径。
因此，每个焊料层51-53的厚度可以被适当地控制。此外，组成器件S1的各个部件的变化可以被补偿，以便器件S1的尺寸可以被适当地控制。
尽管器件S1没有被密封，但器件S1可以用树脂模来密封。在这种情况下，器件S1是通过传递模型方法用环氧树脂来成型。此外，在这种情况下，下热沉20的下表面和上热沉30的上表面从树脂模暴露出来，从而提高热辐射性能。
(第二实施方案)
根据本发明第二实施方案的一种半导体器件S2如图2所示。器件S2包括支撑装置85，它是从下热沉20和热沉块40伸出的凸出85。凸出85朝芯片10突出。尽管下热沉20和热沉块40都包括凸出85，但下热沉20和热沉块40中至少一个可以包括凸出85。当凸出85被布置在芯片10和下热沉20之间时，凸出85被形成在下热沉20上。当凸出85被布置在芯片10和热沉块40之间时，凸出85被形成在热沉块40上。
在图2中，凸出85被形成在下热沉20的上表面上及热沉块40的下表面上。凸出85用挤压加工方法(press work method)或切削加工方法制成。器件S2可以采用类似制作器件S1的方法来制作。在这种情况下，没有金属球80的焊料箔被用作第一和第二焊料层51、52。在器件S2中，第一和第二焊料层51、52的厚度通过凸出85被适当地控制。此外，器件S2包括凹槽90。
这样，各个焊料层51-53的厚度可以被适当地控制。此外，组成器件S2的各个部件的变化可以被补偿，以便可以适当地控制器件S2的尺寸。
尽管支撑装置80为器件S2中的凸出85或者器件S1中的金属球80，但该支撑装置可以是其它部件，只要该支撑装置可保持芯片10和下热沉20之间和/或芯片10和热沉块40之间的距离。
尽管多余焊料容纳装置90为凹槽90，但多余焊料容纳装置90可以是其它部件，只要该多余焊料容纳装置90可容纳多余焊料。
(第三实施方案)
根据本发明第三实施方案的一种半导体器件S3如图3所示。器件S3包括支撑装置87，它在下热沉20或热沉块40的表面上有凹面。第一和第二焊料层51、52被布置在凹面内，使得第一和第二焊料层51、52的厚度被适当地控制。
因此，各个焊料层51-53的厚度可以被适当地控制。此外，组成器件S3的各个部件的变化可以被补偿，从而可以适当地控制器件S3的尺寸。
这些改变和修改应当被理解为属于由所附权利要求书限定的本发明的范围之内。

Claims (8)

1.一种半导体器件，包括：
半导体芯片(10)；
第一金属板(20)，通过第一焊料层(51)布置在芯片(10)的一侧上；
第二金属板(40)，通过第二焊料层(52)布置在芯片(10)的另一侧上；
第三金属板(30)，通过第三焊料层(53)布置在第二金属板(40)上；
支撑装置(80、85、87)，用于保持芯片(10)与第一金属板(20)之间距离和芯片(10)与第二金属板(40)之间距离中的至少一个；以及
多余焊料容纳装置(90)，用于在第三焊料层(53)包括多余焊料时容纳多余焊料，
其中多余焊料容纳装置(90)为凹槽(90)，所述凹槽(90)被布置在和第二金属板(40)的外部周围对应的一部分第三金属板(30)上。
2.根据权利要求1的器件，
其中支撑装置(80)为布置在第一和第二焊料层(51、52)中的金属球(80)。
3.根据权利要求1的器件，
其中支撑装置(80)为涂敷金属的陶瓷球(80)。
4.根据权利要求1～3中任一项所述的器件，
其中支撑装置(80、85、87)被布置在芯片(10)和第一金属板(20)之间及芯片(10)和第二金属板(40)之间，使得芯片(10)和第一金属板(20)之间距离及芯片(10)和第二金属板(40)之间距离被设置为预定距离。
5.根据权利要求4的器件，
其中预定距离由支撑装置(80、85、87)的尺寸定义。
6.根据权利要求1的器件，
其中支撑装置(85、87)为从第一和第二金属板(20、40)朝芯片(10)突出的凸出(85、87)。
7.根据权利要求6的器件，
其中凸出(85、87)被布置在芯片(10)和第一金属板(20)之间及芯片(10)和第二金属板(40)之间，使得芯片(10)和第一金属板(20)之间距离及芯片(10)和第二金属板(40)之间距离被设置为预定距离，以及
其中预定距离由凸出(85、87)的尺寸定义。
8.根据权利要求1～3中任一项所述的器件，
其中第一金属板(20)为电极和热辐射板，使得第一金属板(20)连接在芯片(10)和外部电路之间，且第一金属板(20)辐射芯片(10)内产生的热，以及
其中第三金属板(30)为电极和热辐射板，使得第三金属板(30)连接在芯片(10)和外部电路之间，且第三金属板(30)辐射芯片(10)内产生的热。
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