TWI593067B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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Publication number
TWI593067B
TWI593067B TW103106596A TW103106596A TWI593067B TW I593067 B TWI593067 B TW I593067B TW 103106596 A TW103106596 A TW 103106596A TW 103106596 A TW103106596 A TW 103106596A TW I593067 B TWI593067 B TW I593067B
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Taiwan
Prior art keywords
package structure
bent portion
semiconductor package
heat sink
die
Prior art date
Application number
TW103106596A
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English (en)
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TW201533864A (zh
Inventor
楊惟理
周宗傑
王自強
張倉生
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林朋科技股份有限公司
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Application filed by 林朋科技股份有限公司 filed Critical 林朋科技股份有限公司
Priority to TW103106596A priority Critical patent/TWI593067B/zh
Priority to US14/301,978 priority patent/US9299679B2/en
Publication of TW201533864A publication Critical patent/TW201533864A/zh
Application granted granted Critical
Publication of TWI593067B publication Critical patent/TWI593067B/zh

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L2924/11—Device type
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    • H01L2924/1715—Shape
    • H—ELECTRICITY
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    • H01L2924/181—Encapsulation

Description

半導體封裝結構
本發明係關於一種半導體封裝結構，特別是關於一種半導體封裝結構。
隨著時代演進，車用電子系統正快速的導入各種類別的車輛內，例如汽車用感應雷達、車內音響及各種汽車安全系統等複雜且精密的電子電路系統，均已廣泛的被不斷導入與應用。然而，無可避免的電子電路系統所衍生的EMC問題及穩壓問題卻也越趨嚴重。車用電子電路系統所面臨的EMC或穩壓方面的威脅，可參考IEC7637或JASO等國際性法規。JEDEC協會所公布的DO-218(AB)，目前被選為車用EMC問題的解決方案建議使用元件之一。
習知的DO-218(AB)可參考如第1圖所示，其由一個散熱片401、一個導線架402、一個晶粒403及一個黑膠體404所組成。依照目前的應用與測試資料，習知的DO-218(AB)僅能使用於低功率的EMC防護以及低功率的穩壓，而無法克服諸如IEC7637、JASO-D001-94等較嚴格的法規所定義與規範之高功率EMC衝擊的要求。
請參考如第2圖所示，DO-218(AB)無法克服高功率EMC衝擊之主要原因為晶粒403所產生的熱能，於瞬態下(EMC產生的瞬間)， 係生成於晶粒403的半導體接合處之PN介面(PN JUNCTION)405，而因為晶粒403的PN介面405處與絕緣保護層406須朝上(晶粒403的絕緣保護層406面無法朝下是因為在朝下的情況下，絕緣保護層406會與大片面積的散熱片401接觸，導致生產良率低下與嚴重元件可靠度問題)，使得銲接處的導線架402無法在瞬間快速吸收並消散熱能，導致在高功率的EMC衝擊，或者於高溫的應用環境下，產品有嚴重的功能失效問題。
但隨著複雜的車用電子系統的快速導入與廣泛應用，IEC7637(IEC7637-2-5A、5B)要求防護元件必須能承受高安培數之電流以及長時間的能量衝擊，並已成為基本的EMC要求門檻，傳統的DO-218(AB)結構之規格已無法滿足應用於現今的車用或工業用規格之EMC或穩壓元件的要求。
本發明為一種半導體封裝結構，其包括：下散熱片；晶粒；上散熱片；導線架；以及封裝體。其係以上散熱片及下散熱片分別密接晶粒相對應之二表面對瞬間高功率之熱能進行有效吸收及散熱，下散熱片並設有圍繞晶粒之凹槽使銲錫不會因為溢錫導致產品短路或者造成信賴性問題。封裝體則包覆及保護晶粒、上散熱片、部份導線架、以及部份下散熱片。藉由本發明之實施可在瞬間快速吸收並消散熱能，提高半導體封裝結構之元件可靠度，並增加其可耐受之EMC能量或可承載之操作功率。
本發明係提供一種半導體封裝結構，其包括有：一下散熱片，其為導熱材質所形成，並具有一上表面及一底面，上表面又形成有環狀之一凹槽包圍上表面之一接著區；一晶粒，其係以一第一表面固定結合於接 著區，並具有與第一表面相對之一第二表面及一絕緣保護層；一上散熱片，其為導電導熱材質所形成，並具有一接合部及一第一彎折部，接合部係與第二表面相密接；一導線架，其為導電材質所形成，並具有一第二彎折部及一彎腳，第二彎折部係與第一彎折部相密接，又彎腳之一部份係與底面位於同一平面；以及一封裝體，其係包覆晶粒、上散熱片、導線架之一部份及下散熱片之一部份，並使彎腳及底面外露於封裝體之外。
藉由本發明之實施，至少可以達成下列功效：
一、使半導體封裝結構可使用於嚴苛之使用環境，如汽車引擎室內或高溫、高壓或高電磁波干擾之應用場合。
二、使半導體封裝結構可在瞬間快速吸收並消散熱能。
三、使半導體封裝結構可用以封裝高功率EMC保護元件。
四、使半導體封裝結構可用以封裝高功率穩壓IC。
五、可用以製造標準封裝結構規格之DO-218(AB)或TO-220等封裝結構，具有廣大的產業利用性。
六、將半導體封裝結構封裝之元件銜接於需保護的附載電路時，可以抵擋輸入源所輸出的高安培數之電流衝擊，保護附載電路，免除EMC的威脅(高安培數之電流係指2安培以上或瞬間50A/300ms以上之電流)。
為了使任何熟習相關技藝者了解本發明之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本發明相關之目的及優點，因此將在實施方式中詳細敘述本發明之詳細特徵以及優點。
100‧‧‧半導體封裝結構
10‧‧‧下散熱片
11‧‧‧上表面
12‧‧‧底面
13‧‧‧凹槽
14‧‧‧接著區
20‧‧‧晶粒
21‧‧‧第一表面
22‧‧‧第二表面
23‧‧‧絕緣保護層
30‧‧‧上散熱片
31‧‧‧接合部
32‧‧‧第一彎折部
40‧‧‧導線架
41‧‧‧第二彎折部
42‧‧‧彎腳
421‧‧‧第一彎部
422‧‧‧第二彎部
423‧‧‧第三彎部
50‧‧‧封裝體
60‧‧‧銲錫
70‧‧‧電路板
80‧‧‧防護層
401‧‧‧散熱片
402‧‧‧導線架
403‧‧‧晶粒
404‧‧‧黑膠體
405‧‧‧PN介面
406‧‧‧絕緣保護層
[第1圖]係為習知的DO-218(AB)之側面剖視圖。
[第2圖]係為另一種習知的DO-218(AB)之側面剖視圖。
[第3圖]係為本發明實施例之一種半導體封裝結構之側面剖視圖。
[第4圖]係為本發明實施例之另一種半導體封裝結構之側面剖視圖。
[第5圖]係為本發明實施例之一種下散熱片與晶粒結合之側面剖視圖。
[第6圖]係為本發明實施例之一種半導體封裝結構應用於一電路板上之側面剖視圖。
[第7圖]係為本發明實施例之一種晶粒進一步塗佈防護層之側面剖視圖。
如第3圖所示，係為實施例的一種半導體封裝結構100，其包括：一下散熱片10、一晶粒20、一上散熱片30、一導線架40及一封裝體50。
如第3圖及第4圖所示之半導體封裝結構100可以製作成為一個DO-218(AB)規格之封裝結構，或一個TO-220規格之封裝結構，並可用以做為高功率EMC保護元件、高功率穩壓IC、瞬態電壓抑制晶片或ZENER晶片之封裝結構。
如第3圖及第4圖所示，下散熱片10，其為導熱材質所形成，並具有一上表面11及一底面12，上表面11又形成有環狀之一凹槽13包圍該上表面11之一接著區14。下散熱片10係具有一體積，可以吸收晶粒20所產生的熱量之一部份，並將熱量自底部散出。又凹槽13之形 狀可以為U形或V形或圓弧形，於製作時並無特殊之限制。
再如第3圖及第4圖所示，晶粒20，其可以為一瞬態電壓抑制晶片，亦可以為電磁干擾抑制晶片。晶粒20係以一第一表面21固定結合於下散熱片10之接著區14。且接著區14之面積係可以不小於第一表面21之面積，使下散熱片10對晶粒20具有優良的散熱效果。
此外，晶粒20並具有與第一表面21相對之第二表面22。必要時晶粒20亦可以具有絕緣保護層23，用以保護延伸至晶粒20周圍之PN介面，使不產生短路或受外部干擾，以維持晶粒20之正常功能運作。
如第3圖至第5圖所示，於實際應用時，可利用銲錫60將晶粒20自第一表面21銲接於下散熱片10之接著區14。由於接著區14受凹槽13環繞，銲接時多餘的銲錫60便流入凹槽13之內，使晶粒20不會因為溢錫導致產品短路或者造成信賴性問題而影響正常的運作，並進而使晶粒20可達到理想的可承載功率與提升半導體封裝結構100之元件可靠度。
又如第3圖及第4圖所示，上散熱片30，為導電導熱材質所形成，並具有一接合部31及一第一彎折部32。上散熱片30之接合部31係與晶粒20之第二表面22相密接，其密接方式可以是以銲錫60銲接而相密接。另外，接合部31之面積係可以不小於晶粒20之面積，使具有優良之散熱效果。
請再參閱如第3圖及第4圖所示，導線架40，其係為導電材質所形成，並具有一第二彎折部41及一彎腳42。導線架40之第二彎折部41係與上散熱片30之第一彎折部32相密接，又彎腳42之一部份係與下散熱片10之底面12位於同一平面上。
導線架40之第二彎折部41與上散熱片30之第一彎折部32， 係皆可以形成相對應之V型彎折或U型彎折，且在晶粒20與接著區14及接合部31銲接的組裝過程中，可以同步以銲錫60銲接第二彎折部41與第一彎折部32，使導線架40之彎腳42與晶粒20電性相導通而成為晶粒20之訊號或電性連接腳(CONNECTING PIN)。
再者，第二彎折部41與第一彎折部32可減少溫度變化下的物理應力，使導線架40或上散熱片30不致因為物理應力影響晶粒20之正常運作。又彎腳42係可以如第3圖所示，向晶粒20方向彎曲，或如第4圖所示，向遠離晶粒20之方向彎曲。
如第6圖所示，導線架40之彎腳42係可以彎折形成一第一彎部421、一第二彎部422及一第三彎部423，且第三彎部423並與下散熱片10之底面12可以位於相同平面上，並藉此完成半導體封裝結構100之接腳製程。如此，在實際應用將半導體封裝結構100銲接於電路板時，可達到銲接容易與銲接確實之功效而確保半導體封裝結構100之正常運作。
如第3圖、第4圖及第6圖所示之上散熱片30或下散熱片10，皆係可以為純銅或是銅合金等具導電與高散熱特性之材質所形成，以達到導電性良好、易於以銲錫焊接以及散熱性良好等功效。
再如第3圖及第6圖所示，封裝體50，其係包覆晶粒20、上散熱片30、導線架40之一部份及下散熱片10之一部份，並使導線架40之彎腳42及下散熱片10之底面12外露於封裝體50之外，如此，彎腳42與底面12可進行與外部之電性連接，並可達到對晶粒20進行散熱。而所述之封裝體50，可以為黑膠體(BLACK GLUE)或環氧樹脂(EPOXY)，或是模造封膠體(MOLDING COMPOUND)。
如前各實施例所述之半導體封裝結構100，具有容易製造且 成本低廉之優勢、可以避免溢錫問題、提升產品在高低溫冷熱衝擊下的耐受性及使用壽命，並因大量提升元件的熱消散功率而顯著提升產品的可承載功率與信賴度，更由於高散熱之特性，使半導體封裝結構100可以承受高安培數之電流(此所謂高安培數之電流係指穩定電流或持續電流2安培以上，或者是瞬間50A/300ms以上之電流，其中A=安培，ms=毫秒=千分之一秒)。
另一方面，如第7圖所示，由於元件應用於車用領域或工業領域時，環境上的濕度較無法管控，濕度的變化也較為劇烈。為防止水氣沿著黑膠體與導電材質的縫隙入侵，可於晶粒20周圍塗佈上防護層80以阻隔水氣的入侵，防止晶粒20因水氣而產生銹蝕而達到較佳的防護與產品壽命。其中，所使用之防護層80可以為高分子聚合物(POLYMER)、多晶矽(POLYSILICON)或透明漆(VARNISH WATER)等材質所形成。
惟上述各實施例係用以說明本創作之特點，其目的在使熟習該技術者能瞭解本創作之內容並據以實施，而非限定本創作之專利範圍，故凡其他未脫離本創作所揭示之精神而完成之等效修飾或修改，仍應包含在以下所述之申請專利範圍中。
100‧‧‧半導體封裝結構
10‧‧‧下散熱片
11‧‧‧上表面
12‧‧‧底面
13‧‧‧凹槽
14‧‧‧接著區
20‧‧‧晶粒
21‧‧‧第一表面
22‧‧‧第二表面
23‧‧‧絕緣保護層
30‧‧‧上散熱片
31‧‧‧接合部
32‧‧‧第一彎折部
40‧‧‧導線架
41‧‧‧第二彎折部
42‧‧‧彎腳
50‧‧‧封裝體
60‧‧‧焊錫

Claims (10)

  1. 一種半導體封裝結構，其包括有：一下散熱片，其為導熱材質所形成，並具有一上表面及一底面，該上表面又形成有環狀之一凹槽包圍該上表面之一接著區；一晶粒，其係以一第一表面固定結合於該接著區，並具有與該第一表面相對之一第二表面；一上散熱片，其為導電導熱材質所形成，並具有一接合部及一第一彎折部，該接合部係與該第二表面相密接；一導線架，其為導電材質所形成，並具有一第二彎折部及一彎腳，該第二彎折部係與該第一彎折部相密接，又該彎腳之一部份係與該底面位於同一平面；以及一封裝體，其係包覆該晶粒、該上散熱片、該導線架之一部份及該下散熱片之一部份，並使該彎腳及該底面外露於該封裝體之外；其中該下散熱片係直接與該晶粒接觸，並且該下散熱片之一部份凸出暴露於該封裝體之外；及其中該第二彎折部與該第一彎折部係皆形成相對應之V型彎折或U型彎折。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其係為符合DO-218(AB)規格或TO-220規格之封裝結構。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中該晶粒為一瞬態電壓抑制晶片或一ZENER晶片之封裝結構。
  4. 如申請專利範圍第1項所述之半導體封裝結構，其中該接著區與該第一表面係以銲錫相密接，且該接合部與該第二表面係以銲錫相密 接。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中該接合部之面積係不小於該晶粒面積。
  6. 如申請專利範圍第1項或第5項所述之半導體封裝結構，其中該第二彎折部與該第一彎折部係以銲錫相密接。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中該彎腳係具有一第一彎部、一第二彎部及一第三彎部，該第三彎部並與該底面位於相同平面上。
  8. 如申請專利範圍第1項所述之半導體封裝結構，其中該封裝體係為一黑膠體或為一環氧樹脂。
  9. 如申請專利範圍第1項所述之半導體封裝結構，其中該上散熱片或該下散熱片係為純銅或銅合金材質所形成。
  10. 如申請專利範圍第1項所述之半導體封裝結構，其中該晶粒周圍係塗佈一防護層。
TW103106596A 2014-02-26 2014-02-26 半導體封裝結構 TWI593067B (zh)

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