CN105555848A - 半导体芯片密封用热固化性树脂片及半导体封装体的制造方法 - Google Patents

半导体芯片密封用热固化性树脂片及半导体封装体的制造方法 Download PDF

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CN105555848A
CN105555848A CN201480051887.5A CN201480051887A CN105555848A CN 105555848 A CN105555848 A CN 105555848A CN 201480051887 A CN201480051887 A CN 201480051887A CN 105555848 A CN105555848 A CN 105555848A
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resin sheet
semi
conductor chip
sealing member
encapsulation resin
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CN105555848B (zh
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盛田浩介
石坂刚
丰田英志
志贺豪士
饭野智绘
石井淳
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Nitto Denko Corp
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Nitto Denko Corp
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Abstract

本发明提供可降低热固化性树脂片的体积收缩所致的翘曲变形、并且可靠性和保存性优异的半导体芯片密封用热固化性树脂片及半导体封装体的制造方法。本发明涉及一种半导体芯片密封用热固化性树脂片,其活化能(Ea)满足下述式(1),且在150℃热固化处理1小时后的热固化物的玻璃化转变温度为125℃以上,上述热固化物在上述玻璃化转变温度以下的温度下的热膨胀系数α[ppm/K]及上述热固化物在25℃时的储藏弹性模量E’[GPa]满足下述式(2)。30≤Ea≤120[kJ/mol]…(1)10000≤α×E’≤300000[Pa/K]…(2)。

Description

半导体芯片密封用热固化性树脂片及半导体封装体的制造方法
技术领域
本发明涉及半导体芯片密封用热固化性树脂片及半导体封装体的制造方法。
背景技术
以往,作为半导体封装体的制造方法,已知将固定于基板等的1个或多个半导体芯片用密封树脂密封的方法。作为此种密封树脂,已知例如热固化性树脂片(例如参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2006-19714号公报
发明内容
发明要解决的问题
有时因热固化过程中的密封树脂的体积收缩而半导体封装体产生翘曲变形。若因热固化过程中的密封树脂的体积收缩而产生翘曲变形,则无法将半导体封装体充分固定(例如吸附固定)于平台上,会难以研削半导体封装体的密封树脂。
另外,通常,密封树脂的热膨胀系数比构成半导体封装体的其他元件(例如半导体芯片、基板等)大,因此半导体封装体产生翘曲,在可靠性的方面还有改善的余地。
本发明的目的在于,为解决上述问题而提供可降低热固化性树脂片的体积收缩所致的翘曲变形、并且可靠性和保存性优异的半导体芯片密封用热固化性树脂片及半导体封装体的制造方法。
用于解决问题的技术手段
本发明涉及一种半导体芯片密封用热固化性树脂片,其活化能(Ea)满足下述式(1),且在150℃热固化处理1小时后的热固化物的玻璃化转变温度为125℃以上,上述热固化物在上述玻璃化转变温度以下的温度下的热膨胀系数α[ppm/K]及上述热固化物在25℃时的储藏弹性模量E’[GPa]满足下述式(2)。
30≤Ea≤120[kJ/mol]···(1)
10000≤α×E’≤300000[Pa/K]···(2)
Ea为120kJ/mol以下,能够在较低温进行热固化,因此能够减小翘曲。另外,由于无需为了使其热固化而进行长时间加热,因此生产率优异。
另一方面,由于Ea为30kJ/mol以上,因此可以在利用加热使热固化性树脂片追随凹凸(利用半导体芯片等形成的凹凸)后进行热固化。结果可以降低空隙的产生。另外,保存性良好。
此外,热固化物在玻璃化转变温度以下的温度下的热膨胀系数α及热固化物在25℃时的储藏弹性模量E’满足上述式(2)。因此,可以缓和因热膨胀系数的不同所产生的热应力,并且可以得到可靠性优异的半导体封装体。例如,在α×E’的数值范围内,储藏弹性模量E’较高时,热固化性树脂片的刚性提高,可以吸收或分散应力。此时,热膨胀系数α变低,热固化性树脂片的热膨胀行为得到抑制,因此可以降低对构成半导体封装体的其他元件(例如半导体芯片、基板等)的机械损伤。
需要说明的是,热固化物的玻璃化转变温度为125℃以上,因此可以抑制半导体封装体在通常的使用温度范围及热循环可靠性试验的温度范围(最大125℃)的急剧的物性变化。
本发明的半导体芯片密封用热固化性树脂片优选包含环氧树脂、苯酚线型酚醛系固化剂、无机填充材料及固化促进剂。
上述无机填充材料优选为平均粒径0.5μm~50μm的二氧化硅。
上述固化促进剂优选为咪唑系固化促进剂。通过使用咪唑系固化促进剂,从而能够将活化能容易地调整为30~120kJ/mol,并且可以抑制混炼温度下的固化反应。
上述无机填充材料的含量优选为20体积%~90体积%。
上述热固化物在25℃时的储藏弹性模量E’优选为3GPa~30GPa。
上述热膨胀系数α优选为3ppm/K~50ppm/K。
本发明还涉及一种半导体封装体的制造方法,其包括:工序(A),形成具备上述半导体芯片密封用热固化性树脂片及埋入上述半导体芯片密封用热固化性树脂片的1个或多个半导体芯片的密封体;和工序(B),对上述密封体的树脂片进行热固化。
上述工序(A)中,优选将倒装芯片式连接于半导体晶片的上述半导体芯片埋入上述半导体芯片密封用热固化性树脂片而形成上述密封体。
上述工序(A)中,优选将固定于暂时固定材料的上述半导体芯片埋入上述半导体芯片密封用热固化性树脂片而形成上述密封体。
上述工序(A)中,优选将倒装芯片式连接于上述半导体晶片的多个上述半导体芯片埋入上述半导体芯片密封用热固化性树脂片而形成上述密封体。而且,本发明的半导体封装体的制造方法优选在上述工序(B)之后还包括将上述密封体按照目标半导体芯片单元进行切割的工序(C)。
附图说明
图1是实施方式1的树脂片的剖面示意图。
图2是倒装芯片式安装了半导体芯片的半导体晶片的剖面示意图。
图3是示意性表示用实施方式1的树脂片密封半导体芯片的状态的图。
图4是示意性表示对半导体封装体的树脂片部分进行研削后的状态的图。
图5是示意性表示对半导体封装体的半导体晶片部分进行研削后的状态的图。
图6是示意性表示在半导体封装体中形成了再布线层和凸块的状态的图。
图7是示意性表示对半导体封装体进行切割后的状态的图。
图8是示意性表示将半导体芯片固定于暂时固定材料的状态的图。
图9是示意性表示用树脂片密封半导体芯片的状态的图。
图10是示意性表示从密封体剥离暂时固定材料的状态的图。
图11是示意性表示对半导体封装体的树脂片部分进行研削后的状态的图。
图12是示意性表示在密封体中形成了再布线和凸块的状态的图。
图13是示意性表示对密封体进行切割后的状态的图。
具体实施方式
以下列举实施方式对本发明进行详细地说明,但是本发明并不仅限定为这些实施方式。
[实施方式1]
图1是实施方式1的树脂片11的剖面示意图。需要说明的是,可以在树脂片11的两面设置聚对苯二甲酸乙二醇酯(PET)膜等支承体。为了容易进行从树脂片11的剥离,可以对支承体实施脱模处理。
树脂片11具有热固化性。
树脂片11的活化能(Ea)为30kJ/mol以上。由于该活化能为30kJ/mol以上,因此可以在利用加热使热固化性树脂片追随凹凸(利用半导体芯片等形成的凹凸)后进行热固化。结果可以降低空隙的产生。另外,保存性良好。树脂片11的活化能优选为40kJ/mol以上、更优选为50kJ/mol以上、进一步优选为60kJ/mol以上。
另外,树脂片11的活化能为120kJ/mol以下。由于该活化能为120kJ/mol以下,能够在较低温下进行热固化,因此能够减小翘曲。另外,由于无需为了使其热固化而进行长时间加热,因此生产率优异。树脂片11的活化能优选为100kJ/mol以下。
需要说明的是,活化能可以利用实施例中记载的方法来测定。
树脂片11的活化能可以通过固化促进剂的种类、固化促进剂的量等来控制。
树脂片11满足下述式(2)。
10000≤α×E’≤300000[Pa/K]···(2)
上述式(2)中,α为在150℃热固化处理1小时后的热固化物在玻璃化转变温度以下的温度下的热膨胀系数[ppm/K]。
上述式(2)中,E’为在150℃热固化处理1小时后的热固化物在25℃时的储藏弹性模量[GPa]。
对于树脂片11而言,由于满足上述式(2),因此能够缓和因热膨胀系数的不同产生的热应力。例如,在α×E’的数值范围中,在储藏弹性模量E’高的情况下,树脂片11的刚性提高,从而能够吸收或分散应力。此时,热膨胀系数α变低,树脂片11的热膨胀行为得到抑制,因此可以降低对构成半导体封装体的其他元件(例如半导体芯片、基板等)的机械损伤。
α×E’优选为10万Pa/K以上。α×E’优选为20万Pa/K以下。
储藏弹性模量E’优选为3GPa以上、更优选为10GPa以上、进一步优选为15GPa以上。若储藏弹性模量E’为3GPa以上,则热应力的缓和效果高。另一方面,储藏弹性模量E’的上限并无特别限定,例如为30GPa以下,优选为25GPa以下。
需要说明的是,储藏弹性模量E’可以利用实施例中记载的方法来测定。
树脂片11的储藏弹性模量E’可以通过无机填充材料的含量、热塑性树脂的含量来控制。例如,通过增加无机填充材料的含量,增加热塑性树脂的含量,从而可以提高储藏弹性模量E’。
热膨胀系数α优选为50ppm/K以下、更优选为20ppm/K以下、进一步优选为15ppm/K以下。若热膨胀系数α为50ppm/K以下,则热应力的缓和效果高。另一方面,热膨胀系数α的下限并无特别限定,例如为3ppm/K以上。
需要说明的是,热膨胀系数α可以利用实施例中记载的方法来测定。
树脂片11的热膨胀系数α可以通过无机填充材料的含量等来控制。例如,通过增加无机填充材料的含量,从而可以减小热膨胀系数α。
将树脂片11在150℃热固化处理1小时后的热固化物的玻璃化转变温度(Tg)为125℃以上。若该玻璃化转变温度为125℃以上,则可以抑制半导体封装体在通常的使用温度范围及热循环可靠性试验的温度范围(最大125℃)内的急剧的物性变化。热固化物的玻璃化转变温度的上限并无特别限定,例如为180℃以下,优选为160℃以下。
需要说明的是,玻璃化转变温度可以利用实施例中记载的方法来测定。
树脂片11的热固化物的玻璃化转变温度可以通过基于热固化性树脂(例如环氧树脂、酚醛树脂)的官能基的交联密度来控制。例如,通过应用分子中官能基数多的热固化性树脂,从而可以提高玻璃化转变温度。
树脂片11优选包含环氧树脂。
作为环氧树脂,并无特别限定。例如可以使用三苯基甲烷型环氧树脂、甲酚线型酚醛型环氧树脂、联苯型环氧树脂、改性双酚A型环氧树脂、双酚A型环氧树脂、双酚F型环氧树脂、改性双酚F型环氧树脂、二环戊二烯型环氧树脂、苯酚线型酚醛型环氧树脂、苯氧基树脂等各种环氧树脂。这些环氧树脂可以单独使用,也可以并用2种以上。
从确保环氧树脂的反应性的观点出发,优选环氧当量为150~250、软化点或熔点为50~130℃、在常温为固态的环氧树脂。其中,从可靠性的观点出发,更优选三苯基甲烷型环氧树脂、甲酚酚醛型环氧树脂、联苯型环氧树脂。另外,优选双酚F型环氧树脂。
树脂片11优选包含苯酚线型酚醛系固化剂。作为苯酚线型酚醛系固化剂,可以适合使用苯酚线型酚醛树脂。其中,可以特别适合使用具有联苯芳烷基骨架的苯酚线型酚醛树脂。需要说明的是,苯酚线型酚醛系固化剂可以单独使用,也可以并用2种以上。
作为苯酚线型酚醛系固化剂,从与环氧树脂的反应性的观点出发,优选使用羟基当量为70~250、软化点为50~110℃的固化剂。
树脂片11中的环氧树脂及苯酚线型酚醛系固化剂的合计含量优选为5重量%以上。若合计含量为5重量%以上,则良好地得到针对半导体芯片等的粘接力。树脂片11中的环氧树脂及苯酚线型酚醛系固化剂的合计含量优选为40重量%以下、更优选为20重量%以下。若该合计含量为40重量%以下,则可以较低地抑制吸湿性。
从固化反应性的观点出发,环氧树脂与苯酚线型酚醛系固化剂的配合比例优选按照相对于环氧树脂中的环氧基1当量而使苯酚线型酚醛系固化剂中的羟基的合计达到0.7~1.5当量的方式进行配合、更优选为0.9~1.2当量。
树脂片11优选包含固化促进剂。
作为固化促进剂,只要是使环氧树脂与苯酚线型酚醛系固化剂的固化进行的物质,则并无特别限定,例如可列举:2-甲基咪唑(商品名;2MZ)、2-十一烷基咪唑(商品名;C11-Z)、2-十七烷基咪唑(商品名;C17Z)、1,2-二甲基咪唑(商品名;1.2DMZ)、2-乙基-4-甲基咪唑(商品名;2E4MZ)、2-苯基咪唑(商品名;2PZ)、2-苯基-4-甲基咪唑(商品名;2P4MZ)、1-苄基-2-甲基咪唑(商品名;1B2MZ)、1-苄基-2-苯基咪唑(商品名;1B2PZ)、1-氰基乙基-2-甲基咪唑(商品名;2MZ-CN)、1-氰基乙基-2-十一烷基咪唑(商品名;C11Z-CN)、1-氰基乙基-2-苯基咪唑鎓偏苯三酸盐(商品名;2PZCNS-PW)、2,4-二氨基-6-[2’-甲基咪唑基-(1’)]-乙基均三嗪(商品名;2MZ-A)、2,4-二氨基-6-[2’-十一烷基咪唑基-(1’)]-乙基均三嗪(商品名;C11Z-A)、2,4-二氨基-6-[2’-乙基-4’-甲基咪唑基-(1’)]-乙基均三嗪(商品名;2E4MZ-A)、2,4-二氨基-6-[2’-甲基咪唑基-(1’)]-乙基均三嗪异氰脲酸加成物(商品名;2MA-OK)、2-苯基-4,5-二羟基甲基咪唑(商品名;2PHZ-PW)、2-苯基-4-甲基-5-羟基甲基咪唑(商品名;2P4MHZ-PW)等咪唑系固化促进剂(均为四国化成工业(株)制)。
其中,基于能够将活化能容易地调整为30~80kJ/mol、且抑制混炼温度下的固化反应的理由,优选咪唑系固化促进剂,更优选2-苯基-4,5-二羟基甲基咪唑、2,4-二氨基-6-[2’-乙基-4’-甲基咪唑基-(1’)]-乙基均三嗪,进一步优选2-苯基-4,5-二羟基甲基咪唑。
固化促进剂的含量相对于环氧树脂及苯酚线型酚醛系固化剂的合计100重量份优选为0.2重量份以上、更优选为0.5重量份以上、进一步优选为0.8重量份以上。若该含量为0.2重量份以上,则能够将活化能容易地调整为80kJ/mol以下。固化促进剂的含量相对于环氧树脂及苯酚线型酚醛系固化剂的合计100重量份优选为5重量份以下、更优选为2重量份以下。若该含量为5重量份以下,则能够将活化能容易地调整为30kJ/mol以上。
树脂片11优选包含热塑性树脂(弹性体)。
作为热塑性树脂,可列举:天然橡胶、丁基橡胶、异戊二烯橡胶、氯丁二烯橡胶、乙烯-乙酸乙烯酯共聚物、乙烯-丙烯酸共聚物、乙烯-丙烯酸酯共聚物、聚丁二烯树脂、聚碳酸酯树脂、热塑性聚酰亚胺树脂、6-尼龙或6,6-尼龙等聚酰胺树脂、苯氧基树脂、丙烯酸类树脂、PET或PBT等饱和聚酯树脂、聚酰胺酰亚胺树脂、氟树脂、苯乙烯-异丁烯-苯乙烯三嵌段共聚物、甲基丙烯酸甲酯-丁二烯-苯乙烯共聚物(MBS树脂)等。这些热塑性树脂可以单独使用或并用2种以上。
树脂片11中的热塑性树脂的含量优选为1重量%以上。若该含量为1重量%以上,则可以赋予柔软性、可挠性。树脂片11中的热塑性树脂的含量优选为30重量%以下。若该含量为30重量%以下,则良好地得到对半导体芯片等的粘接力。
树脂片11优选包含无机填充材料。通过配合无机填充材料,从而提高储藏弹性模量E’,并且可以减小热膨胀系数α。
作为无机填充材料,可列举例如:石英玻璃、滑石、二氧化硅(熔融二氧化硅、结晶性二氧化硅等)、氧化铝、氮化铝、氮化硅、氮化硼等。其中,基于能够良好地降低热膨胀系数的理由,优选二氧化硅、氧化铝,更优选二氧化硅。作为二氧化硅,基于流动性优异的理由,优选熔融二氧化硅,更优选球状熔融二氧化硅。
无机填充材料的平均粒径优选为0.5μm以上、更优选为5μm以上。若该平均粒径为0.5μm以上,则容易得到树脂片11的可挠性、柔软性。无机填充材料的平均粒径优选为50μm以下、更优选为30μm以下。若该平均粒径为50μm以下,则容易将无机填充材料高填充率化。
需要说明的是,例如,可以通过使用从母集团中任意抽取的试样、并采用激光衍射散射式粒度分布测定装置进行测定,从而导出平均粒径。
无机填充材料优选被硅烷偶联剂处理(前处理)过的无机填充材料。由此,可以提高与树脂的润湿性,并且可以提高无机填充材料的分散性。
硅烷偶联剂为在分子中具有水解性基团及有机官能团的化合物。
作为水解性基团,可列举例如:甲氧基、乙氧基等碳数1~6的烷氧基;乙酰氧基、2-甲氧基乙氧基等。其中,基于容易除去利用水解产生的醇等挥发成分的理由,优选甲氧基。
作为有机官能团,可列举:乙烯基、环氧基、苯乙烯基、甲基丙烯酰基、丙烯酰基、氨基、酰脲基、巯基、硫醚基、异氰酸酯基等。其中,基于容易与环氧树脂、苯酚线型酚醛系固化剂反应的理由,优选环氧基。
作为硅烷偶联剂,可列举例如:乙烯基三甲氧基硅烷、乙烯基三乙氧基硅烷等含乙烯基硅烷偶联剂;2-(3,4-环氧环己基)乙基三甲氧基硅烷、3-环氧丙氧基丙基甲基二甲氧基硅烷、3-环氧丙氧基丙基三甲氧基硅烷、3-环氧丙氧基丙基甲基二乙氧基硅烷、3-环氧丙氧基丙基三乙氧基硅烷等含环氧基硅烷偶联剂;对苯乙烯基三甲氧基硅烷等含苯乙烯基硅烷偶联剂;3-甲基丙烯酰氧基丙基甲基二甲氧基硅烷、3-甲基丙烯酰氧基丙基三甲氧基硅烷、3-甲基丙烯酰氧基丙基甲基二乙氧基硅烷、3-甲基丙烯酰氧基丙基三乙氧基硅烷等含甲基丙烯酰基硅烷偶联剂;3-丙烯酰氧基丙基三甲氧基硅烷等含丙烯酰基硅烷偶联剂;N-2-(氨基乙基)-3-氨基丙基甲基二甲氧基硅烷、N-2-(氨基乙基)-3-氨基丙基三甲氧基硅烷、3-氨基丙基三甲氧基硅烷、3-氨基丙基三乙氧基硅烷、3-三乙氧基甲硅烷基-N-(1,3-二甲基-亚丁基)丙胺、N-苯基-3-氨基丙基三甲氧基硅烷、N-(乙烯基苄基)-2-氨基乙基-3-氨基丙基三甲氧基硅烷等含氨基硅烷偶联剂;3-酰脲基丙基三乙氧基硅烷等含酰脲基硅烷偶联剂;3-巯基丙基甲基二甲氧基硅烷、3-巯基丙基三甲氧基硅烷等含巯基硅烷偶联剂;双(三乙氧基甲硅烷基丙基)四硫醚等含硫醚基硅烷偶联剂;3-异氰酸酯丙基三乙氧基硅烷等含异氰酸酯基硅烷偶联剂等。
作为利用硅烷偶联剂对无机填充材料进行处理的方法,并无特别限定,可列举:在溶剂中对无机填充材料和硅烷偶联剂进行混合的湿式法、在气相中对无机填充材料和硅烷偶联剂进行处理的干式法等。
硅烷偶联剂的处理量并无特别限定,优选相对于未处理的无机填充材料100重量份,处理硅烷偶联剂0.1~1重量份。
树脂片11中的无机填充材料的含量优选为20体积%以上、更优选为70体积%以上、进一步优选为74体积%以上。若该含量为20体积%以上,则能够将α×E’容易地调整为10000Pa/K以上。另一方面,无机填充材料的含量优选为90体积%以下、更优选为85体积%以下。若该含量为90体积%以下,则得到良好的凹凸追随性。另外,能够将α×E’容易地调整为300000Pa/K以下。
无机填充材料的含量也可以以“重量%”为单位来进行说明。代表性地对于二氧化硅的含量,以“重量%”为单位进行说明。
二氧化硅的比重通常为2.2g/cm3,因此二氧化硅的含量(重量%)的适合范围例如如以下所示。
即,树脂片11中的二氧化硅的含量优选为81重量%以上、更优选为84重量%以上。树脂片11中的二氧化硅的含量优选为94重量%以下、更优选为91重量%以下。
氧化铝的比重通常为3.9g/cm3,因此氧化铝的含量(重量%)的适合范围例如如以下所示。
即,树脂片11中的氧化铝的含量优选为88重量%以上、更优选为90重量%以上。树脂片11中的氧化铝的含量优选为97重量%以下、更优选为95重量%以下。
除上述成分以外,树脂片11也可以适当含有在密封树脂的制造中通常所使用的配合剂、例如阻燃剂成分、颜料、硅烷偶联剂等。
作为阻燃剂成分,可以使用例如:氢氧化铝、氢氧化镁、氢氧化铁、氢氧化钙、氢氧化锡、复合化金属氢氧化物等各种金属氢氧化物;膦腈化合物等。其中,基于阻燃性、固化后的强度优异的理由,优选膦腈化合物。
作为颜料,并无特别限定,可列举炭黑等。
树脂片11的制造方法并无特别限定,优选将混炼上述各成分(例如环氧树脂、苯酚线型酚醛系固化剂、无机填充材料及固化促进剂等)而得的混炼物塑性加工成片状的方法。由此,可以将无机填充材料进行高填充。
具体而言,通过将环氧树脂、苯酚线型酚醛系固化剂、无机填充材料及固化促进剂等利用混炼机、加压式捏合机、挤出机等公知的混炼机进行熔融混炼,从而制备混炼物,并将所得的混炼物塑性加工成片状。作为混炼条件,温度的上限优选为140℃以下、更优选为130℃以下。温度的下限优选为上述的各成分的软化点以上,例如30℃以上、优选为50℃以上。混炼的时间优选为1~30分钟。另外,混炼优选在减压条件下(减压气氛下)进行,减压条件下的压力为例如1×10-4~0.1kg/cm2
熔融混炼后的混炼物优选不进行冷却而直接以高温状态进行塑性加工。作为塑性加工方法,并无特别限制,可列举平板压制法、T型模挤出法、螺杆式模头挤出法、辊压延法、辊混炼法、吹塑挤出法、共挤出法、压延成形法等。作为塑性加工温度,优选为上述的各成分的软化点以上,若考虑环氧树脂的热固化性及成形性,则例如为40~150℃、优选为50~140℃、进一步优选为70~120℃。
树脂片11的厚度并无特别限定,优选为100μm以上、更优选为150μm以上。另外,树脂片11的厚度优选为2000μm以下、更优选为1000μm以下。若该厚度为上述范围内,则可以将半导体芯片良好地密封。
需要说明的是,在图1中,示出树脂片11为单层的情况,但是树脂片11并不限定于此,也可以为多层。
树脂片11是为了密封半导体芯片而使用的。
[半导体封装体的制造方法]
例如,通过进行以下的工序,从而可以得到半导体封装体。
(准备工序)
在准备工序中,准备倒装芯片安装有多个半导体芯片13的半导体晶片12(参照图2)。通常,在半导体芯片13的电路形成面(活性面)形成有凸块13a。另外,通常在半导体晶片12的电路形成面(活性面)形成有电极12a。通常将半导体芯片13与半导体晶片12电连接。在图2中示出借助凸块13a和电极12a将半导体芯片13与半导体晶片12电连接的例子。半导体芯片13向半导体晶片12的搭载可以使用倒装芯片接合器、芯片接合器等公知的装置。另外,根据需要在半导体芯片13与半导体晶片12之间填充底部填充材料14。
(密封工序)
在密封工序中,将半导体芯片13用树脂片11进行密封(参照图3)。由此,得到具备树脂片11及埋入树脂片11的半导体芯片13的密封体15(半导体封装体15)。作为将半导体芯片13用树脂片11进行密封的方法,例如可列举:在倒装芯片式连接于半导体晶片12的半导体芯片13上层叠树脂片11后,将具备半导体晶片12、倒装芯片式连接于半导体晶片12的半导体芯片13、及配置于半导体芯片13上的树脂片11的层叠体以平行平板方式进行热压,由此,将半导体芯片13埋入树脂片11的方法等。
作为将半导体芯片13埋入树脂片11时的热压条件,温度例如为40~100℃、优选为50~90℃,压力例如为0.1~10MPa、优选为0.5~8MPa,时间例如为0.3~10分钟、优选为0.5~5分钟。另外,若考虑提高树脂片11对半导体芯片13及半导体晶片12的粘附性及追随性,则优选在减压条件下(例如0.1~5kPa)进行压制。
(热固化工序)
对密封体15的树脂片11进行热固化。
对于树脂片11而言,为了满足上述式(1),可以在较低温下进行热固化。热固化处理的条件并无特别限定,例如如以下所示。
作为热固化处理的条件,加热温度优选为100℃以上、更优选为120℃以上。另一方面,加热温度的上限优选为200℃以下、更优选为180℃以下。若加热温度为上述范围,则可以使密封体15的翘曲变小,并且可以降低空隙的产生。
加热时间优选为10分钟以上、更优选为30分钟以上。另一方面,加热时间的上限优选为300分钟以下、更优选为180分钟以下。另外,可以根据需要进行加压,优选为0.1MPa以上、更优选为0.5MPa以上。另一方面,上限优选为10MPa以下、更优选为5MPa以下。
(研削工序)
根据需要对密封体15的树脂片11进行研削(参照图4)。作为研削方法,例如可列举使用高速旋转的磨石的研磨法等。
(再布线层形成工序)
根据需要对密封体15的半导体晶片12进行研削。通过研削可以形成通孔(Via)12b(参照图5)。作为研削方法,例如可列举使用高速旋转的磨石的研磨法等。接着,根据需要对密封体15形成具有布线21的再布线层22(参照图6)。接着,根据需要在布线21上形成凸块23。在图6中示出将孔12b与布线21连接的例子。
(切割工序)
根据需要进行密封体15的切割(参照图7)。由此,可以得到芯片状的半导体封装体16。
(基板安装工序)
根据需要将密封体15或半导体封装体16安装于基板。
(激光标记工序)
激光标记可以在任意时机对密封体15或半导体封装体16进行。例如可以对热固化前的密封体15进行激光标记,也可以对热固化后的密封体15进行激光标记,还可以对半导体封装体16进行激光标记。
[半导体封装体的制造方法]
例如,即使进行以下的工序,也可以得到半导体封装体。以下的工序适合于制造Fan-out(扇出)型晶片级封装体(WLP)。
(暂时固定工序)
首先,在暂时固定材料41固定多个半导体芯片13(参照图8)。此时,根据需要,以半导体芯片13的电路形成面与暂时固定材料41对置的方式进行配置固定。半导体芯片13的固定可以使用倒装芯片接合器、芯片接合器等公知的装置。
暂时固定材料41通常具有支承体42和层叠于支承体42上的粘合剂层43。
作为粘合剂层43,并无特别限定,基于能够容易地剥离的理由,通常使用热剥离性粘合剂层、放射线固化型粘合剂层等。作为支承体42的材料,并无特别限定。例如为SUS等金属材料、聚酰亚胺、聚酰胺亚胺、聚醚醚酮、聚醚砜等塑料材料等。
(密封工序)
在密封工序中,将半导体芯片13用树脂片11进行密封(参照图9)。由此,得到具备树脂片11及埋入树脂片11的半导体芯片13的密封体51。作为将半导体芯片13用树脂片11进行密封的方法,例如可列举:在配置于暂时固定材料41上的半导体芯片13上层叠树脂片11后,对具备暂时固定材料41、配置于暂时固定材料41上的半导体芯片13、及配置于半导体芯片13上的树脂片11的层叠体用平行平板方式进行热压,由此将半导体芯片13埋入树脂片11的方法等。
将半导体芯片13埋入树脂片11时的热压条件可以采用在上述制法中说明的内容。
(热固化工序)
对密封体51进行热固化(对密封体51的树脂片11进行热固化)。
热固化处理的条件可以采用在上述制法中说明的内容。
(剥离工序)
接着,从密封体51剥离暂时固定材料41(参照图10)。剥离方法并无特别限定,优选在使粘合剂层43的粘合力降低后进行剥离。例如,在粘合剂层43为热剥离性粘合剂层的情况下,对粘合剂层43进行加热,使粘合剂层43的粘合力降低后,进行剥离。
(研削工序)
接着,根据需要对密封体51的树脂片11进行研削(参照图11)。作为研削方法,例如可列举使用高速旋转的磨石的研磨法等。
(布线层形成工序)
接着,利用半加成法等,对密封体51形成再布线52(参照图12)。在图12中示出将再布线52与半导体芯片13连接的例子。
之后,在密封体51的形成有再布线52的面形成聚酰亚胺、聚苯并噁唑(PBO)等的绝缘层。绝缘层例如可以通过层压干膜抗蚀剂等膜来形成。
接着,进行在再布线52上形成凸块53的凸块制作(バンピング)加工。凸块制作加工可以利用焊料球、焊料镀敷等公知的方法来进行。
(切割工序)
可以进行具备半导体芯片13、树脂片11及再布线52等的密封体51的切割(参照图13)。根据以上操作,可以得到将布线引出至芯片区域的外侧的半导体封装体61。需要说明的是,可以不切割而将密封体51直接作为半导体封装体来使用。
(基板安装工序)
根据需要将半导体封装体61安装于基板。
(激光标记工序)
激光标记可以在任意时机对密封体51或半导体封装体61进行。例如,可以对热固化前的密封体51进行激光标记,也可以对热固化后的密封体51进行激光标记,还可以对半导体封装体61进行激光标记。
如以上所示,例如,可以通过如下方法来制造半导体封装体16、61,该方法包括:形成具备树脂片11及埋入树脂片11的1个或多个半导体芯片13的密封体15、51的工序(A);和对密封体15、51的树脂片11进行热固化的工序(B)。
在工序(A)中,可以通过将倒装芯片式连接于半导体晶片12的半导体芯片13埋入树脂片11来形成密封体15。此时,在工序(A)中,可以将倒装芯片式连接于半导体晶片12的多个半导体芯片13埋入树脂片11来形成密封体15。而且,上述方法可以还包括:在工序(B)之后按照目标半导体芯片单元对密封体15进行切割的工序(C)。
在工序(A)中,可以通过将固定于暂时固定材料41的半导体芯片13埋入树脂片11来形成密封体51。
实施例
以下,例示性地对本发明的适合的实施例进行详细地说明。但是,关于该实施例中记载的材料、配合量等,只要没有特别限定性的记载,其主旨并非将本发明的范围仅限定为这些实施例。
对实施例中使用的成分进行说明。
环氧树脂A:新日铁化学(株)制的YSLV-80XY(双酚F型环氧树脂、环氧当量200g/eq.软化点80℃)
环氧树脂B:日本化药公司制的EPPN501-HY(环氧当量169g/eq.软化点60℃)
酚醛树脂A:明和化成公司制的MEH-7851-SS(具有联苯芳烷基骨架的苯酚线型酚醛树脂、羟基当量203g/eq.软化点67℃)
酚醛树脂B:明和化成公司制的MEH-7500-3S(苯酚线型酚醛树脂、羟基当量103g/eq.软化点83℃)
固化促进剂A:四国化成工业公司制的2PHZ-PW(2-苯基-4,5-二羟基甲基咪唑)
固化促进剂B:北兴化学工业公司制的TPP-K(四苯基硼四苯基膦)
固化促进剂C:四国化成工业公司制的2E4MZ-A(2,4-二氨基-6-[2’-乙基-4’-甲基咪唑基-(1’)]-乙基均三嗪)
弹性体A:Kaneka公司制的SIBSTAR072T(苯乙烯-异丁烯-苯乙烯三嵌段共聚物)
弹性体B:通过下述合成例1得到的丙烯酸类共聚物(包含丙烯酸丁酯:丙烯腈:甲基丙烯酸缩水甘油酯=85:8:7重量%的共聚物、重均分子量80万)
无机填充材料A:电气化学工业公司制的FB-9454(球状熔融二氧化硅粉末、平均粒径20μm)
无机填充材料B:Admatechs公司制的SO-25R(球状熔融二氧化硅粉末、平均粒径0.5μm)
硅烷偶联剂:信越化学公司制的KBM-403(3-环氧丙氧基丙基三甲氧基硅烷)
炭黑:三菱化学公司制的#20
[合成例1]
使用2,2’-偶氮双异丁腈作为聚合引发剂,在甲乙酮中在氮气气流下将丙烯酸丁酯、丙烯腈、甲基丙烯酸缩水甘油酯按照85:8:7的投入重量比率进行70℃下5小时和80℃下1小时的自由基聚合,从而得到上述丙烯酸共聚物。
[实施例及比较例]
按照表1中记载的配合比,利用混合机将各成分进行掺合,利用双轴混炼机在120℃熔融混炼2分钟,接着,从T型模头挤出,由此制作厚度500μm的树脂片。
[评价]
使用所得的树脂片,进行下述的评价。将结果示于表1中。
(活化能)
活化能使用Friedman(傅里德曼)法按照以下的步骤来计算。
首先,称量10mg树脂片。对10mg的树脂片,使用装置名:Q2000(TAInstruments公司制),在升温速度1degC/min、2degC/min、5degC/min及10degC/min下进行DSC测定,得到DSC曲线。
在所得的DSC曲线中,将放热峰的积分值在峰整体中达到20%的温度设定T1,将达到60%的温度设为T2,将从T1升温至T2所用的时间设为dt,计算出ln(dα/dt)(dα=0.6-0.2=0.4)。
将所得的ln(dα/dt)以各测定条件下的1/T2轴进行绘图,根据各曲线,使用最小二乘法算出曲线(直线)的斜率。曲线的斜率为Ea/R,因此利用其来计算Ea(参照下述式)。
【数1】
ln d α d t = l n [ A f ( α ) ] - E α R 1 T
α:反应率
t:时间
A:Arrhenius的前指数因子
Ea:活化能
R:气体常数
T:成为α的温度
(储藏弹性模量E’的测定)
将树脂片在150℃热固化处理1小时后,使用固体粘弹性测定装置(RheometricScientic公司制:型号:RSA-III),测定了储藏弹性模量。即,通过如下方式获得:将样品尺寸设为长40mm×宽10mm×厚200μm,并将测定试样设置于膜拉伸测定用夹具,在频率1Hz、升温速度10℃/min的条件下测定在-50~300℃的温度区域的拉伸储藏弹性模量及损失弹性模量,读取在25℃的储藏弹性模量(E’)。
(热膨胀率α的测定)
将树脂片在150℃热固化处理1小时后,从热固化物切割长15mm×宽5mm×厚200μm的测定试样。将测定试样设置于热机械测定装置(TAInstruments公司制:型号:Q-400EM)的膜拉伸测定用夹具后,在-50~300℃的温度区域,在拉伸载荷2g、升温速度10℃/min的条件下,由50℃~70℃下的膨胀率计算出热膨胀系数α。
(玻璃化转变温度的测定)
通过将树脂片在150℃进行1小时的加热处理而使其热固化,之后用切刀切割成厚200μm、长40mm(测定长度)、宽10mm的条状,使用固体粘弹性测定装置(RSAIII、RheometricScientic(株)制),测定在-50~300℃的储藏弹性模量及损失弹性模量。测定条件设为频率1Hz、升温速度10℃/min。此外,通过计算tanδ(G”(损失弹性模量)/G’(储藏弹性模量))的值,从而得到玻璃化转变温度。
(固化评价)
使用装置名:Q2000(TAInstruments公司制)对在110℃加热处理5小时后的树脂片和加热处理前的树脂片进行DSC测定,求得放热量(升温速度10℃/min)。将在加热处理后的树脂片中未观测到放热峰的情况、或加热处理后的树脂片的放热量为加热处理前的树脂片的放热量的10%以下的情况判定为“○”。将加热处理后的树脂片的放热量大于加热处理前的树脂片的放热量的10%的情况判定为“×”。
(翘曲评价)
将树脂片层叠于载体(在300mm×400mm×厚1.4mm的玻璃板(TEMPAX玻璃)上层叠暂时固定粘合片(日东电工公司制的No.3195V),进一步地在暂时固定粘合片上按照9mm间隔排列6mm×6mm×厚200μm的半导体元件),在150℃加热1小时。从载体剥离树脂片后,测定树脂片的翘曲量,将翘曲量为1mm以下的情况判定为“○”,将翘曲量大于1mm的情况判定为“×”。
(填充性)
将树脂片层叠于载体(在300mm×400mm×厚1.4mm的玻璃板(TEMPAX玻璃)上层叠暂时固定粘合片(日东电工公司制的No.3195V),进一步地在暂时固定粘合片上按照9mm间隔排列6mm×6mm×厚200μm的半导体元件),在150℃加热1小时。从载体剥离树脂片后,观察树脂片的芯片周边部(半导体元件周边部)。将在芯片周边部无空隙的情况判定为“○”,将有空隙的情况判定为“×”。
(热循环试验)
将树脂片层叠于载体(在300mm×400mm×厚1.4mm的玻璃板(TEMPAX玻璃)上层叠暂时固定粘合片(日东电工公司制的No.3195V),进一步地在暂时固定粘合片上按照9mm间隔排列6mm×6mm×厚200μm的半导体元件),在150℃加热1小时。之后,将层叠体(成形物)单片化,得到半导体封装体。对所得的半导体封装体实施热循环试验(温度-50℃~125℃、1个循环为1小时)。在热循环试验后观察半导体封装体,将在2000个循环以上未产生树脂的裂纹及剥离的情况判定为“◎”,将在1000个循环以上未产生树脂的裂纹及剥离的情况判定为“○”,将产生树脂的裂纹或剥离的情况判定为“×”。
在使用了满足上述式(1)及上述式(2)的树脂片的实施例中,可以降低树脂片的翘曲变形。另外,在实施例中,利用较低温的加热处理(在110℃进行5小时加热处理)来进行热固化反应。另外,在实施例中,通过在150℃进行1小时的加热,从而使树脂片追随载体的凹凸,并在芯片周边部未观察到空隙。另外,在实施例中,在热循环试验中未产生裂纹或剥离。
另一方面,在未满足上述式(1)及上述式(2)的任一者的比较例中,任一性能均变差。例如,在比较例3中,热固化反应的进行加快,无法利用树脂片填充芯片周边部。
符号说明
11树脂片
12半导体晶片
12a电极
12b通孔
13半导体芯片
13a凸块
14底部填充材料
15密封体
16半导体封装体
21布线
22再布线层
23凸块
41暂时固定材料
42支承体
43粘合剂层
51密封体
52再布线
53凸块
61半导体封装体

Claims (11)

1.一种半导体芯片密封用热固化性树脂片,其活化能(Ea)满足下述式(1),且
在150℃热固化处理1小时后的热固化物的玻璃化转变温度为125℃以上,
所述热固化物在所述玻璃化转变温度以下的温度下的热膨胀系数α[ppm/K]及所述热固化物在25℃时的储藏弹性模量E’[GPa]满足下述式(2),
30≤Ea≤120[kJ/mol]···(1)
10000≤α×E’≤300000[Pa/K]···(2)。
2.根据权利要求1所述的半导体芯片密封用热固化性树脂片,其包含环氧树脂、苯酚线型酚醛系固化剂、无机填充材料及固化促进剂。
3.根据权利要求2所述的半导体芯片密封用热固化性树脂片,其中,所述无机填充材料为平均粒径0.5μm~50μm的二氧化硅。
4.根据权利要求2或3所述的半导体芯片密封用热固化性树脂片,其中,所述固化促进剂为咪唑系固化促进剂。
5.根据权利要求2~4中任一项所述的半导体芯片密封用热固化性树脂片,其中,所述无机填充材料的含量为20体积%~90体积%。
6.根据权利要求1~5中任一项所述的半导体芯片密封用热固化性树脂片,其中,所述热固化物在25℃时的储藏弹性模量E’为3GPa~30GPa。
7.根据权利要求1~6中任一项所述的半导体芯片密封用热固化性树脂片,其中,所述热膨胀系数α为3ppm/K~50ppm/K。
8.一种半导体封装体的制造方法,其包括:
工序(A),形成具备权利要求1~7中任一项所述的半导体芯片密封用热固化性树脂片及埋入所述半导体芯片密封用热固化性树脂片的1个或多个半导体芯片的密封体;和
工序(B),对所述密封体的树脂片进行热固化。
9.根据权利要求8所述的半导体封装体的制造方法,其中,在所述工序(A)中,将倒装芯片式连接于半导体晶片的所述半导体芯片埋入所述半导体芯片密封用热固化性树脂片而形成所述密封体。
10.根据权利要求8所述的半导体封装体的制造方法,其中,在所述工序(A)中,将固定于暂时固定材料的所述半导体芯片埋入所述半导体芯片密封用热固化性树脂片而形成所述密封体。
11.根据权利要求8或9所述的半导体封装体的制造方法,其中,在所述工序(A)中,将倒装芯片式连接于所述半导体晶片的多个所述半导体芯片埋入所述半导体芯片密封用热固化性树脂片而形成所述密封体,
在所述工序(B)之后,还包括将所述密封体按照目标半导体芯片单元进行切割的工序(C)。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109890894A (zh) * 2016-11-02 2019-06-14 住友电木株式会社 环氧树脂组合物和结构体
CN111279472A (zh) * 2017-10-31 2020-06-12 长濑化成株式会社 安装结构体的制造方法及其中使用的片材
CN111465638A (zh) * 2017-12-21 2020-07-28 松下知识产权经营株式会社 预浸料、基底、覆金属层压体、半导体封装体和印刷电路板
CN113227284A (zh) * 2018-12-27 2021-08-06 株式会社斗山 半导体封装体用非导电性粘接膜及利用其的半导体封装体的制造方法
CN113423753A (zh) * 2019-02-21 2021-09-21 松下知识产权经营株式会社 半导体封装材料和半导体器件
TWI792364B (zh) * 2020-06-30 2023-02-11 韓商利諾士尖端材料有限公司 用於製造電子裝置的絕緣膜
CN113423753B (zh) * 2019-02-21 2024-06-11 松下知识产权经营株式会社 半导体封装材料和半导体器件

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6792322B2 (ja) * 2015-05-12 2020-11-25 昭和電工マテリアルズ株式会社 半導体装置及び半導体装置の製造方法
TWI618615B (zh) * 2015-08-12 2018-03-21 Zhao Chang Wen Method for forming thermosetting resin package sheet
JP2017088759A (ja) * 2015-11-11 2017-05-25 リンテック株式会社 接着シート
JP6224188B1 (ja) 2016-08-08 2017-11-01 太陽インキ製造株式会社 半導体封止材
US9865570B1 (en) * 2017-02-14 2018-01-09 Globalfoundries Inc. Integrated circuit package with thermally conductive pillar
JP7066975B2 (ja) * 2017-03-10 2022-05-16 味の素株式会社 樹脂組成物、樹脂シート、回路基板及び半導体チップパッケージ
WO2018207862A1 (ja) * 2017-05-10 2018-11-15 三井化学株式会社 半導体装置の製造方法および半導体装置の中間体
CN109300794B (zh) * 2017-07-25 2021-02-02 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
JP6781677B2 (ja) * 2017-08-01 2020-11-04 芝浦メカトロニクス株式会社 電子部品の実装装置と実装方法、およびパッケージ部品の製造方法
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JP7267272B2 (ja) * 2018-06-08 2023-05-01 リンテック株式会社 硬化封止体の製造方法
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JP7221046B2 (ja) * 2018-12-26 2023-02-13 東京応化工業株式会社 接着剤組成物、積層体、積層体の製造方法、及び電子部品の製造方法
JPWO2022190898A1 (zh) * 2021-03-11 2022-09-15

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400657A (zh) * 2001-07-26 2003-03-05 株式会社电装 压铸的功率器件及其制造方法
JP2005060584A (ja) * 2003-08-18 2005-03-10 Hitachi Chem Co Ltd 封止用フィルム
CN1681097A (zh) * 2004-04-09 2005-10-12 株式会社东芝 半导体芯片安装体的制造方法和半导体芯片安装体
JP2006241449A (ja) * 2005-02-07 2006-09-14 San Nopco Ltd 熱硬化性樹脂組成物
JP2012227441A (ja) * 2011-04-21 2012-11-15 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置
CN102812066A (zh) * 2010-03-19 2012-12-05 积水化学工业株式会社 固化性组合物、切割和芯片接合带、连接结构体及带有粘合剂层的半导体芯片的制造方法
JP2013168541A (ja) * 2012-02-16 2013-08-29 Fujitsu Ltd 半導体装置の製造方法及び電子装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2660631B2 (ja) * 1992-03-19 1997-10-08 株式会社日立製作所 樹脂封止型半導体装置
JP4038363B2 (ja) 2000-12-25 2008-01-23 日本特殊陶業株式会社 配線基板
JP4730652B2 (ja) 2004-06-02 2011-07-20 ナガセケムテックス株式会社 電子部品の製造方法
SG160331A1 (en) 2005-03-25 2010-04-29 Sumitomo Bakelite Co Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for encapsulating
EP2024454B1 (en) * 2006-05-16 2012-09-19 Lord Corporation Curable protectant for electronic assemblies
JP5608977B2 (ja) * 2006-12-05 2014-10-22 住友ベークライト株式会社 半導体パッケージ、コア層材料、ビルドアップ層材料および封止樹脂組成物
WO2010041651A1 (ja) * 2008-10-10 2010-04-15 住友ベークライト株式会社 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400657A (zh) * 2001-07-26 2003-03-05 株式会社电装 压铸的功率器件及其制造方法
JP2005060584A (ja) * 2003-08-18 2005-03-10 Hitachi Chem Co Ltd 封止用フィルム
CN1681097A (zh) * 2004-04-09 2005-10-12 株式会社东芝 半导体芯片安装体的制造方法和半导体芯片安装体
JP2006241449A (ja) * 2005-02-07 2006-09-14 San Nopco Ltd 熱硬化性樹脂組成物
CN102812066A (zh) * 2010-03-19 2012-12-05 积水化学工业株式会社 固化性组合物、切割和芯片接合带、连接结构体及带有粘合剂层的半导体芯片的制造方法
JP2012227441A (ja) * 2011-04-21 2012-11-15 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置
JP2013168541A (ja) * 2012-02-16 2013-08-29 Fujitsu Ltd 半導体装置の製造方法及び電子装置の製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109890894A (zh) * 2016-11-02 2019-06-14 住友电木株式会社 环氧树脂组合物和结构体
CN109890894B (zh) * 2016-11-02 2020-04-21 住友电木株式会社 环氧树脂组合物和结构体
CN111279472A (zh) * 2017-10-31 2020-06-12 长濑化成株式会社 安装结构体的制造方法及其中使用的片材
CN111279472B (zh) * 2017-10-31 2023-06-30 长濑化成株式会社 安装结构体的制造方法及其中使用的片材
CN111465638A (zh) * 2017-12-21 2020-07-28 松下知识产权经营株式会社 预浸料、基底、覆金属层压体、半导体封装体和印刷电路板
CN111465638B (zh) * 2017-12-21 2023-02-03 松下知识产权经营株式会社 预浸料、基底、覆金属层压体、半导体封装体和印刷电路板
CN113227284A (zh) * 2018-12-27 2021-08-06 株式会社斗山 半导体封装体用非导电性粘接膜及利用其的半导体封装体的制造方法
CN113423753A (zh) * 2019-02-21 2021-09-21 松下知识产权经营株式会社 半导体封装材料和半导体器件
CN113423753B (zh) * 2019-02-21 2024-06-11 松下知识产权经营株式会社 半导体封装材料和半导体器件
TWI792364B (zh) * 2020-06-30 2023-02-11 韓商利諾士尖端材料有限公司 用於製造電子裝置的絕緣膜

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