CN101164165A - 电路部件、电路部件的制造方法、半导体器件及电路部件表面的叠层结构 - Google Patents

电路部件、电路部件的制造方法、半导体器件及电路部件表面的叠层结构 Download PDF

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CN101164165A
CN101164165A CNA2006800138513A CN200680013851A CN101164165A CN 101164165 A CN101164165 A CN 101164165A CN A2006800138513 A CNA2006800138513 A CN A2006800138513A CN 200680013851 A CN200680013851 A CN 200680013851A CN 101164165 A CN101164165 A CN 101164165A
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circuit block
leading part
plate portion
backing plate
coating
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CN100576525C (zh
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岛崎洋
斋藤启之
增田正亲
松村健司
福地胜
池泽孝夫
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Abstract

本发明提供一种电路部件，其特征在于，其是将轧制铜板或轧制铜合金板进行图案加工形成了具有装载半导体芯片的垫板部和电连接上述半导体芯片的引线部的框架材料的电路部件，其中，该电路部件包含在上述垫板部和上述引线部的上面及侧壁面形成了粗糙面的粗糙面，以及在上述垫板部及上述引线部的下面形成的平滑面，按照使上述引线部的下面露出的形式上述垫板部和上述引线部被埋设于密封树脂中。

Description

电路部件、电路部件的制造方法、半导体器件及电路部件表面的叠层结构
技术领域
本发明涉及电路部件表面的叠层结构、作为电路部件之一的引线框架的表面处理技术及使用该电路部件的半导体器件，进一步详细地涉及与半导体封装的类型相对应提高引线框架与密封树脂之间的粘接强度的技术。
背景技术
作为半导体器件，有具有下述结构的半导体封装：在引线框架中装载IC芯片、LSI芯片等半导体芯片，再用绝缘性树脂进行密封。这样的半导体器件，随着高集成化及小型化的进展，封装结构经过从SOJ(Small Outline J-LeadedPackage-J形引脚小外型封装)或QFP(Quad Flat Package-四侧引脚扁平封装)这样的树脂封装侧壁外部引线突出于外侧的类型，发展到外部引线不突出于外部而按照在树脂封装的里面露出外部引线的形式进行埋设的，QFN(QuadFlat Non-leaded Package-四侧无引脚扁平封装)或SON(Small OutlineNoneleaded Package-无引脚小外型封装)等的薄型这样安装面积小的类型。
作为引线框架，已知有对用绝缘性树脂密封的框架材料的表面实施粗糙面化处理，并在该表面采用镀覆法依次层叠镍(Ni)层、钯(Pd)层的结构(例如，日本特开平11-40720号公报(第4页、图1)：专利文献1)。作为上述粗糙面化处理的方法，其是将引线框架的材料表面用有机酸类的蚀刻液进行化学研磨。
作为其他的引线框架，已知有框架材料的表面被表面侧粗糙面化的镀镍层覆盖的引线框架(例如，日本特开2004-349497号公报(第7页、图3)：专利文献2)。这些粗糙面化的镀镍层，可通过调整镀覆法的条件来形成。
象这样在引线框架的整个面上形成镀镍层，在其上实施镀钯或镀金的方法，由于制造工序的简易化以及适应环境的软钎焊工序的无铅化目的，因而已被广泛进行。
另外，作为与绝缘性树脂粘接的电路部件，除了引线框架之外，还有将车辆的供给电源向车用配件进行分配的电连接箱中使用的连接器的导电板或母线(バスバ一)等。
发明内容
但是，上述专利文献1中记载的有机酸类的蚀刻液，对于用镀覆法形成的铜的表面有效，但存在对于作为引线框架材料的轧制铜板的表面的粗糙面化不太有效的问题。附带地，虽然在用这样的有机酸类的蚀刻液处理轧制铜材料的表面时，表面粗糙度提高，但表面轮廓没有成为针状。因此，用有机酸类的蚀刻液进行粗糙面化处理的引线框架，对于与构成封装的绝缘树脂之间的粘接性不能获得很大的效果。另外，使用有机酸类的蚀刻液的粗糙面化，表面粗糙度(Ra)达到0.15μm，但由铜表面到深3μm必须进行蚀刻，要得到该数值以上的表面粗糙度需要进一步深地进行蚀刻。因此，对于该处理方法，由于蚀刻需要时间因而有不适于实际引线框架生产的情况。
在上述专利文献2中记载的形成以镀覆法被粗糙面化的镀镍层的方法中，为了使表面粗糙度变大则必须将镀镍层变厚，如果达不到1μm以上就不能获得稳定的效果。最近有镀层变薄的倾向，作为镀镍层的厚度希望为0.5μm左右。
可是，在如上述QFN或SON等这样的薄型封装面积小的类型的半导体器件中使用的引线框架，因为外部引线的下面露出于树脂封装的下面，所以外部引线与绝缘性树脂接触面积小。因此，有必要进一步提高引线框架与绝缘性树脂之间的粘接强度。近年来，面向车载用途的半导体器件的需求上升，在用于这样的用途时，由于面临振动或温度变化，所以必须将引线框架与绝缘性树脂之间的粘接强度加强至现有强度以上。
另外，在考虑内部引线实施线接合的领域、或外部引线对安装基板(印刷电路基板)进行软钎焊的领域等的同时，期望具有与封装的类型相对应的功能的引线框架。
因此，本发明的主要目的在于，提供可提高与密封树脂的粘接强度的引线框架和其制造方法以及半导体器件。
另外，本发明的另外的目的在于，提供可用于QFN或SON等封装类型的引线框架和其制造方法以及半导体器件。
进而，本发明的其他的目的在于，提供可提高对于绝缘性树脂的粘接强度的电路部件的表面叠层结构。
本发明的第1个特征为电路部件，其中，将轧制铜板或轧制铜合金板进行图案加工形成了具有在表面装载半导体芯片的垫板部(die pad section)和电连接该半导体芯片的引线部的框架材料，其要点在于，在上述垫板部和上述引线部的上面及侧壁面形成粗糙面的同时，使垫板部和引线部的下面成为平滑面，以使引线部的下面露出的形式被埋设于密封树脂中。
本发明的第2个特征为电路部件，其中，将轧制铜板或轧制铜合金板进行图案加工形成了具有在表面装载半导体芯片的垫板部和电连接该半导体芯片的引线部的框架材料，其要点在于，对垫板部的上面、在引线部上面的连接接合线的部分形成平滑面的同时，在这些平滑面上层叠镀层，在除了形成镀层的区域以及垫板部和上述引线部的下面之外的区域形成粗糙面。
进而，要点在于电路部件中与树脂密封用模具相连接的部分为平滑面。
另外，在本发明中，上述粗糙面的表面粗糙度(Ra)优选为0.3μm以上，进而作为层叠的镀层，优选依次层叠厚度为0.5μm～2μm的镀镍层、厚度为0.005μm～0.2μm的镀钯层、厚度为0.03μm～0.01μm的镀金层。另外，上述的粗糙面，优选用以过氧化氢和硫酸作为主要成分的微蚀刻液处理形成。在这里，所谓微蚀刻液是指稍稍溶解金属的表面，形成由微细的凹凸组成的粗糙面的表面处理剂。
本发明的第3个特征为电路部件的制造方法，其要点在于，具有下述工序：将轧制铜板或轧制铜合金板进行图案加工，制造具有垫板部和引线部的框架材料的工序；在用掩模材料(マスク材)覆盖框架材料的下面的状态下，用以过氧化氢和硫酸作为主要成分的微蚀刻液将框架材料的上面及侧壁面进行粗糙面化处理的工序；剥离掩模材料后，在框架材料的表面层叠镀层的工序。
本发明的第4个特征为电路部件的制造方法，其要点在于，具有下述工序：将轧制铜板或轧制铜合金板进行图案加工，制造具有垫板部和引线部的框架材料的工序；对垫板部的上面、以及引线部接合线被连接的部分层叠镀层的工序；在用掩模材料覆盖框架材料的下面的状态下，使用以过氧化氢和硫酸作为主要成分的微蚀刻液将框架材料进行粗糙面化处理的工序；剥离掩模材料的工序。
在这里，作为在垫板部以及引线部的接合线被连接部分层叠的镀层是2～15μm的镀银层，或是在框架材料上依次层叠镀镍层、镀钯层的镀层。
本发明的第5个特征为半导体器件，其要点在于，具有：电路部件，该电路部件由轧制铜板或轧制铜合金板构成，具有垫板部和引线部，在垫板部和引线部的上面及侧壁面形成了粗糙面，且垫板部和引线部的下面形成平滑面的同时在表面层叠有镀层；半导体芯片，装载在垫板部的上面；接合线，连接该半导体芯片和引线部；以及电绝缘性密封树脂，以露出引线部的下面的形式密封电路部件和半导体芯片和接合线。
本发明的第6个特征为半导体器件，其要点在于，具有：电路部件，该电路部件由轧制铜板或轧制铜合金板构成，具有垫板部和引线部，在垫板部的上面、和引线部的上面连接接合线的部分形成平滑面的同时，在这些平滑面上层叠有镀层，在除了形成这些镀层的区域和垫板部和引线部的下面的区域形成了粗糙面；半导体芯片，装载在垫板部的上面；接合线，连接该半导体芯片和引线部；电绝缘性密封树脂，以露出引线部的下面的形式密封电路部件和半导体芯片和接合线。
本发明的第7个特征为与绝缘性树脂接合的电路部件的表面叠层结构，其要点在于，在由轧制铜板或轧制铜合金板构成的导电性材料的表面，形成表面粗糙度(Ra)为0.3μm以上的粗糙面，在该粗糙面上依次层叠镀镍层、镀钯层，镀镍层的厚度为0.5μm～2μm，镀钯层的厚度为0.005μm～0.2μm。
附图说明
[图1]图1是表示本发明第1实施方式的引线框架的平面图。
[图2]图2是表示本发明第1实施方式的引线框架制造方法的工序剖面图。
[图3]图3是表示本发明第1实施方式的引线框架制造方法的工序剖面图。
[图4]图4是表示本发明第1实施方式的引线框架制造方法的工序剖面图。
[图5]图5是表示本发明第1实施方式的引线框架制造方法的工序剖面图。
[图6]图6是表示本发明第1实施方式的引线框架制造方法的工序剖面图。
[图7]图7是表示本发明第1实施方式的半导体器件制造方法的工序剖面图。
[图8]图8是表示本发明第1实施方式的半导体器件制造方法的工序剖面图。
[图9]图9是表示本发明第1实施方式的半导体器件的剖面图。
[图10]图10是表示本发明实施方式的引线框架的粗糙面化部分的放大剖面图。
[图11]图11是表示粘接强度试验概要的斜视图。
[图12]图12(a)～(d)是表示本发明第2实施方式的引线框架的制造工序的剖面图。
[图13]图13(a)～(d)是表示本发明第2实施方式的半导体器件的制造工序的工序剖面图。
[图14]图14是表示本发明其他实施方式的引线框架的粗糙面化部分的放大剖面图。
[图15]图15(a)～(e)是表示本发明第3实施方式的引线框架的制造工序的工序剖面图。
[图16]图16(a)～(e)是表示本发明第3实施方式的半导体器件的制造工序的剖面图。
具体实施方式
以下，根据附图详细说明本发明实施方式中的电路部件、电路部件的制造方法、半导体器件及电路部件的表面叠层结构。本实施方式，作为电路部件采用引线框架说明本发明。但是，附图为示意图，应注意各材料层的厚度或其比例等与实际的不同。因此，具体的厚度或尺寸应当参考以下的说明来判断。另外，即使在附图相互间当然也包含尺寸的相互关系或比例不同的部分。
[第1实施方式]
图1～图9表示本发明的第1实施方式。图1表示引线框架的平面图，图2～图9表示着眼于图1的A-A剖面的引线框架及半导体器件的制造方法的工序图。
(引线框架的构成)
本实施方式的引线框架1通过将由细长的带状轧制铜板或轧制铜合金板构成的框架材料2，通过蚀刻或模具冲压等方法形成图案，以多个单位图案连接的状态来制造。另外，图1表示引线框架1中的1个单位图案。
如图1所示，引线框架1的1个单位图案，形成于中央，具有：用于装载半导体芯片的矩形的垫板部3；以包围该垫板部3的形式所形成的引线部8；将垫板部3连接在框架材料2上的连接杆6；横向连接引线部8的连接杆7。该引线部8如后述的那样，设定尺寸以达到不从密封树脂15的侧壁向外侧突出的程度。另外，本实施方式中，虽然形成了横向连接引线部8的连接杆7，但是也可省略连接杆7，形成引线部8从框架架2的外框部向垫板部3的边缘延伸的图案。
本实施方式中的引线框架1的上面(装载半导体芯片侧的面)及各图案的侧壁面，如图4或图5所示那样，成为用以过氧化氢和硫酸为主要成分的微蚀刻液实施了粗糙面化处理的粗糙面3A、3B、8A、8B。这些粗糙面3A、3B、8A、8B的表面粗糙度(Ra)设定为0.3μm以上，表面轮廓成为突出成针状的凹凸面。框架材料2的下面(半导体芯片装载面的相反侧的面)形成平滑面。
另外，在包含垫板部3及引线部8等的框架材料2的表面上，如图6所示，形成了镀层10。这里，本实施方式中的镀层10，如图10所示的那样，是在材料2的表面上依次层叠镀镍层17、镀钯层18而成。设定镀镍层17的厚度为0.5μm～2μm、镀钯层18的厚度为0.005μm～0.2μm。另外，镀钯层18是与接合线及焊膏的连接性良好的金属层，可确实进行如图7所示的连接接合线13的线接合、或没有图示的对于安装基板(印刷电路基板)进行软钎焊。
在这样构成的引线框架1中，将粗糙面3A、3B、8A、8B的表面粗糙度设定为0.3μm以上，通过设定构成镀层10的镀镍层17及镀钯层18的厚度范围，粗糙面3A、3B、8A、8B的表面轮廓不会混乱，可保持以镀层10来涂覆针状突起表面而成的形状。因此，将该引线框架1进行树脂密封时，认为产生了含有镀层10的微细突起切入固定于密封树脂的效果。
(引线框架的制造方法)
接着，用图2～图6来说明本实施方式中的引线框架的制造方法。
首先，在本实施方式中，如图2所示，准备已形成垫板部3或引线部8等规定的图案的框架材料2。该框架材料2(轧制铜合金板)的构成材料，可使用例如三菱电机メテシクス制低锡的镍铜合金MF202。
接着，如图3所示的那样，在框架材料2的下面(另一个主表面)，层压作为掩模材料的保护膜9。然后，将框架材料2的没有被保护膜9覆盖的部分，在以过氧化氢和硫酸为主要成分的微蚀刻液中浸渍，进行约90秒的微蚀刻，形成如图4所示的粗糙面3A、3B、8A、8B。这些粗糙面3A、3B、8A、8B的表面轮廓，形成陡峭的针状凹凸。进行这样的粗糙面化处理的结果，粗糙面3A、3B、8A、8B的蚀刻量为2μm，表面粗糙度(Ra)为0.33μm，Sratio为2.08。这里，所谓蚀刻量，是表示蚀刻刻下去的平均深度。Sratio是凹凸面的表面积被测定范围的平面面积除的值。
其后，如图5所示剥离保护膜(掩模材料)9，形成如图6所示的镀层10。这里，该镀层10，如上述是在框架材料2的表面上，依次层叠镀镍层17、镀钯层18而成。另外，镀层10的形成方法，可使用电镀法或化学镀法等公知的方法。在这里，控制镀层的成长使得镀镍层17的厚度在0.5～2μm、镀钯层18的厚度在0.005～0.2μm的范围里。这样完成了引线框架的制造。
按本实施方式的引线框架的制造方法，可缩短蚀刻时间、提高生产率。另外，因为镀层10的厚度薄，所以可抑制昂贵的镀覆液的消耗。
然后，用图7～图9说明半导体器件的制造方法及半导体器件的构成。
如图7所示，在用上述制造方法制造的引线框架1的垫板部3的上面，通过焊膏剂12装载半导体芯片11。其后，进行线接合，引线部8的顶端部和半导体芯片11的对应电极之间用接合线13连接。然后，如图8所示，在引线框架1下面层压防树脂泄漏用保护膜14后，整体用例如环氧树脂组成的密封树脂15制模。其后，通过将密封树脂15及引线框架1一并切断(单片化)成为期望的形状，如图9所示的半导体器件(半导体封装)16得以完成。
在本实施方式的半导体器件16中，引线部8及垫板部3的下面露出于密封树脂15的下面侧。该露出的引线部8，通过软钎焊连接在没有图示的安装基板(印刷电路基板)侧。
这样构成的半导体器件16中，由于除了引线框架1的垫板部3及引线部8的下面以外的表面进行了粗糙面化，所以与树脂15的粘接强度高，可发挥对于振动或温度变化的耐久性。
在此，对轧制铜合金板进行本实施方式的粗糙面化处理的场合与进行有机酸类的处理的场合进行比较。
下表1，比较如本实施方式那样使用以过氧化氢与硫酸为主的微蚀刻液实施粗糙面化处理的例子和如现有那样使用有机酸类(在此例中使用商品名为CZ8100的有机酸类物质)的比较例中的蚀刻量、表面粗糙度(Ra)、Sratio、蚀刻时间。在比较例中，可列举蚀刻量为1μm、2μm、3μm的场合。
表1
处理液     过氧化氢+硫酸类 有机酸类(C28100)的比较例
  蚀刻量     2μm   1μm   2μm   3μm
  表面粗糙度(Ra) 0.33μm 0.085μm 0.105μm 0.152μm
  Sratio     2.08   1.11   1.13   1.20
  蚀刻时间     约1.5分钟   约3分钟   约6分钟   约9分钟
由上述表1可知，在使用有机酸类的比较例中，要得到0.15μm的粗糙度，必须进行深度3μm蚀刻。因此，在得到这以上的粗糙度的场合，有必要进行更深的蚀刻，由于该蚀刻需要时间，所以，不适于实际的引线框架的生产。与此相反，进行本实施方式的粗糙面化处理，可得到蚀刻深2μm、比较例的2倍以上的粗糙度。在本实施方式中，通过使用以过氧化氢和硫酸为主成分的微蚀刻液进行粗糙面化处理，能得到具有细的针状凹凸的表面形状。可以认为该形状对于发挥以数值表示的参数以上的固定效果是有效的。
在本实施方式中为了测定与密封树脂的粘接强度，如图11所示那样测定杯剪切强度(カシプせん断強度)。在铜合金(MF202)的轧制铜合金板上，形成与上述同样的镀层及实施防变色处理，从而制作成粘接强度试验片20。将该粘接强度试验片20在加热板上以220℃进行60秒加热后，再在加热板上以220℃进行60秒加热，进一步在加热板上以240℃进行80秒加热。成型是在125kg/cm的压力下在175℃进行120秒的加热。其后，进一步在175℃进行5小时加热来固化环氧树脂21。
这样成型的环氧树脂21与粘接强度试验片20，如图11所示在箭头方向施加负载，剥离时的负载用粘合面的面积除，求出每单位面积的负载(kN/cm2)。
该结果，作为剪切强度的值而得到以下的值，本实施方式通过进行粗糙面处理，可获得提高与密封树脂的粘接强度的效果。
(1)没有粗糙面化的场合，0.04kN/cm2
(2)有粗糙面化、没有防锈处理的场合，0.42kN/cm2
(3)有粗糙面化、有硅烷类防锈处理的场合，0.54kN/cm2
[第2实施方式]
使用图12及图13说明本发明的第2实施方式。另外，在本实施方式中，与上述第1实施方式相同的部分引用相同的符号而省略说明。
第2实施方式中的电路部件，引线框架表面中与树脂密封用模具连接的部分做成平滑的面、其他的部分进行了粗糙面化的引线框架，具有防止密封树脂成型时树脂毛刺的发生、树脂泄漏的效果。图12(a)，表示与图2同样地形成了图案的框架材料2的剖面。作为部分粗糙化的方法，如图12(b)所示的那样，用以下方法代替图3说明的在框架材料2的下面层叠保护膜的方法，即，隔着橡胶垫27、28用上下一对的蚀刻用夹具29、30夹持框架材料2，将微蚀刻液32由附设在蚀刻用夹具上的喷嘴31向框架材料2喷射规定时间进行微蚀刻，从而形成粗糙面。
此时，橡胶垫28在框架材料2的下面及橡胶垫27在框架材料2的上面中覆盖树脂密封用模具的连接部分，起到掩模材料的作用，在微蚀刻中得到保护而残留了框架材料2的平滑面。
图12(c)表示蚀刻后从蚀刻用夹具中取出框架材料的状态，使下面23及上面中被橡胶垫27覆盖的部分(连接于树脂密封用模具的部分)24作为平滑面而残留，这以外的表面成为粗糙面3A、3B、8A、8B。
接着，如图12(d)所示，在包含垫板部3及引线部8的框架材料2的表面，与上述第1实施方式同样地形成镀层10，引线框架1A得以完成。
图13表示使用上述引线框架1A来制造半导体器件的工序。引线框架1A中，如图13(a)所示，垫板部上面隔着焊膏剂12装载半导体芯片11后，进行线接合，引线部8与半导体芯片11的对应电极相互之间用接合线13连接。
接着，如图13(b)所示，使用树脂密封用模具25以密封树脂15进行制模。树脂制模后，将引线框架从树脂密封用模具25取出的状态示于图13(c)。在该状态下切断引线部的不要部分而成为期望的形状，完成半导体器件(半导体封装)图13(d)。这里，在本实施方式中，因为例示个别制模，所以没有整体制模时用于个片化的切割机切割的工序。
图13(b)由密封树脂进行树脂制模时，与树脂密封用模具25连接的部分的引线框架1A的表面被粗糙面化时，树脂密封用模具25与引线框架1A之间产生间隙，密封树脂进入而成为树脂毛刺，极端的场合密封树脂泄漏于模具外面。在本实施方式中，粗糙面化部分在发挥与上述第1实施方式相同的效果的同时，如上述那样使得与树脂密封用模具25连接部分的引线框架1A的表面成为平滑面，因此树脂密封用模具25与引线框架1A粘接而具有防止树脂毛刺或树脂泄漏的效果。
[第3实施方式]
用图15及图16说明本发明的第3实施方式中的电路部件。另外，本实施方式中，与上述第1实施方式相同的部分采用相同的符号而省略说明。
在本实施方式中，如图15(a)所示，准备由轧制铜合金板构成的框架材料2，所述轧制铜合金板通过蚀刻或模具冲压形成了垫板部3或引线部8等的引线框架的规定的图案。
接着，如图15(b)所示，在框架材料2的垫板上面的装载半导体芯片的部分及引线上面的连接接合线的部分，形成贵金属镀层10B的同时，如图15(c)所示，在框架材料2的下面层叠保护膜(掩模材料)9。
接着，在框架材料2的表面喷射微蚀刻液或将框架材料2浸渍在微蚀刻液中，进行规定时间(约90秒)的微蚀刻，形成如图15(d)所示的3A、3B、8A、8B的粗糙面。在此，框架材料2的表面中施加了贵金属镀层10B的部分和层叠了保护膜9的部分是从微蚀刻中得到保护而残留下的框架材料2表面的平滑面。图15(e)是表示剥离保护膜9而完成的引线框架1的剖面的图，下表面23与贵金属镀层10B保存了平滑面，这以外的表面形成了粗糙面3A、3B、8A、8B。
在此，作为上述的贵金属镀层10B是镀银层，或是在框架材料2表面依次层叠镀镍层、镀钯层的镀层。
图16表示使用按照图15的工序制造的本发明的引线框架，制造QFN(Quad FlatNon-leaded Package—四侧无引脚扁平封装)的工序。图16(a)是表示对应于图15(e)的单位图案被施加了多面的引线框架的剖面图。
接着，如图16(b)所示，根据需要在引线框架下面贴上防止树脂毛刺用的膜，垫板上面隔着焊膏剂12装载半导体芯片11后，进行线接合，引线部8的镀层10B和半导体芯片11的对应电极相互之间用接合线连接。
其后，如图16(c)那样使用树脂密封用模具(整体制模用模具)用密封树脂15进行整体制模(树脂密封)。
接着，为了提高封装时的软钎焊连接性，如图16(d)所示在由密封树脂露出的引线部及垫板部上施加软钎焊镀层22后，在单片化的切断位置26将整体制模的引线框架进行切割机切割，如图16(e)所示那样完成各半导体器件。
即使在该第3实施方式中，也可获得与上述第1实施方式同样的效果。另外，在本实施方式中，只在半导体芯片装载面或线接合面施加镀层，另外，进行软钎焊的引线部8的下面因为施加软钎焊镀层，所以可节约昂贵的贵金属镀覆液，在能控制产品成本降低的同时，可提高线接合性或半导体芯片11的安装性。
[电路部件的表面叠层结构]
接着，用图10说明本发明的电路部件的表面叠层结构。在由轧制铜板或轧制铜合金板构成的作为导电性材料的框架材料2表面，形成了表面粗糙度(Ra)为0.3μm以上的粗糙面8A，该粗糙面8A是依次层叠镀镍层17、镀钯层18而成，优选镀镍层的厚度为0.5～2μm、镀钯层的厚度为0.005～0.2μm。通过形成这样的表面叠层结构，可提高导电性材料和绝缘性树脂之间的粘接强度。另外，如图14所示，也可形成在镀钯层18上层叠厚度为0.003～0.01μm镀金层19的结构。这样的镀金层，具有防止在镀钯层的表面形成氧化膜的效果。
[其他的实施方式]
构成上述实施方式的公开部分的论述及附图不应理解为限定本发明。由该公开内容本领域技术人员可清楚各种替代的实施方式、实施例及运用技术。
例如，在第1、第2及第3的实施方式中，镀层10是层叠1层镀银层、或层叠镀镍层17和镀钯层18这样2层而构成，但也可如图14所示的电路部件的表面叠层结构那样，在镀钯层18上进一步层叠镀金层19而成镀层10。另外，该镀金层19的厚度优选为0.003μm～0.01μm的范围。
在实施第1、第2及第3的实施方式中，适用于封装类型QFN或SON等薄型的封装面积小的类型，当然也可适用于QFP、SOP、FLGA等类型的引线框架，可实现与密封树脂的粘接强度的提高。
进而，在实施第1、第2及第3的实施方式中，虽然采用引线框架作为电路部件进行了说明，但也可适用于在将车辆供给电源向车用配件分配的电气接线箱中使用的连接器的导电板或母线等电路部件。

Claims (20)

1.一种电路部件，其特征在于，其是将轧制铜板或轧制铜合金板进行图案加工形成了具有装载半导体芯片的垫板部和电连接所述半导体芯片的引线部的框架材料的电路部件，其包含在所述垫板部和所述引线部的上面及侧壁面形成了粗糙面的粗糙面、在所述垫板部及所述引线部的下面形成的平滑面，并且，按照使所述引线部的下面露出的形式，所述垫板部和所述引线部被埋设于密封树脂中。
2.根据权利要求1所述的电路部件，其特征在于，包含为了提高接合线与焊膏的连接性而在所述垫板部和所述引线部的表面形成的镀层。
3.一种电路部件，其特征在于，其是将轧制铜板或轧制铜合金板进行图案加工形成了具有装载半导体芯片的垫板部和电连接所述半导体芯片的引线部的框架材料的电路部件，其包含：在所述垫板部上面、在所述引线部上面的连接接合线的部分形成的平滑面；所述平滑面上的镀层；在除了形成所述镀层的区域以及所述垫板部和所述引线部的下面之外的区域形成的粗糙面。
4.根据权利要求3所述的电路部件，其特征在于，所述镀层为镀银层。
5.根据权利要求3所述的电路部件，其特征在于，所述镀层为在所述轧制铜板上依次层叠的镀镍层和镀钯层。
6.根据权利要求3所述的电路部件，其特征在于，所述镀层为在所述轧制铜板上依次层叠的镀镍层、镀钯层、镀金层。
7.根据权利要求3所述的电路部件，其特征在于，所述粗糙面的表面粗糙度(Ra)为0.3μm以上。
8.根据权利要求4所述的电路部件，其特征在于，所述镀银层的厚度为2～15μm。
9.根据权利要求5所述的电路部件，其特征在于，所述镀镍层的厚度为0.5～2μm，所述镀钯层的厚度为0.005～0.2μm。
10.根据权利要求6所述的电路部件，其特征在于，所述镀镍层的厚度为0.5～2μm，所述镀钯层的厚度为0.005～0.2μm，所述镀金层的厚度为0.003～0.01μm。
11.根据权利要求1所述的电路部件，其特征在于，所述粗糙面被用以过氧化氢和硫酸为成分的微蚀刻液处理。
12.一种电路部件的制造方法，其特征在于，对轧制铜板和轧制铜合金板进行图案加工，制造具有垫板部和引线部的框架材料；在用掩模材料覆盖所述框架材料的下面的状态下，用以过氧化氢和硫酸为成分的微蚀刻液将所述框架材料的上面及侧壁面进行粗糙面化；剥离所述掩模材料后，在所述框架材料的表面层叠镀层。
13.一种电路部件的制造方法，其特征在于，对轧制铜板或轧制铜合金板进行图案加工，制造具有垫板部和引线部的框架材料；在所述垫板部的上面、所述引线部的连接接合线的部分层叠镀层；在用掩模材料覆盖层叠了所述镀层的所述框架材料的下面的状态下，用以过氧化氢和硫酸为主成分的微蚀刻液将所述框架材料进行粗糙面化；剥离所述掩模材料。
14.根据权利要求12所述的电路部件的制造方法，其特征在于，层叠所述镀层的工序是在所述框架材料的表面层叠镀银层。
15.根据权利要求12所述的电路部件的制造方法，其特征在于，层叠所述镀层的工序是在所述框架材料的表面依次层叠镀镍层、镀钯层。
16.根据权利要求15所述的电路部件的制造方法，其特征在于，在所述镀钯层上层叠镀金层。
17.一种半导体器件，其特征在于，其包含：
由轧制铜板或轧制铜合金板构成的电路部件，该电路部件包含垫板部及引线部、在所述垫板部和所述引线部的上面及侧壁面形成的粗糙面、在所述垫板部和所述引线部的下面n形成的平滑面以及所述表面的镀层；
在所述垫板部的上面装载的半导体芯片；
连接所述半导体芯片和所述引线部的接合线；以及
按照使所述引线部的下面露出的形式密封所述电路部件、所述半导体芯片及所述接合线的电绝缘性的密封树脂。
18.一种半导体器件，其特征在于，其包含：
由轧制铜板或轧制铜合金板构成的电路部件，该电路部件包含垫板部及引线部、在所述垫板部的上面和在所述引线部的表面的连接接合线的部分形成的平滑面、所述平滑面的镀层、以及在除了形成所述镀层的区域及所述垫板部及所述引线部的背面之外的区域形成的粗糙面；
在所述垫板部的上面装载的半导体芯片；
连接所述半导体芯片和所述引线部的接合线；
按照使所述引线部的下面露出的形式密封所述电路部件、所述半导体芯片及所述接合线的电绝缘性的密封树脂。
19.一种电路部件的表面叠层结构，其特征在于，其是与绝缘性树脂接合的电路部件的表面叠层结构，其包含：由轧制铜板或轧制铜合金板构成的导电性材料的表面所形成的表面粗糙度(Ra)为0.3μm以上的粗糙面；在所述粗糙面依次层叠的镀镍层和镀钯层，所述镀镍层的厚度为0.5～2μm、所述镀钯层的厚度为0.005～0.2μm。
20.根据权利要求19所述的电路部件的表面叠层结构，其特征在于，其进一步包含在所述镀钯层上层叠的厚度为0.003～0.01μm的镀金层。
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