TWI429045B - Circuit member, manufacturing method of circuit member, laminated structure of semiconductor device and circuit member surface - Google Patents

Circuit member, manufacturing method of circuit member, laminated structure of semiconductor device and circuit member surface Download PDF

Info

Publication number
TWI429045B
TWI429045B TW095114961A TW95114961A TWI429045B TW I429045 B TWI429045 B TW I429045B TW 095114961 A TW095114961 A TW 095114961A TW 95114961 A TW95114961 A TW 95114961A TW I429045 B TWI429045 B TW I429045B
Authority
TW
Taiwan
Prior art keywords
plating layer
circuit member
wafer
pad portion
wafer pad
Prior art date
Application number
TW095114961A
Other languages
English (en)
Other versions
TW200731494A (en
Inventor
Yo Shimazaki
Hiroyuki Saito
Masachika Masuda
Kenji Matsumura
Masaru Fukuchi
Takao Ikezawa
Original Assignee
Dainippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dainippon Printing Co Ltd filed Critical Dainippon Printing Co Ltd
Publication of TW200731494A publication Critical patent/TW200731494A/zh
Application granted granted Critical
Publication of TWI429045B publication Critical patent/TWI429045B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01088—Radium [Ra]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

電路構件、電路構件之製造方法、半導體裝置及電路構件表面之層積構造
本發明，係有關於電路構件表面之層積構造，或作為電路構件之一種的導線框表面處理技術，或使用該電路構件的半導體裝置；更詳細來說，係有關對應於半導體封裝之形式，提高導線框與密封樹脂之密合強度的技術。
作為半導體裝置，係有具備於導線框裝載IC晶片、LSI晶片等半導體晶片，並以絕緣性樹脂密封之構造的半導體封裝。此種半導體裝置中，隨著高積體化及小型化的演進，封裝構造也從SOJ(Small Outline J-leaded Package)或QFP(Quad Flat Package)之外部導線從樹脂封裝側壁突出到外側的形式，進展為不使外部導線突出到外側，而以使外部導線在樹脂封裝之背面露出之方式來埋設的QFN(Quad Flat Non-leaded Package)或SON(Small Outline Nonleaded Package)等之較薄且安裝面積較小的形式。
作為導線框，已知有在用絕緣性樹脂密封之框素材表面施加粗面化處理，於此表面依序以鍍法(plating method)層積有鎳(Ni)層、鉑(Pd)層的構造(例如，日本特開平11-40720號公報(第4頁，第1圖)：專利文件1)。作為上述粗面化處理之方法，係將導線框之素材表面，以有機酸系蝕刻液來化學研磨。
作為其他導線框，已知有將框素材之表面，以表面側被粗面化之Ni鍍層覆蓋者(例如，日本特開2004-349497號公報(第7頁，第3圖)：專利文件2)。此種被粗面化之Ni鍍層，可藉由調整鍍法之條件來形成。
如上述般，於導線框全面形成Ni鍍層，在其上施加Pd鍍或Au鍍，係因為製造工程之簡潔化以及環保之銲錫工程無鉛化的目的而被廣泛進行。
又，作為與絕緣性樹脂密合之電路構件，除了導線框之外，還有將車輛之供給電源分配到車用機器的電性連接箱所使用的連接器導電板或匯流排棒。
然而，上述專利文件1所記載之有機酸系蝕刻液，對以鍍法所形成之銅表面較有效，但是對導線框素材亦即壓展銅板表面的粗面化，則有不甚有效的問題。因此，用此種有機酸系蝕刻液來處理壓展銅素材的表面時，雖然表面粗糙渡會上升，但是表面輪廓不會成為針狀構造。故用此種有機酸系蝕刻液進行粗面化處理之導線框，係對於與構成封裝之絕緣性樹脂的密合性，無法得到較大效果者。此外，使用有機酸系蝕刻液之粗面化中，為了將表面粗糙度(Ra)設為0.15μm，必須從銅表面蝕刻到深度3μm為止，而要得到此者以上之粗糙度就必須做更深的蝕刻。從而此處理方法中，因為蝕刻需要時間，故並不適合實際的導線框生產。
以上述專利文件2所記載之鍍法來形成粗面化之Ni鍍層的方法中，為了提升表面粗度，必須加厚Ni鍍層，如果厚度不是1μm以上，就無法得到安定的效果。近來有使鍍層變薄之傾向，而希望Ni鍍層之厚度在0.5μm左右。
然而上述QFN或SON等薄型而安裝面積較小之形式的半導體裝置所使用的導線框中，因為外部導線之下面係露出於樹脂封裝的下面，故外部導線與絕緣性樹脂的接觸面積較小。因此，必須更加提高導線框與絕緣性樹脂的密合強度。近年來，車上用途取向之半導體裝置需求提高，使用於此種用途時，會暴露於震動或溫度變化之下，故導線框與絕緣性樹脂的密合強度必須比先前更加提高。
又，期望有能考慮內部導線中施加有銲線之區域，或外部導線中對安裝基板(印刷配線基板)錫銲之區域等，同時也具有對應封裝形式之功能的導線框。
因此本發明之主要目的，係提供一種可提高與密封樹脂之密合強度的導線框、及其製造方法，以及半導體裝置。
又本發明之其他目的，係提供一種可用於QFN或SON等封裝形式的導線框、及其製造方法，以及半導體裝置。
更且本發明之其他目的，係提供一種可提高對絕緣性樹脂之密合強度的電路構件之表面層積構造。
本發明之第1特徵，係一種電路構件，其將具備表面 裝載有半導體晶片之晶片銲墊部，和電性連接於此半導體晶片之導線部的框素材，以將壓展銅板或壓展銅合金板加以圖案加工來形成的電路構件，其主旨係將晶片銲墊部及導線部之上面及側壁面形成粗面，同時將晶片銲墊部及導線部之下面形成平滑面；使導線部之下面露出地，將晶片銲墊部及導線部埋設於密封樹脂中。
本發明之第2特徵，係一種電路構件，其將具備表面裝載有半導體晶片之晶片銲墊部，和電性連接於此半導體晶片之導線部的框素材，以將壓展銅板或壓展銅合金板加以圖案加工來形成的電路構件，其主旨係將晶片銲墊部之上面，與導線部之上面連接銲線之部分設為平滑面，同時於此平滑面層積鍍層；在形成鍍層區域，及除了晶片銲墊部及上述導線部之下面以外之區域，則形成粗面。
進而，主旨為電路構件中與樹脂密封用模具接觸的部分，係作為平滑面。
另外本發明中，上述粗面之表面粗糙度(Ra)以0.3μm以上為佳；進而作為層積之鍍層，以依序層積厚度0.5~2μm之Ni鍍層，厚度0.005~0.2μm之Pd鍍層，厚度0.003~0.01μm之Au鍍層為佳。又上述之粗面，係以過氧化氫與硫酸作為主成份的微蝕刻液來處理形成為佳。在此作為微蝕刻液，係指少許溶解金屬表面，形成以細微凹凸所構成之粗面的表面處理劑。
本發明之第3特徵，係一種電路構件之製造方法，其主旨係具有將壓展銅板和壓展銅合金板加以圖案加工，來 製作具有晶片銲墊部與導線部之框素材的工程；和在以遮罩材覆蓋框素材之下面的狀態下，將框素材之上面及側壁面，使用以過氧化氫與硫酸作為主成份之微蝕刻液來粗面化的工程；和剝除遮罩材後，於框素材之表面層積鍍層的工程。
本發明之第4特徵，係一種電路構件之製造方法，其主旨係將壓展銅板和壓展銅合金板加以圖案加工，來製作具有晶片銲墊部與導線部之框素材的工程；和在晶片銲墊部之上面，與導線部中連接有銲線之部分，層積鍍層的工程；和在以遮罩材覆蓋框素材之下面的狀態下，將框素材之上面及側壁面，使用以過氧化氫與硫酸作為主成份之微蝕刻液來粗面化的工程；和剝除遮罩材的工程。
在此，作為於晶片銲墊部與導線部中連接有銲線之部分，所層積之鍍層，係2~15μm之Ag鍍層，或在框素材上依序層積Ni鍍層、Pd鍍層的鍍層。
本發明之第5特徵，係一種半導體裝置，其主旨係具備由壓展銅板或壓展銅合金板所構成的電路構件，e9電路構件係具備晶片銲墊部與導線部，在晶片銲墊部及導線部之上面及側壁面形成有粗面，且晶片銲墊部及導線部之下面作為平滑面，同時表面層積有鍍層；和裝載於晶片銲墊部上面的半導體晶片；和連接半導體晶片與導線部的銲線；和以使導線部之下面露出之方式來密封電路構件、半導體晶片及銲線的電性絕緣性之密封樹脂。
本發明之第6特徵，係一種半導體裝置，其主旨係具 備由壓展銅板或壓展銅合金板所構成的電路構件，該電路構件係具備晶片銲墊部與導線部，將晶片銲墊部上面及導線部上面連接有銲線之部份，作為平滑面，同時於此等平滑面層積有鍍層，在形成此鍍層之區域，及除了晶片銲墊部及導線部之下面以外之區域，形成粗面；和裝載於晶片銲墊部上面的半導體晶片；和連接半導體晶片與導線部的銲線；和以使導線部之下面露出之方式來密封電路構件、半導體晶片及銲線的電性絕緣性之密封樹脂。
本發明之第7特徵，係一種電路構件表面之層積構造，其與絕緣性樹脂黏合；其主旨係在壓展銅板或壓轉銅合金板所構成之導電性素材表面，形成表面粗糙度(Ra)為0.3μm以上的粗面；在此粗面依序層積Ni鍍層、Pd鍍層；Ni鍍層之厚度係0.5~2μm，Pd鍍層之厚度係0.005~0.2μm。
以下，依據圖示詳細說明本發明實施方式中的電路構件、電路構件之製造方法，半導體裝置及電路構件表面之層積構造。本實施方式中，係將本發明適用為導線框作為電路構件來說明。惟，圖示係示意者，應注意各材料層之厚度或其比例與現實不同。從而，具體厚度或尺寸應參考以下說明來判斷。又，圖示互相之間當然也包含互相尺寸關係或比例不同的部分。
[第1實施方式]
第1圖~第9圖，係表示本發明第1實施方式。第1圖係導線框之俯視圖，第2圖~第9圖係著眼於第1圖之A-A剖面，表示導線框及半導體裝置之製造方法的工程圖。
(導線框之構造)
本實施方式之導線框1，係將細長緞帶狀之壓展銅板或壓展銅合金板所構成的框素材2，藉由蝕刻或模具打穿來形成圖案，以複數單位之圖案連續的狀態來製造。另外，第1圖係表示導線框1中的1單位圖案。
如第1圖所示，導線框1之1單位圖案，係具備形成於中央之用以裝載半導體晶片的矩形晶片銲墊部3；和以包圍此晶片銲墊部3之方式形成的導線部8；和將晶片銲墊部3連結於框素材2的繫桿6；和在橫方向連結導線部8的繫桿7。此導線部8，係如後所述，設定為不會從密封樹脂15側壁往外側突出之程度的尺寸。另外本實施方式中，雖然形成有在橫方向連結導線部8的繫桿7，但亦可省略繫桿7，使導線部8形成為從框2之外框部向著晶片銲墊部3之週邊延伸的圖案。
本實施方式之導線框1之上面(裝載半導體晶片側之面)及各圖案之側壁面，係如第4圖及第5圖所示，使用以過氧化氫與硫酸作為主成分之微蝕刻液，成為施加粗面化處理的粗面3A、3B、8A、8B。此等粗面3A、3B、8A 、8B之表面粗糙度(Ra)，係設定在0.3μm以上，表面輪廓成為突出為針狀的凹凸面。框素材2之下面(裝載半導體晶片之相反側之面)，則形成平滑面。
又，包含晶片銲墊部3與導線部8等之框素材2的表面，係如第6圖所示，形成有鍍層10。另外本實施方式中之鍍層10，係如第10圖所示，在框素材2表面依序層積Ni鍍層17、Pd鍍層18而成。然後將Ni鍍層17之厚度設定為0.5~2μm，將Pd鍍層18之厚度設定為0.005~0.2μm。另外Pd鍍層18，係與銲線及銲錫黏膠之連接性良好的金屬層，而可以確實進行第7圖所示之連接銲線13的打線，或對未圖示之安裝基板(印刷配線基板)的錫銲。
此種構造之導線框1中，將粗面3A、3B、8A、8B之表面粗糙度(Ra)設定在0.3μm以上，並設定構成鍍層10之Ni鍍層17及Pd鍍層18的厚度區域，藉此不會使粗面3A、3B、8A、8B之表面輪廓崩潰，而可保持以鍍層10來塗佈針狀突起表面的形狀。因此將此導線框1做樹脂密封時，包含鍍層10之細微突起會咬入密封樹脂，而可想見達成樁(Anchor)效果。
(導線框之製造方法)
其次，使用第2圖~第6圖說明本實施方式的導線框之製造方法。
首先本實施方式中，如第2圖所示，準備有晶片銲墊 部3或導線部8等之形成特定圖案的框素材2。此框素材2(壓展銅合金板)之構成材料，係例如日本三菱電機Metecs製造，低錫，Ni銅合金MF202。
其次如第3圖所示，在框素材2之下面(一邊的主要面)，層疊上保護膜9作為遮罩材。然後將框素材2中沒有覆蓋保護膜9的部分，浸泡於以過氧化氫與硫酸為主成分之微蝕刻液中，進行約90秒的微蝕刻，而形成如第4圖所示之粗面3A、3B、8A、8B。此等粗面3A、3B、8A、8B之表面輪廓，會成為陡急的針狀凹凸。進行了此種粗面化處理的結果，粗面3A、3B、8A、8B之蝕刻量為2μm，表面粗糙度(Ra)為0.33μm，S比為2.08。另外所謂蝕刻量，係表示以蝕刻挖下之平均深度。S比係將凹凸面之表面積，以測定區域平面之面積來除的值。
之後如第5圖所示，剝除保護膜9(遮罩材)，形成如第10圖所示的鍍層10。另外此鍍層10，係如上所述，在框素材2表面依序層積Ni鍍層17、Pd鍍層18所形成。另外鍍層10之形成方法，可使用電鍍法或無電解鍍法等已知方法。在此，係使Ni鍍層之厚度為0.5~2μm，Pd鍍層之厚度為0.005~0.2μm地，來控制鍍層10的澱積。如此一來，則結束導線框的製造。
本實施方式之導線框的製造方法中，可縮短蝕刻時間而提高生產性。又因為鍍層10之厚度較薄，故可抑制昂貴蝕刻液的消耗。
其次，使用第7圖~第9圖說明半導體裝置之製造方 法及半導體裝置的構造。
如第7圖所示，以上述製造方法所製造之導線框1的晶片銲墊部3上面，係經由黏著劑12裝載半導體晶片11。之後，進行打線，以銲線13連接導線部8的前端部和半導體晶片11的對應電極之間。其次如第8圖所示，在導線框1之下面層疊樹脂洩漏防止用保護薄膜14之後，將整體以例如環氧樹脂所構成的密封樹脂15來模造。之後使其成為期望形狀地，將密封樹脂15及導線框1一起切斷(單片化)，藉此完成第9圖所示之半導體裝置(半導體封裝)16。
本實施方式之半導體裝置16中，導線部8及晶片銲墊部3之下面，係在密封樹脂15的下面側露出。此露出之導線部8，係藉由錫銲連接於未圖示之安裝基板(印刷配線基板)側。
如此構成之半導體裝置16中，因為將晶片銲墊部3，及導線部8下面以外之表面粗面化，故與密封樹脂15之密合強度較高，可發揮對震動或溫度變化的耐久性。
在此，比較對壓展銅合金板進行本實施方式之粗面化處理的情況，和進行有機酸系處理的情況。
下面第1表，係如本實施方式般，使用以過氧化氫與硫酸為主成分之微蝕刻液，施加粗面化處理的例子；和如先前一般，使用有機酸系(此例中係使用商品名稱CZ8100)的比較例，對其比較蝕刻量、表面粗糙度(Ra)、S比、蝕刻時間者。比較例中，係舉出蝕刻量為1μm、 2μm、3μm的例子。
由上述第1表，得知使用有機酸系之比較例中，為了得到0.15μm之粗糙度，必須蝕刻3μm。因此要得到該者以上之粗糙度時，必須蝕刻的更深，而此蝕刻需要時間，故不適合實際的導線框生產。相對地，若進行本實施方式之粗面化處理，則以蝕刻深度2μm就可得到比較例2倍以上的粗糙度。本實施方式中，藉由使用以過氧化氫與硫酸為主成分之微蝕刻液，施加粗面化處理，可得到具有較細之針狀凹凸的表面形狀。此形狀，可有效取得以數值所表示之參數以上的樁效果。
為了測定本實施方式中與密封樹脂的密合強度，係測定如第1圖所示之杯剪斷強度。在銅合金(MF202)之壓展銅合金板上，施加與上述相同之鍍層形成以及防止變色處理，來製作密合強度實驗片20。將此密合強度實驗片20放在加熱板上以220℃、加熱60秒之後，更在加熱板上以220℃、加熱60秒，更且在加熱板上以240℃、加熱 80秒。成型，則是在125kg/cm之壓力下以175℃、加熱120秒。之後更以175℃進行5小時之加熱，使環氧樹脂21硬化。
對如此成型之環氧樹脂21與密合強度實驗片20，在第11圖所示之箭頭方向施加負重，以黏著面之面積來除剝落時之負重，求出每單位面積之負重(kN/cm2 )。
結果，作為剪斷強度值可得到以下數值，藉由進行本實施方式之粗面處理，可得到提高與密封樹脂之密合強度的效果。
(1)無粗面化時，為0.04kN/cm2
(2)有粗面化，無防鏽處理時，為0.42kN/cm2
(3)有粗面化，並有矽烷系防鏽處理時，為0.54kN/cm2
[第2實施方式]
使用第12圖及第13圖，說明本發明第2實施方式。另外本實施方式中與上述第1實施方式相同的部分，係附加相同符號而省略說明。
第2實施方式之電路構件，係藉由將導線框表面中與樹脂密封用模具接觸的部分作為平滑面，而其他部分作為粗面的導線框，來具有防止密封樹脂成型時之樹脂擴張之產生，或防止樹脂洩漏的效果。第12圖(a)係與第2圖一樣表示形成有圖案之框素材2的剖面。做為部份粗糙化之方法，係如第12圖(b)所示，取代第3圖說明之在框 素材2下面層疊保護膜的方法，而經由橡膠包裝27、28以上下一對蝕刻用治具29、30來包夾框素材2，從附加在蝕刻用治具19之噴嘴31，對框素材2噴射微蝕刻液32特定時間，進行微蝕刻而形成粗面。
此時，橡膠包裝28覆蓋框素材2之下面，橡膠包裝27則覆蓋框素材2之上面中與樹脂密封用模具接觸的平滑部分，達到遮罩材之工作，保護其不受到微蝕刻而留下框素材2的平滑面。
第12圖(c)係表示蝕刻後，從蝕刻用治具取出框素材2的狀態；下面23及上面中被橡膠包裝27覆蓋的部分(接觸樹脂密封用模具的部分)24會殘留為平滑面，此外之表面則成為粗面3A、3B、8A、8B。
其次如第12圖(d)所示，在包含晶片銲墊部3及導線部8之框素材2表面，與上述第1實施方式一樣形成鍍層10，而完成導線框1A。
第13圖表示使用上述導線框1A製造半導體裝置的工程。於導線框1A，如第13圖(a)所示，在晶片銲墊部上面經由黏著劑12裝載半導體晶片11之後，進行打線，藉由銲線13將導線部8與半導體晶片11之對應電極彼此加以連接。
其次如第13圖(b)所示，使用樹脂密封用模具25來以密封樹脂15模造。第13圖(c)表示在樹脂模造之後，從樹脂密封用模具25取出導線框的狀態。在此狀態下將導線部之多餘部分切斷為期望形狀，而完成半導體裝 置(半導體封裝)第13圖(d)。另外本實施方式中，因為例舉個別模造，故沒有一起模造時之單片化所需的切片器切割工程。
在第13圖(b)之密封樹脂所帶來的樹脂模造時，若將與樹脂密封用模具25接觸之部分的導線框1A表面加以粗面化，則樹脂密封用模具25與導線框1A之間會產生空隙，使密封樹脂滲入而形成樹脂擴張，嚴重之情況下，密封樹脂會洩漏到模具外。本實施方式中，被粗面化之部分係與上述第1實施方式達到相同效果；同時因為如上述般，將與樹脂密封用模具25接觸之部分的導線框1A表面作為平滑面，故樹脂密封用模具25與導線框1A會密合，而有防止樹脂擴張或樹脂洩漏的效果。
[第3實施方式]
使用第15圖及第16圖，說明本發明第3實施方式之電路構件。另外本實施方式中與上述第1實施方式相同的部分，係附加相同符號而省略說明。
本實施方式中，係如第15圖(a)所示，準備藉由蝕刻或模具打穿，而形成有晶片銲墊部3或導線部8等導線框之特定圖案的，壓展銅合金所構成之框素材2。
其次如第15圖(b)所示，在框素材2之晶片銲墊上面裝載有半導體晶片的部分，以及導線上面連接有銲線的部分，形成貴金屬鍍層10B；同時如第15圖(c)所示，在框素材2下面層疊保護薄膜(遮罩材)9。
其次，對框素材2表面噴射微蝕刻液，或將框素材2浸泡於微蝕刻液，進行特定時間(例如90秒)的微蝕刻，而形成如第15圖(d)所示的粗面3A、3B、8A、8B。在此，框素材2表面中施加有貴金屬鍍層10B之部分，和層疊有保護薄膜9之部分，係被保護不受到微蝕刻而留下框素材2表面的平滑面。第15圖(e)，係表示剝除保護薄膜9而完成之導線框1其剖面的圖；下面23與貴金屬鍍層10B係保存為平滑面，此外之表面則形成為粗面3A、3B、8A、8B。
在此，作為上述貴金屬鍍層10B，係層積有Ag鍍層、或在框素材2表面依序層積Ni鍍層、Pd鍍層而成的鍍層。
第16圖，係表示使用以第15圖之工程所製造之本發明導線框，來製造QFN(Quad Flat Non-leaded Package，四面扁平無腳封裝)的工程。第16圖(a)係表示對應第15圖(e)之多面附加有單位圖案之導線框的剖面圖。
其次如第16圖(b)所示，在導線框下面因應必要而黏貼樹脂擴張防止用薄膜，於晶片銲墊上面經由黏著劑12裝載半導體晶片11之後，進行打線，藉由銲線13將導線部8之鍍層10B與半導體晶片11之對應電極彼此加以連接。
之後，如第16圖(c)般使用樹脂密封用模具(一併模造用模具)25，以密封樹脂15來一併模造(樹脂密封)。
其次為了提高安裝時之銲錫連接性，係如第16圖(d)所示，對從密封樹脂露出之導線部及晶片銲墊部施加銲錫鍍層22之後，在單片化之切斷位置26將一併模造之導線框加以切片切斷，而如第16圖(e)所示般完成半導體裝置。
此第3實施方式中，亦可得到與上述第1實施方式相同的效果。另外本實施方式中，僅對半導體晶片裝載面或銲線面施加鍍層，又，進行錫銲之導線部8下面施加有銲錫鍍，故可節省昂貴的貴金屬鍍液，壓低製品成本，而可提高打線性或半導體晶片11的安裝性。
[電路構件之表面層積構造]
其次，使用第10圖說明本發明之電路構件的表面層積構造。作為壓展銅板或壓展銅合金版所構成之導電性素材，在框素材2之表面，形成表面粗糙度(Ra)0.3μm以上的粗面8A；於此粗面8A，依序層積Ni鍍層17、Pd鍍層18；Ni鍍層17之厚度以0.5~2μm，Pd鍍層18之厚度以0.005~0.2μm為佳。藉由作為此種表面層積構造，可提高導電性素材與絕緣性樹脂的密合強度。又，亦可如第14圖所示，作為在Pd鍍層18上層積厚度0.003~0.01μm之Au鍍層19的構造。此種Au鍍層，有防止Pd鍍層表面形成氧化層的效果。
[其他實施方式]
構成上述實施方式之揭示中一部分的敘述及圖示，應理解其並非限定本發明者。從此揭示，業者可得之各種替代實施方式、實施例及應用技術。
例如第1、第2、第3實施方式中，係將鍍層10作為Ag鍍層1層，或層積Ni鍍層17與Pd鍍層18等2層的構造；但是如第14圖所示之電路構件的表面層積構造般，在Pd鍍層18上更加層積Au鍍層19的鍍層10A亦可。另外此Au鍍層19之厚度，以0.003~0.01μm的區域為佳。
上述第1、第2及第3實施方式中，作為封裝形式雖適用QFN或SON等薄型而安裝面積較小的形式，但當然亦可適用QFP、SOP、FLGA等形式的導線框，而可謀求與密封樹脂的密合強度提高。
更且，上述第1、第2及第3實施方式中，作為電路構件雖適用說明了導線框，但亦可適用於將車輛之供給電源分配到車用機器的電性連接箱，所使用的連接器導電板或匯流排棒等電路構件。
1‧‧‧導線框
1A‧‧‧導線框
2‧‧‧框素材
3‧‧‧晶片銲墊部
3A‧‧‧粗面
3B‧‧‧粗面
6‧‧‧繫桿
7‧‧‧繫桿
8‧‧‧導線部
8A‧‧‧粗面
8B‧‧‧粗面
9‧‧‧保護薄膜
10‧‧‧鍍層
10A‧‧‧鍍層
10B‧‧‧鍍層
11‧‧‧半導體晶片
12‧‧‧黏著劑
13‧‧‧銲線
14‧‧‧樹脂洩漏防止用保護薄膜
15‧‧‧密封樹脂
16‧‧‧半導體裝置
17‧‧‧Ni鍍層
18‧‧‧Pd鍍層
19‧‧‧Au鍍層
20‧‧‧密合強度實驗片
21‧‧‧環氧樹脂
22‧‧‧鍍層
23‧‧‧下面
24‧‧‧上面
25‧‧‧樹脂密封用模具
26‧‧‧切斷位置
27‧‧‧橡膠包裝
28‧‧‧橡膠包裝
29‧‧‧蝕刻用治具
30‧‧‧蝕刻用治具
32‧‧‧微蝕刻液
【第1圖】第1圖，係表示本發明第1實施方式之導線框的俯視圖
【第2圖】第2圖，係表示本發明第1實施方式之導線框之製造方法的工程剖面圖
【第3圖】第3圖，係表示本發明第1實施方式之導 線框之製造方法的工程剖面圖
【第4圖】第4圖，係表示本發明第1實施方式之導線框之製造方法的工程剖面圖
【第5圖】第5圖，係表示本發明第1實施方式之導線框之製造方法的工程剖面圖
【第6圖】第6圖，係表示本發明第1實施方式之導線框之製造方法的工程剖面圖
【第7圖】第7圖，係表示本發明第1實施方式之半導體裝置之製造方法的工程剖面圖
【第8圖】第8圖，係表示本發明第1實施方式之半導體裝置之製造方法的工程剖面圖
【第9圖】第9圖，係表示本發明第1實施方式之半導體裝置的剖面圖
【第10圖】第10圖，係本發明實施方式之導線框中粗面化部份的放大剖面圖
【第11圖】第11圖，係表示密合強度實驗之概要的立體圖
【第12圖】第12圖(a)~(d)，係表示本發明第2實施方式之導線框之製造工程的剖面圖
【第13圖】第13圖(a)~(d)，係表示本發明第2實施方式之半導體裝置之製造工程的工程剖面圖
【第14圖】第14圖，係本發明其他實施方式之導線框中粗面化部份的放大剖面圖
【第15圖】第15圖(a)~(e)，係表示本發明第3 實施方式之導線框之製造工程的工程剖面圖
【第16圖】第16圖(a)~(e)，係表示本發明第3實施方式之半導體裝置之製造工程的剖面圖
1‧‧‧導線框
2‧‧‧框素材
3‧‧‧晶片銲墊部
6‧‧‧繫桿
7‧‧‧繫桿
8‧‧‧導線部

Claims (20)

  1. 一種電路構件，係將具備裝載半導體晶片之晶片銲墊部和電性連接於上述半導體晶片之導線部的框素材，以將壓展銅板或壓展銅合金板加以圖案加工來形成的電路構件，其特徵：包含：形成在上述晶片銲墊部及上述導線部之上面及側壁面的粗面；形成在上述晶片銲墊部及上述導線部之下面的平滑面；及形成在上述晶片銲墊部及上述導線部之粗面的鍍層；以使上述導線部之下面露出之方式，將上述晶片銲墊部及上述導線部埋設於密封樹脂中；於形成在上述導線部之粗面的上述鍍層表面形成粗面，並於上述鍍層表面的粗面連接銲線。
  2. 一種電路構件，係將具備裝載半導體晶片之晶片銲墊部和電性連接於上述半導體晶片之導線部的框素材，以將壓展銅板或壓展銅合金板加以圖案加工來形成的電路構件，其特徵為：包含：形成在上述晶片銲墊部之上面的裝載半導體晶片的部份與上述導線部上面之連接銲線之部分的平滑面；上述平滑面上的鍍層；及形成在上述晶片銲墊部上面之未裝載上述半導體晶片 的部份及側壁部的粗面，與形成在上述導線部上面之未連接上述銲線的部份及側壁面的粗面；裝載半導體晶片的部分之上述晶片銲墊部的上面及上述鍍層的上面為平滑面。
  3. 如申請專利範圍第2項所記載之電路構件，其中，上述鍍層係Ag鍍層。
  4. 如申請專利範圍第2項所記載之電路構件，其中，上述鍍層係在上述壓展銅板上依序層積的Ni鍍層和Pd鍍層。
  5. 如申請專利範圍第2項所記載之電路構件，其中，上述鍍層係在上述壓展銅板上依序層積的Ni鍍層、Pd鍍層，Au鍍層。
  6. 如申請專利範圍第2項所記載之電路構件，其中，上述粗面之表面粗糙度(Ra)為0.3μm以上。
  7. 如申請專利範圍第3項所記載之電路構件，其中，上述Ag鍍層之厚度係2~15μm。
  8. 如申請專利範圍第4項所記載之電路構件，其中，上述Ni鍍層之厚度係0.5~2μm，上述Pd鍍層之厚度係0.005~0.2μm。
  9. 如申請專利範圍第5項所記載之電路構件，其中，上述Ni鍍層之厚度係0.5~2μm，上述Pd鍍層之厚度係0.005~0.2μm，上述Au鍍層之厚度係0.003~0.01μm。
  10. 如申請專利範圍第1項所記載之電路構件，其中，上述粗面係以過氧化氫與硫酸作為成份的微蝕刻液來處理。
  11. 一種電路構件之製造方法，其特徵為：將壓展銅板和壓展銅合金板加以圖案加工，來製作具有晶片銲墊部與導線部的框素材；在以遮罩材覆蓋上述框素材之下面的狀態下，將上述框素材之上面及側壁面，使用以過氧化氫與硫酸作為成份的微蝕刻液來加以粗面化；剝除上述遮罩材後，於上述框素材之表面層積鍍層；上述鍍層，係在上述導線部的粗面上，以上述鍍層表面成為粗面之方式形成，並於上述鍍層表面的粗面連接銲線。
  12. 一種電路構件之製造方法，其特徵為：將壓展銅板或壓展銅合金板加以圖案加工，來製作具有晶片銲墊部與導線部的框素材；在上述晶片銲墊部之上面的裝載半導體晶片之部分，和上述導線部之連接有銲線的部分，層積鍍層；在以遮罩材覆蓋上述層積鍍層的上述晶片銲墊部及上述導線部之下面的狀態下，以維持裝載上述半導體晶片之部分的上述晶片銲墊部上面的平滑面及上述鍍層上面的平滑面之方式，將上述晶片銲墊部上面之未裝載上述半導體晶片的部份及側壁部，與上述導線部上面之未連接上述銲線的部份及側壁面，使用以過氧化氫與硫酸作為主成份的微蝕刻液來加以粗面化；剝除上述遮罩材。
  13. 如申請專利範圍第11項所記載之電路構件之製造 方法，其中，層積上述鍍層之工程，係在上述框素材之表面層積Ag鍍層。
  14. 如申請專利範圍第11項所記載之電路構件之製造方法，其中，層積上述鍍層之工程，係在上述框素材表面上依序層積Ni鍍層和Pd鍍層。
  15. 如申請專利範圍第14項所記載之電路構件之製造方法，其中，在上述Pd鍍層上，層積Au鍍層。
  16. 一種半導體裝置，其特徵為：包含：由壓展銅板或壓展銅合金板所構成的電路構件，該電路構件係包含：晶片銲墊部與導線部、形成在上述晶片銲墊部及上述導線部之上面及側壁面的粗面、形成在上述晶片銲墊部及上述導線部之下面的平滑面、及形成在上述晶片銲墊部及上述導線部之粗面的鍍層；裝載於上述晶片銲墊部上面的半導體晶片；連接上述半導體晶片與上述導線部的銲線；及以使上述導線部之下面露出之方式，來密封上述電路構件、上述半導體晶片及上述銲線的電性絕緣性之密封樹脂；於形成在上述導線部的粗面之上述鍍層表面形成粗面，並於上述鍍層表面連接銲線。
  17. 一種半導體裝置，其特徵為：包含：由壓展銅板或壓展銅合金板所構成的電路構件，該電 路構件係包含：晶片銲墊部與導線部、形成在上述晶片銲墊部上面之裝載半導體晶片的部份與上述導線部表面連接有銲線之部份的平滑面、上述平滑面的鍍層、及形成在上述晶片銲墊部上面之未裝載上述半導體晶片的部份及側壁部的粗面，與形成在上述導線部上面之未連接上述銲線的部份及側壁面的粗面；裝載於上述晶片銲墊部上面的半導體晶片；連接上述半導體晶片與上述導線部的銲線；及以使上述導線部之下面露出之方式，來密封上述電路構件、上述半導體晶片及上述銲線的電性絕緣性之密封樹脂；裝載半導體晶片的部分之上述晶片銲墊部的上面及上述鍍層的上面為平滑面。
  18. 一種電路構件，係將具備裝載半導體晶片之晶片銲墊部和電性連接於上述半導體晶片之導線部的框素材，以將壓展銅板或壓展銅合金板加以圖案加工來形成的電路構件，其特徵：在上述晶片銲墊部及上述導線部之上面及側壁面形成粗面，並且上述晶片銲墊部及上述導線部之下面為平滑面；上述導線部之上面的與樹脂密封用模具接觸的部分為平滑面；以使上述導線部之下面露出之方式，將上述晶片銲墊部及上述導線部埋設於密封樹脂。
  19. 一種電路構件之製造方法，其特徵為：將壓展銅板或壓展銅合金板加以圖案加工，來製作具有晶片銲墊部與導線部的框素材；在以遮罩材覆蓋上述晶片銲墊部及上述導線部之下面，和上述導線部之上面的與樹脂密封用模具接觸的部分之狀態下，將上述晶片銲墊部及導線部之上面及側壁面，使用以過氧化氫與硫酸作為成份的微蝕刻液來加以粗面化；剝除上述遮罩材之後，於上述框素材的表面層積鍍層。
  20. 一種半導體裝置，其特徵為：包含：由壓展銅板或壓展銅合金板所構成的電路構件，該電路構件係包含：晶片銲墊部與導線部、形成在上述晶片銲墊部及上述導線部之上面及側壁面的粗面、形成在上述晶片銲墊部及上述導線部之下面的平滑面、及上述表面的鍍層；裝載於上述晶片銲墊部上面的半導體晶片；連接上述半導體晶片與上述導線部的銲線；及以使上述導線部之下面露出之方式，來密封上述電路構件、上述半導體晶片及上述銲線的電性絕緣性之密封樹脂；上述導線部之上面的與樹脂密封用模具接觸之部分為平滑面。
TW095114961A 2005-04-26 2006-04-26 Circuit member, manufacturing method of circuit member, laminated structure of semiconductor device and circuit member surface TWI429045B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005128259A JP4857594B2 (ja) 2005-04-26 2005-04-26 回路部材、及び回路部材の製造方法

Publications (2)

Publication Number Publication Date
TW200731494A TW200731494A (en) 2007-08-16
TWI429045B true TWI429045B (zh) 2014-03-01

Family

ID=37214880

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095114961A TWI429045B (zh) 2005-04-26 2006-04-26 Circuit member, manufacturing method of circuit member, laminated structure of semiconductor device and circuit member surface

Country Status (9)

Country Link
US (2) US8742554B2 (zh)
JP (1) JP4857594B2 (zh)
KR (1) KR100928474B1 (zh)
CN (1) CN100576525C (zh)
DE (1) DE112006001048B4 (zh)
MY (1) MY142623A (zh)
SG (3) SG2014010920A (zh)
TW (1) TWI429045B (zh)
WO (1) WO2006115267A1 (zh)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4978294B2 (ja) * 2007-04-20 2012-07-18 株式会社デンソー 半導体装置およびその製造方法
US8981548B2 (en) 2007-05-25 2015-03-17 Stats Chippac Ltd. Integrated circuit package system with relief
US8030742B2 (en) * 2007-11-30 2011-10-04 Infineon Technologies Electronic device having profiled elements extending from planar surfaces
US8240036B2 (en) 2008-04-30 2012-08-14 Panasonic Corporation Method of producing a circuit board
US20090315159A1 (en) * 2008-06-20 2009-12-24 Donald Charles Abbott Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same
JP2010010634A (ja) * 2008-06-30 2010-01-14 Shinko Electric Ind Co Ltd リードフレーム及び半導体装置の製造方法
JP5217800B2 (ja) 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
KR101241735B1 (ko) 2008-09-05 2013-03-08 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
US8603864B2 (en) * 2008-09-11 2013-12-10 Infineon Technologies Ag Method of fabricating a semiconductor device
JP4670931B2 (ja) * 2008-09-29 2011-04-13 住友金属鉱山株式会社 リードフレーム
US8106502B2 (en) * 2008-11-17 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with plated pad and method of manufacture thereof
KR101555300B1 (ko) * 2008-12-05 2015-09-24 페어차일드코리아반도체 주식회사 외부 본딩 영역을 구비하는 반도체 파워 모듈 패키지
US10431567B2 (en) 2010-11-03 2019-10-01 Cree, Inc. White ceramic LED package
KR20100103015A (ko) 2009-03-12 2010-09-27 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
JP2010245417A (ja) 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体装置およびその製造方法
JP4892033B2 (ja) * 2009-05-13 2012-03-07 日立ケーブルプレシジョン株式会社 リードフレームの製造方法
KR101113891B1 (ko) 2009-10-01 2012-02-29 삼성테크윈 주식회사 리드 프레임 및 리드 프레임 제조 방법
US9332642B2 (en) 2009-10-30 2016-05-03 Panasonic Corporation Circuit board
EP2496061A4 (en) * 2009-10-30 2014-01-08 Panasonic Corp PRINTED CIRCUIT BOARD AND SEMICONDUCTOR DEVICE COMPRISING A COMPONENT MOUNTED ON A PRINTED CIRCUIT BOARD
EP2400534A1 (en) * 2010-06-22 2011-12-28 Nxp B.V. Packaged semiconductor device having improved locking properties
KR101128999B1 (ko) * 2010-07-08 2012-03-23 엘지이노텍 주식회사 칩 패키지 제조 방법 및 이에 의해 제조된 칩 패키지
US9831393B2 (en) 2010-07-30 2017-11-28 Cree Hong Kong Limited Water resistant surface mount device package
JPWO2012036281A1 (ja) 2010-09-17 2014-02-03 ローム株式会社 半導体発光装置、その製造方法、および表示装置
US8836107B2 (en) * 2011-02-24 2014-09-16 Texas Instruments Incorporated High pin count, small SON/QFN packages having heat-dissipating pad
JP2012212867A (ja) * 2011-03-30 2012-11-01 Ibiden Co Ltd プリント配線板及びその製造方法
KR20130007022A (ko) * 2011-06-28 2013-01-18 삼성전기주식회사 인쇄회로기판 및 이의 제조방법
KR101310256B1 (ko) 2011-06-28 2013-09-23 삼성전기주식회사 인쇄회로기판의 무전해 표면처리 도금층 및 이의 제조방법
TWI455269B (zh) * 2011-07-20 2014-10-01 Chipmos Technologies Inc 晶片封裝結構及其製作方法
JP2013023766A (ja) * 2011-07-26 2013-02-04 Hitachi Chemical Co Ltd テープキャリア付半導体実装用導電基材の表面処理方法、ならびにこの処理方法を用いてなるテープキャリア付半導体実装用導電基材および半導体パッケージ
US20130098659A1 (en) * 2011-10-25 2013-04-25 Yiu Fai KWAN Pre-plated lead frame for copper wire bonding
KR101372205B1 (ko) * 2011-12-15 2014-03-10 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
CN102543910A (zh) * 2012-02-06 2012-07-04 三星半导体(中国)研究开发有限公司 芯片封装件及其制造方法
GB2500604A (en) * 2012-03-26 2013-10-02 Leclanche Sa Battery Cell electrical connections
WO2013145532A1 (ja) * 2012-03-28 2013-10-03 パナソニック株式会社 樹脂パッケージ
US8587099B1 (en) * 2012-05-02 2013-11-19 Texas Instruments Incorporated Leadframe having selective planishing
US8796049B2 (en) * 2012-07-30 2014-08-05 International Business Machines Corporation Underfill adhesion measurements at a microscopic scale
JP2013048280A (ja) * 2012-10-30 2013-03-07 Renesas Electronics Corp 半導体装置の製造方法
WO2014132483A1 (ja) * 2013-03-01 2014-09-04 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP5939185B2 (ja) * 2013-03-26 2016-06-22 トヨタ自動車株式会社 半導体装置及びその製造方法
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
JP5994720B2 (ja) * 2013-04-19 2016-09-21 株式会社デンソー 半導体装置、および半導体装置の製造方法
US9711489B2 (en) 2013-05-29 2017-07-18 Cree Huizhou Solid State Lighting Company Limited Multiple pixel surface mount device package
US9607940B2 (en) * 2013-07-05 2017-03-28 Renesas Electronics Corporation Semiconductor device
DE102013215246A1 (de) * 2013-08-02 2015-02-05 Robert Bosch Gmbh Elektronikmodul mit Leiterplatten und anspritzbarem Kunststoff-Dichtring, insbesondere für ein Kfz-Getriebesteuergerät, und Verfahren zum Fertigen desselben
JP6262968B2 (ja) * 2013-09-09 2018-01-17 Ｄｏｗａメタルテック株式会社 電子部品搭載基板およびその製造方法
TWI565100B (zh) * 2014-01-28 2017-01-01 Jun-Ming Lin An electronic component bracket with a roughened surface
JP6414669B2 (ja) * 2014-07-22 2018-10-31 大口マテリアル株式会社 リードフレーム及びその製造方法
JP6362111B2 (ja) * 2014-12-01 2018-07-25 大口マテリアル株式会社 リードフレームの製造方法
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
JP6065081B2 (ja) * 2015-10-01 2017-01-25 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
JP6650723B2 (ja) * 2015-10-16 2020-02-19 新光電気工業株式会社 リードフレーム及びその製造方法、半導体装置
JP6603538B2 (ja) * 2015-10-23 2019-11-06 新光電気工業株式会社 リードフレーム及びその製造方法
JP6608672B2 (ja) * 2015-10-30 2019-11-20 新光電気工業株式会社 半導体装置及びその製造方法、リードフレーム及びその製造方法
JP6576796B2 (ja) * 2015-11-05 2019-09-18 新光電気工業株式会社 リードフレーム及びその製造方法、半導体装置
JP6685112B2 (ja) * 2015-11-18 2020-04-22 株式会社三井ハイテック リードフレーム及びリードフレームパッケージ、並びにこれらの製造方法
DE102016015883B3 (de) 2016-03-21 2022-07-14 Infineon Technologies Ag Räumlich selektives Aufrauen von Verkapselungsmasse, um eine Haftung mit einer Funktionsstruktur zu fördern
JP2016165005A (ja) * 2016-04-19 2016-09-08 大日本印刷株式会社 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法
US20190164869A1 (en) * 2016-08-03 2019-05-30 Soliduv, Inc. Strain-Tolerant Die Attach with Improved Thermal Conductivity, and Method of Fabrication
DE102016117841A1 (de) * 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung
WO2018074035A1 (ja) 2016-10-18 2018-04-26 株式会社デンソー 電子装置及びその製造方法
JP6852358B2 (ja) * 2016-11-14 2021-03-31 大日本印刷株式会社 半導体装置用リードフレームとその製造方法および樹脂封止型半導体装置
JP6761738B2 (ja) * 2016-11-15 2020-09-30 新光電気工業株式会社 リードフレーム及びその製造方法、電子部品装置の製造方法
JP6857035B2 (ja) * 2017-01-12 2021-04-14 ローム株式会社 半導体装置
DE112017007098T5 (de) 2017-02-21 2019-11-21 Mitsubishi Electric Corporation Halbleitervorrichtung
CN106835084A (zh) * 2017-02-28 2017-06-13 西安微电子技术研究所 一种在半导体裸芯片上实现键合金属化改性的方法
TWI613768B (zh) * 2017-03-20 2018-02-01 矽品精密工業股份有限公司 電子封裝件及其製法
JP2017108191A (ja) * 2017-03-24 2017-06-15 ルネサスエレクトロニクス株式会社 半導体装置
US10074590B1 (en) * 2017-07-02 2018-09-11 Infineon Technologies Ag Molded package with chip carrier comprising brazed electrically conductive layers
US10211131B1 (en) * 2017-10-06 2019-02-19 Microchip Technology Incorporated Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device
JP2019083295A (ja) * 2017-10-31 2019-05-30 トヨタ自動車株式会社 半導体装置
IT201800005354A1 (it) 2018-05-14 2019-11-14 Dispositivo a semiconduttore e procedimento corrispondente
CN111341750B (zh) * 2018-12-19 2024-03-01 奥特斯奥地利科技与系统技术有限公司 包括有导电基部结构的部件承载件及制造方法
US10937744B2 (en) * 2019-02-22 2021-03-02 Infineon Technologies Ag Semiconductor packages including roughening features
JP6736716B1 (ja) 2019-03-22 2020-08-05 大口マテリアル株式会社 リードフレーム
JP6741356B1 (ja) * 2019-03-22 2020-08-19 大口マテリアル株式会社 リードフレーム
CN112133640B (zh) * 2020-11-24 2021-02-09 宁波康强电子股份有限公司 一种具有粗糙侧壁的引线框架的制备方法
US11715678B2 (en) * 2020-12-31 2023-08-01 Texas Instruments Incorporated Roughened conductive components
WO2022188071A1 (en) 2021-03-10 2022-09-15 Innoscience (suzhou) Semiconductor Co., Ltd. Iii-nitride-based semiconductor packaged structure and method for manufacturing thereof
US20240145356A1 (en) * 2021-09-03 2024-05-02 Dai Nippon Printing Co., Ltd. Lead frame and manufacturing method thereof
CN113782453B (zh) * 2021-11-12 2022-02-08 深圳中科四合科技有限公司 一种引线框架的制作方法
KR102563273B1 (ko) * 2021-12-31 2023-08-04 해성디에스 주식회사 반도체 패키지의 제조 방법
US20230268254A1 (en) * 2022-02-18 2023-08-24 Advanced Semiconductor Engineering, Inc. Electronic device with frame component
CN114845483A (zh) * 2022-03-31 2022-08-02 生益电子股份有限公司 埋设线路的pcb制作方法及埋设线路的pcb
WO2024157758A1 (ja) * 2023-01-25 2024-08-02 ローム株式会社 半導体装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3981691A (en) * 1974-07-01 1976-09-21 Minnesota Mining And Manufacturing Company Metal-clad dielectric sheeting having an improved bond between the metal and dielectric layers
US4786545A (en) * 1986-02-28 1988-11-22 Seiko Epson Corporation Circuit substrate and method for forming bumps on the circuit substrate
JPS6333853A (ja) * 1986-07-28 1988-02-13 Dainippon Printing Co Ltd 集積回路パツケ−ジ
US5114557A (en) * 1991-02-20 1992-05-19 Tooltek Engineering Corp. Selective plating apparatus with optical alignment sensor
JPH0846116A (ja) 1994-07-28 1996-02-16 Mitsubishi Denki Metetsukusu Kk リードフレーム及びその製造方法
US6163961A (en) * 1995-02-25 2000-12-26 Glacier Vandervell Limited Plain bearing with overlay
JPH09148509A (ja) 1995-11-22 1997-06-06 Goto Seisakusho:Kk 半導体装置用リードフレーム及びその表面処理方法
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
JPH1140720A (ja) 1997-07-16 1999-02-12 Dainippon Printing Co Ltd 回路部材および該回路部材を用いた樹脂封止型半導体装置
JPH1129883A (ja) * 1997-07-08 1999-02-02 Mec Kk 銅および銅合金のマイクロエッチング剤
US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP2000077594A (ja) 1998-09-03 2000-03-14 Hitachi Cable Ltd 半導体装置用リードフレーム
EP0987747A1 (en) * 1998-09-17 2000-03-22 STMicroelectronics S.r.l. Process for improving the adhesion between metal and plastic in containment structures for electronic semiconductor devices
KR100687548B1 (ko) * 1999-01-27 2007-02-27 신꼬오덴기 고교 가부시키가이샤 반도체 웨이퍼 제조 방법, 반도체 장치 제조 방법 및 칩 사이즈의 반도체 웨이퍼 패키지 제조 방법
CN1182197C (zh) * 2000-07-13 2004-12-29 日本特殊陶业株式会社 填充通孔的浆料及使用该浆料的印刷线路板
JP4033611B2 (ja) 2000-07-28 2008-01-16 メック株式会社 銅または銅合金のマイクロエッチング剤およびそれを用いるマイクロエッチング法
JP3930732B2 (ja) * 2000-12-27 2007-06-13 荏原ユージライト株式会社 銅および銅合金用のマイクロエッチング剤並びにこれを用いる銅または銅合金の微細粗化方法
JP3963655B2 (ja) * 2001-03-22 2007-08-22 三洋電機株式会社 回路装置の製造方法
JP2002299538A (ja) * 2001-03-30 2002-10-11 Dainippon Printing Co Ltd リードフレーム及びそれを用いた半導体パッケージ
JP2002309396A (ja) * 2001-04-11 2002-10-23 Dainippon Printing Co Ltd 製版めっき方法
CN1681373A (zh) * 2001-08-10 2005-10-12 日矿金属加工株式会社 层叠板用铜合金箔
DE10148120B4 (de) * 2001-09-28 2007-02-01 Infineon Technologies Ag Elektronische Bauteile mit Halbleiterchips und ein Systemträger mit Bauteilpositionen sowie Verfahren zur Herstellung eines Systemträgers
JP2003158234A (ja) * 2001-11-21 2003-05-30 Hitachi Ltd 半導体装置及びその製造方法
JP3618316B2 (ja) * 2001-11-21 2005-02-09 株式会社三井ハイテック 半導体装置の製造方法
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP3883543B2 (ja) * 2003-04-16 2007-02-21 新光電気工業株式会社 導体基材及び半導体装置
JP3841768B2 (ja) * 2003-05-22 2006-11-01 新光電気工業株式会社 パッケージ部品及び半導体パッケージ
US7049683B1 (en) * 2003-07-19 2006-05-23 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound

Also Published As

Publication number Publication date
KR100928474B1 (ko) 2009-11-25
WO2006115267A1 (ja) 2006-11-02
SG194400A1 (en) 2013-11-29
CN101164165A (zh) 2008-04-16
CN100576525C (zh) 2009-12-30
DE112006001048T5 (de) 2008-04-30
SG161245A1 (en) 2010-05-27
SG2014010920A (en) 2014-05-29
JP2006310397A (ja) 2006-11-09
DE112006001048B4 (de) 2012-08-30
US8742554B2 (en) 2014-06-03
KR20070119758A (ko) 2007-12-20
JP4857594B2 (ja) 2012-01-18
US8739401B2 (en) 2014-06-03
US20100325885A1 (en) 2010-12-30
MY142623A (en) 2010-12-15
US20090039486A1 (en) 2009-02-12
TW200731494A (en) 2007-08-16

Similar Documents

Publication Publication Date Title
TWI429045B (zh) Circuit member, manufacturing method of circuit member, laminated structure of semiconductor device and circuit member surface
US10431560B2 (en) Molded semiconductor package having an optical inspection feature
CN105185752B (zh) 半导体器件及其制造方法
JPWO2007061112A1 (ja) 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置
US20090315159A1 (en) Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same
JP6269887B2 (ja) 半導体装置の製造方法、およびリードフレームの製造方法
KR20200112658A (ko) 리드 프레임
JP4670931B2 (ja) リードフレーム
JP4892033B2 (ja) リードフレームの製造方法
JP5678980B2 (ja) 回路部材の製造方法
JP2024123171A (ja) リードフレーム及びその製造方法
CN114695303A (zh) 引线框架、引线框架的制造方法以及半导体装置
JP2014146827A (ja) 回路部材の表面積層構造
JP5353954B2 (ja) 回路部材、及び半導体装置
JP6191664B2 (ja) 半導体装置の多面付け体および半導体装置
JP6733941B1 (ja) 半導体素子搭載用基板
JP5299411B2 (ja) リードフレームの製造方法
KR20200112657A (ko) 리드 프레임
KR20200112656A (ko) 리드 프레임
TWI387080B (zh) 四方扁平無引腳之半導體封裝結構及封裝方法
JP2012028822A (ja) リードフレーム及び半導体装置