CN100461403C - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN100461403C
CN100461403C CNB200510076387XA CN200510076387A CN100461403C CN 100461403 C CN100461403 C CN 100461403C CN B200510076387X A CNB200510076387X A CN B200510076387XA CN 200510076387 A CN200510076387 A CN 200510076387A CN 100461403 C CN100461403 C CN 100461403C
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China
Prior art keywords
semiconductor element
frequency
support substrates
semiconductor device
hole
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Expired - Fee Related
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CNB200510076387XA
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English (en)
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CN1822364A (zh
Inventor
爱场喜孝
藤泽哲也
米田义之
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Socionext Inc
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Fujitsu Semiconductor Ltd
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Publication of CN1822364A publication Critical patent/CN1822364A/zh
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Abstract

本发明公开一种半导体器件，包括：支撑衬底；第一半导体元件，安装在该支撑衬底的一侧上；第二半导体元件，包括安装在该支撑衬底的所述一侧上的高频电极；通孔，设置在与该高频电极相关联的该支撑衬底上；以及外部连接电极，设置在与该通孔相关联的该支撑衬底的另一侧上。

Description

半导体器件
技术领域
本发明涉及一种半导体器件，在该半导体器件中，如存储元件和/或逻辑元件等半导体元件，以及用于处理高频信号的高频半导体元件被安装在共同的衬底上。
背景技术
近年来并在持续之中，对于半导体元件(例如移动电话等电子装置中的电子组件)的更高集成度存在不断增长的需求，以实现电子装置中的微型化以及技术改进。
响应这种需求，开发出这样的半导体器件，在公共的容器或者封装中容纳多个具有不同功能的半导体元件(例如存储元件和/或如微处理器的逻辑元件)。这种半导体器件被称为SiP(封装中的系统)。
并且，关于这些电子装置，为了与外部单元和/或装置通信，需要提高通信速度。因此，例如，用于处理0.1-10GHz频带内的高频信号的高频半导体元件可被设置在如上所述的容器或者封装内。
图1为显示安装衬底的结构图，该衬底容纳包括与存储元件和/或逻辑元件例如微处理器相对应的半导体元件的半导体器件，以及包括高频半导体元件的半导体器件。
在所示实例中，在底板(电子装置的主电子电路衬底)55的一侧上安装：第一半导体器件10，其包括例如相应于存储元件和/或逻辑元件的半导体元件21和25；以及第二半导体器件40，其包括高频半导体器件47。
第一半导体器件10包括支撑衬底11、安装在支撑衬底11一侧上的半导体元件21和25、以及在支撑衬底11另一侧上设置的外部连接端子31。
支撑衬底11相应于半导体元件安装衬底，其包括：通孔(被导电材料填充，但以下称为通孔)13，其穿过支撑衬底11的基材12；导线连接部分14和15，其被设置在通孔13的上端；以及连接焊盘16和17，其被设置在通孔13的下端。
半导体元件21被安装在支撑衬底11上，并且包括电极焊盘22，这些电极焊盘通过导线23电连接到支撑衬底11的导线连接部分14。
半导体元件25被安装在支撑衬底11上，并且包括电极焊盘26，这些电极焊盘通过导线28电连接到支撑衬底11的导线连接部分15。半导体元件21和15被树脂29沿着导线23和28密封。
连接焊盘16和17经由外部端子31电连接到在底板55上设置的焊盘57或者布线59，这些外部端子31形成为例如球状或者凸块。
注意在一个实例中，半导体21和25其中之一可以相应于逻辑元件例如微处理器，而半导体21和25的另一个可以相应于存储元件例如闪存。在这种情况下，逻辑元件和存储元件的相对位置(即哪个半导体元件被放置在另一个上)可以根据以下条件来确定：例如用于实现各半导体元件的功能和电路结构所需的芯片尺寸(面积)以及端子数量。
第二半导体器件40包括：支撑衬底41、在支撑衬底41一侧上安装的高频半导体元件47、以及在支撑衬底41另一侧上设置的外部连接端子53。
支撑衬底41相应于半导体元件安装衬底，其包括：通孔43，其穿过支撑衬底41的基材42；导线连接部分44，其被设置在通孔43的上端；以及连接焊盘45，其被设置在通孔43的下端。
高频半导体元件47(其相应于适于处理具有例如1GHz以上频率的高频模拟信号的半导体元件)被安装在支撑衬底41上，并且包括电极焊盘48，这些电极焊盘通过导线49电连接到支撑衬底41的导线连接部分44。
高频半导体元件47被树脂51沿着导线49密封。连接焊盘45经由外部连接端子53连接到在底板55上设置的焊盘58或者布线59，这些外部连接端子53形成为球状或者凸块。
在底板55一侧上设置的布线59实现第一半导体器件10和第二半导体器件40之间的电连接。例如，日本特开专利公开号2003-110084公开了一种涉及如上所述设置的技术。
为了实现例如移动电话等电子装置中的微型化以及技术改进，处理高频信号的半导体元件优选安装在如上所述与逻辑元件和/或存储元件共同的衬底上，而不是设置为分离的半导体器件。
但是，如同本领域的专业技术人员所熟知的，高频半导体元件易于受位于该高频半导体元件附近的其他布线和半导体元件的电磁场影响。
例如，在图1的实例中，如果半导体元件21和25以及高频半导体元件47被安装在作为共同支撑衬底(插入器)的底板55上，并且被密封在一起(被封装)，则在通过连接到高频半导体元件47的布线/导线传输的信号和通过连接到半导体元件21或25的布线/导线传输的信号之间会产生干扰，并且不能获得所需的电特性。
因此，在现有技术中，如图1所示，半导体元件21和25以及高频半导体元件47分别作为分离的半导体器件10和40被安装在底板55上。
但是，当多于一个被密封(被封装)的半导体器件被如上所述安装在一个共同的支撑衬底上时，则支撑衬底的封装密度会下降，而这是电子装置微型化的障碍。
此外，当除了相应于高频半导体元件的半导体器件之外的多个半导体器件被分离地形成在支撑衬底上，并且对于每个半导体器件试图获得所需的电特性时，则支撑衬底设计可能很复杂，并且电子装置的制造成本会增加。
此外，在上述结构中，连接高频半导体器件与另一半导体器件(例如图1的布线59)的布线长度会很长，从而在传输高频信号时会产生较大传输损耗。
发明内容
本发明针对相关现有技术的一个或更多问题而被构思出来，并且本发明的目的为提供具有提高的封装密度的半导体器件，该半导体器件能够防止高频信号的传输损耗并实现电子装置中的微型化以及技术改进。
在本发明的一个方案中，第一半导体元件和第二半导体元件被安装在共同的支撑衬底上，从而可以增加半导体器件的封装密度。此外，高频电极被设置在支撑衬底一侧上相应于通孔位置的位置处，并且外部连接电极被设置在支撑衬底另一侧上相应于通孔位置的位置处，从而可以减少高频电极和外部连接电极之间的信号传输路径长度，并防止高频信号的传输损耗。此外该第二半导体元件包括耦合至该高频电极并面向该支撑衬底的重布线。
在本发明的优选实施例中，第二半导体元件被正面向下安装在支撑衬底的一侧上。在本实施例的一个方案中，高频电极可以连接到支撑衬底。
在本发明的另一优选实施例中，高频电极的中心轴位于通孔的外围中。在本发明的一个方案中，这样设置高频电极，以使得其中心轴位于通孔的外围中，从而可以准确地进行高频电极和外部连接电极之间的高频信号传输。
在本发明的另一优选实施例中，第一半导体元件被堆叠在第二半导体元件上。在本实施例的一个方案中，第一半导体元件被堆叠在第二半导体元件的顶部，从而在防止被传输的高频信号的传输损耗的同时，可以减小支撑衬底的尺寸，并实现半导体器件的微型化。
在本发明的另一优选实施例中，第二半导体元件包括被设置为地电势的防护部件。在实施例的一个方案中，被设置为地电势的防护部件被设置在第二半导体元件上，从而可以防止第二半导体元件受到来自第一半导体元件的噪声影响。
在本发明的另一优选实施例中，第二半导体元件包括形成无源元件的重布线(rewiring)。在本实施例的一个方案中，通过使用重布线形成无源元件，无源元件不必分离形成，从而可以减少第二半导体元件中所需的组件数和安装空间。此外，可以降低阻抗，从而可以提高第二半导体元件的电特性。
在本发明的另一优选实施例中，第二半导体元件包括一对重布线结构，其包括相互平行的部分。在本实施例的一个方案中，通过提供具有相互平行部分的一对重布线结构，可以消除布线中的串扰，从而可以减少噪声。
在本发明的另一优选实施例中，第二半导体元件包括具有基本相等布线长度的一组重布线结构。在本实施例的一个方案中，通过设置具有基本相等布线长度的一组重布线结构，可以进行不定时(skew timing)的调整和优化。
附图说明
图1为显示根据现有技术容纳多个半导体器件的安装衬底的结构剖面图；
图2为显示根据本发明第一实施例的半导体器件结构的剖面图；
图3为显示图2的半导体器件被安装在安装衬底上的状态的剖面图；
图4为从底侧观看的图2的半导体器件的平面图；
图5为显示在图2的半导体器件中设置的高频半导体元件结构的剖面图；
图6为说明在半导体元件中设置的重布线的示范性排列图；
图7为说明在用于高频半导体元件的外部连接端子的安装节距与用于支撑衬底的外部连接端子的安装节距相等的情况下高频半导体元件的高频外部连接端子的连接图；
图8为说明在用于高频半导体元件的外部连接端子的安装节距为用于支撑衬底的外部连接端子的安装节距的一半(1/2)的情况下，高频半导体元件的高频外部连接端子的连接图；
图9为说明在用于高频半导体元件的外部连接端子的安装节距为用于支撑衬底的外部连接端子的安装节距的k倍(0<k<1)的情况下，高频半导体元件的高频外部连接端子的连接图；
图10为显示不包括导体柱(post)的高频半导体元件结构的剖面图；
图11为显示根据本发明第二实施例的半导体器件结构的剖面图；
图12为显示根据本发明第三实施例的半导体器件结构的剖面图；
图13为显示根据该第三实施例的高频半导体元件结构的剖面图；
图14为显示不包括导体柱的高频半导体元件结构的剖面图；
图15为显示根据本发明第四实施例的半导体器件结构的剖面图；
图16为从底侧观看的图15的半导体器件的平面图；以及
图17为显示根据本发明第五实施例的半导体器件结构的剖面图。
具体实施方式
在下文中，将参照附图描述本发明的优选实施例。
(第一实施例)
首先，参照图2-4，描述根据本发明第一实施例的半导体器件70。
图2为显示根据第一实施例的半导体器件70结构的剖面图；而图3为显示半导体器件70被安装在安装衬底上的状态的剖面图。
图4为从由图2的箭头A表示的方向观看的半导体器件70的底平面图。
注意在图2中，所示的区域B相应于上绝缘膜76上安装半导体元件101的区域(以下称为“芯片安装区域B”)。
根据本实施例，半导体器件70包括：支撑衬底71、外部连接端子97和98、相应于第一半导体元件的半导体元件101和105、以及相应于第二半导体元件的高频半导体元件110。半导体元件101和105以及高频半导体元件110被安装在共同的支撑衬底71上，并且被模制树脂122整体密封。
模制树脂122被设置为保护半导体元件101、105和110以及它们的连接导线。在本实施例中，半导体元件101通过所谓的正面向上(face-up)安装方法经由接合(bonding)层104被安装在支撑衬底71上，并且半导体元件105通过正面向上安装经由接合层109被安装在半导体元件101上。
相应于第二半导体元件的高频半导体元件110通过所谓的正面向下(倒装法)安装方法被安装在支撑衬底71上。在这种情况下，半导体元件110的高频外部连接端子121被连接到连接焊盘87，该连接焊盘被设置在穿过支撑衬底71的通孔81的顶端处。
注意在本实施例中，半导体元件101被设置为在尺寸上大于半导体元件105。半导体元件101和105可以相应于存储元件或逻辑元件(例如微处理器)，其可根据需要或要求进行组合。由于芯片尺寸和外部连接端子的数量/排列可根据在每个电子装置中需要的半导体元件的功能和容量而改变，存储元件和逻辑元件的相对位置可以根据每个特定电子装置来确定(即根据每个特定的电子装置，就存储元件或者逻辑元件中的哪一个被放置在另一个上进行确定)。
高频半导体元件110相应于处理高频信号例如高频模拟信号的半导体元件。
支撑衬底71包括穿过支撑衬底71的基材72的多个通孔73。在支撑衬底71的上表面(即半导体安装表面)上，设置有电连接到通孔73的上布线75、覆盖上布线75的上绝缘层76、以及穿过上绝缘层76的上通孔78。在上绝缘层76上，设置电连接到上通孔78的导线连接部分83和84。
在支撑衬底71的下表面(即外部连接端子安装表面)上，设置电连接到通孔73的下布线88、覆盖下布线88的下绝缘层89、以及穿过下绝缘层89的下通孔91。在下绝缘层89上，设置电连接到下通孔91的连接焊盘93。此外，在下绝缘层89的底表面区域上相应于没有设置连接焊盘93的区域设置抗焊层96。
此外，在本实施例中设置通孔81，该通孔穿过上绝缘膜76、基材72、以及下绝缘膜89的分层结构。通孔81被设置为实现与高频半导体元件110的高频外部连接端子121的连接。
根据本实施例，基材72相应于由树脂或者陶瓷材料制成的绝缘片/板。
上布线75被设置在基材72的上表面72A上，以被连接到通孔73，并且由树脂层制成的上绝缘层76被设置为覆盖上布线75。
上通孔78在一端连接到上布线75，而在另一端连接到导线连接部分83、84，布线85，或者连接焊盘86。
通孔81被设置在相应于高频半导体元件110的高频外部连接端子121的位置的位置。
在支撑衬底71的一侧(上侧)，导线连接部分83和84被设置在上绝缘层76上，以被电连接到通孔78。导线连接部分83经由导线103被连接到半导体元件101的电极焊盘102。导线连接部分84经由导线108被连接到半导体元件105的电极焊盘106。
布线85被设置在上绝缘层76上，以被电连接到相应的通孔78。高频半导体元件110的外部连接端子120被连接到布线85，其中该高频半导体元件被设置为处理除了高频信号之外的信号。此外，半导体元件105的电极焊盘106经由导线108被连接到布线85，从而可以实现半导体元件105和高频半导体元件110之间的电连接。
连接焊盘86被设置在上绝缘层76上、正面向下(倒装法)安装有高频半导体元件110的元件安装表面的部分处。连接焊盘86被连接到高频半导体元件110的外部连接端子120，该高频半导体元件被设置为处理除了高频信号之外的信号，并且在一侧连接到连接焊盘86。此外，连接焊盘86在另一侧被连接到通孔78。
连接焊盘87被设置在上绝缘层76上，以在一侧连接到通孔81的一端81A，而在另一端直接连接到正面向下(倒装法)安装的高频半导体元件110的高频外部连接端子121。
在支撑衬底71的另一侧(下侧)，设置电连接到通孔73的下布线88和由树脂制成且覆盖下布线88的下绝缘层89。在下绝缘层89的底表面上设置的连接焊盘93通过下通孔91被电连接到下布线88。
此外，注意连接焊盘95被设置在通孔81的底端。
在连接焊盘93和95的底表面上，设置相应于焊接凸块的外部连接端子97和98。
覆盖下绝缘层89的底表面区域的抗焊层96被设置在连接焊盘93和95周围，以防止外部连接端子97和98相互接触。
如图3所示，具有如上述结构的半导体器件70经由外部连接端子97和98被电连接到设置在安装衬底125上的电极焊盘/布线127。以这种方式，可以在半导体元件101、105、高频半导体元件110和安装衬底125之间实现包括高频信号在内的信号传输。
在根据本实施例的半导体器件70中，半导体元件101、105和高频半导体元件110被安装在一个共同的支撑衬底71上，由此，可以减小布线85的长度，从而可以减小在半导体元件105和高频半导体元件110之间传输的高频信号的传输损耗。
此外，根据本实施例，高频半导体元件110的高频外部连接端子121被连接到连接焊盘87，连接焊盘95通过通孔81被连接到连接焊盘87，并且在连接焊盘95上设置的外部连接端子98被连接到安装衬底125的电极焊盘/布线127。以这种方式，可以在高频半导体元件110和安装衬底125之间实现高频信号传输(需要高速传输的信号的传输)。
如图4所示，根据本实施例，在半导体器件70的支撑衬底71的下侧，外部连接端子97和98被排列成矩阵，并且四个适于处理高频信号的外部连接端子98被设置在外部连接端子排列的最外面的位置处，从而使得外部连接端子98可以容易地连接到外部电路或者装置。
注意外部连接端子97和98排列中的安装节距基于标准化规格被设置为预定值。
在下文中，参照图5描述高频半导体元件110的结构。
图5为显示高频半导体元件110被如上所述正面向下(倒装法)安装在支撑衬底71上的状态的剖面图。
如本图中所示，例如，高频半导体元件110包括高频元件111、重布线115、116、柱状电极(导体柱)118、模制树脂119、外部连接端子120、以及高频外部连接端子121。
高频元件111相应于硅(Si)半导体元件，例如，该硅半导体元件包括实现适于处理高频模拟信号的电子电路的功能元件。高频元件111包括：电极焊盘112和113，所述焊盘通过传统晶片工艺形成在硅衬底的一侧；以及绝缘层114，覆盖硅衬底并露出电极焊盘112和113。注意实现电子电路的功能元件例如晶体管和电阻器在本图中没有示出。
电极焊盘112相应于用于传输高频信号的电极焊盘。另一方面，例如，电极焊盘113相应于连接到电源线、地线的电极焊盘或者用于处理较低频率信号的布线。
绝缘层114相应于所谓的钝化层，并且例如可由氮化硅(SiN)制成。
重布线115沿绝缘层114延伸，并且在一端被连接到电极焊盘112。在另一端，重布线115经由柱状电极(导体柱)118被电连接到高频外部连接端子121。
重布线116沿绝缘层114延伸，并且在一端被连接到电极焊盘113。在另一端，重布线116被电连接到高频外部连接端子120。
根据本实施例，重布线115和116由铜(Cu)制成，并且被设置为实现高频外部连接端子121或者外部连接端子120的安装位置的调整以及外围电路元件的优化(阻抗匹配)。
图6为显示半导体元件中的重布线的示范性排列图。
注意图6中所示的半导体元件的结构不必一定对应于图5中所示的高频半导体元件110的结构。但是，图6中所示与图5中所示相同的组件被赋予相同的标号。
在图6的示范性实例中，重布线124A、124B及124C具有基本相同的布线长度并且构成一组重布线。
重布线124A、124B及124C在一侧连接到相邻的电极焊盘113，并且在另一侧经由导体柱(未示出)电连接到外部连接端子120。注意重布线124B被设置为沿绕行路径延伸，而不采取最短路径，从而使得重布线124B可具有与重布线124A和124C基本相同的布线长度。
通过设置用以连接到具有基本相同布线长度的重布线124A、124B及124C的相邻的电极焊盘113，可以实现不定时调整和优化。
此外，在图6中，重布线125A和125B构成一对重布线，其包括彼此平行的部分。
重布线125A和125B一侧被连接到电极焊盘113，这些电极焊盘113被连接到电子电路的差动电路单元，并且重布线125A和125B在另一侧经由导体柱(未示出)被电连接到外部连接端子120。通过设置连接到差动电路单元的一对重布线中的至少一部分为相互平行，可以降低噪声。
此外，在图6中，重布线126被螺旋设置为围绕电极焊盘112并实现一个电感，该电感对应于无源元件。
重布线126一侧被连接到电极焊盘112，在另一侧经由导体柱(未示出)被电连接到高频外部连接端子121。
通过采用重布线126来实现电感，无源元件例如电感就不必分离设置，并且可以降低组件数量和安装面积。
此外，通过将无源元件设置为靠近半导体元件的电极，可以降低阻抗并改进电特性。
注意在图5的高频半导体元件110中，重布线115、116及外部连接端子120、121通过柱状电极118相互电连接及机械连接，这些柱状电极118被设置在重布线115和116上。
通过如上所述在重布线115和116上设置柱状电极118，重布线115和116被模制树脂119密封。模制树脂119可被设置为保护重布线115、116以及柱状电极118(例如其可由铜(Cu)制成)。
外部连接端子120和121可相应于例如由无铅焊料制成的凸块。
重新参考图2和图3，根据本实施例，当高频半导体元件110被正面向下(倒装)安装在支撑衬底71上时，则高频外部连接端子121被连接到连接焊盘87，该连接焊盘被设置在穿过支撑衬底71的通孔81的一端81A。
以这种方式，高频半导体元件110的高频外部连接端子121可经由连接焊盘87、通孔81及连接焊盘95被电连接到外部连接端子98。
在这种设置中，用于实现高频外部连接端子121和外部连接端子98之间经由通孔81的电连接的连接距离可以减小，从而使得传输高频信号中的传输损耗可以降低。
此外，由于高频外部连接端子121和连接焊盘87都没有被设置为沿着支撑衬底71延伸，因此可以降低半导体元件101和半导体元件105之间相互干扰的出现。
注意外部连接端子120和高频外部连接端子121排列中的安装节距基于标准化规格被设置为预定值。
在下文中，参照图7-9描述高频外部连接端子121和连接焊盘87之间的连接。
首先，参考图7，描述在用于高频半导体元件110的外部连接端子120和121的安装节距P1与用于支撑衬底71上的外部连接端子97和98的安装节距P2相等(即P1＝P2)的情况下，高频外部连接端子121和连接焊盘87之间的连接。
注意在图7中，高频外部连接端子121的中心轴由C表示(以下称为“中心轴C”)，通孔81的外围由E表示(以下称为“外围E”)，用于高频半导体元件110的外部连接端子120和121的安装节距由P1表示(以下称为“安装节距P1”)，用于支撑衬底71上设置的外部连接端子97和98的安装节距由P2表示(以下称为“安装节距P2”)，以及通孔81的直径由R1表示(以下称为“直径R1”)。
如图7所示，当P1＝P2时，则高频半导体元件110的高频外部连接端子121经由连接焊盘87以这种方式设置在相应于通孔81的端部81A位置的位置处：使得通孔的中心轴基本与高频外部连接端子121的中心轴一致。然后，以这种方式放置的高频外部连接端子121被连接到连接焊盘87。
注意在高频外部连接端子121与连接焊盘87的连接中，高频外部连接端子121的中心轴C优选被设置为位于通孔81的外围E的内侧。
接下来，参考图8和图9，描述在用于高频半导体元件110的外部连接端子120和121的安装节距P1与用于支撑衬底71上的外部连接端子97和98的安装节距P2不同的情况下，高频外部连接端子121和连接焊盘87之间的示范性连接。
图8说明在用于高频半导体元件110的外部连接端子120和121的安装节距P1为用于在支撑衬底71上设置的外部连接端子97和98的安装节距P2的一半(1/2)的情况下，高频外部连接端子121的连接。图9说明在用于高频半导体元件110的外部连接端子120和121的安装节距P1为用于在支撑衬底71上设置的外部连接端子97和98的安装节距P2的k倍(0<k<1)的情况下，高频外部连接端子121的连接。
注意在图8和图9中，与图7所示相同的组件被赋予相同的标号。在图8中，外部连接端子120的中心轴由C’表示。在图9中，通孔81的直径由“R2”表示(以下称为“直径R2”)，以及通孔81的外围由F表示(以下称为“外围F”)。
如图8所示，当P1＝(P2/2)时，外部连接端子120被设置在两个高频外部连接端子121之间，从而使得高频外部连接端子121之间的距离被设置为P1×2＝P2，以及高频外部连接端子121可经由连接焊盘87被设置在相应于通孔81的端部81A位置的位置处。
注意在高频外部连接端子121与连接焊盘87的连接中，高频外部连接端子121的中心轴C优选设置为位于通孔81的外围E的内侧。
如图9所示，当P1＝k×P2(0<k<1)时，并且当通孔81的直径被设置为R1时高频外部连接端子121不能在相应于通孔81的端部81A位置的位置处被连接，则通孔81的直径被加宽为R2(R2>R1)，以使得高频外部连接端子121被设置在相应于通孔81的端部81A位置的位置处。以这种方式放置的高频外部连接端子121被连接到连接焊盘87，该连接焊盘87被设置在通孔81的端部81A上。
通过加宽在支撑衬底71上设置的通孔81的直径，高频外部连接端子121可以被放置为面向通孔81的端部81A，而不必改变用于高频半导体元件110的外部连接端子120和121的安装节距P1。
以这种方式，可以实现高频外部连接端子121和外部连接端子98之间的高频信号准确传输，而不会引起高频半导体元件110的高频特性退化。
注意在高频外部连接端子121与连接焊盘87的连接中，高频外部连接端子121的中心轴C优选被设置为位于通孔81的外围F的内侧。
通过以这种方式连接高频外部连接端子121与连接焊盘87：使得高频外部连接端子121的中心轴C被放置在通孔81的外围E/F的内侧(如上所述)，可以降低在高频外部连接端子121和外部连接端子98之间传输的高频信号的传输损耗。
图10为不包括柱状电极(导体柱)的高频半导体元件130的结构图。注意在这幅图中，与图5相同的组件被赋予相同的标号。
在图10的高频半导体元件130中，外部连接端子120和121被直接设置在重布线115和116上，而没有设置柱状电极(导体柱)。在本实例中，例如由有机绝缘树脂制成的树脂131被设置，以覆盖绝缘层114。
如上所述，根据一个实施例，不包括柱状电极的半导体元件被用作高频半导体元件。
注意在图6中所示的重布线结构例如重布线124A、124B、124C、125A、125B及126根据需要或要求可以设置在高频半导体元件130中。
在下文中，描述用于制造半导体器件70的工艺步骤。
首先，根据采用半导体元件70的电子装置所需的功能来选择适当类型的半导体元件作为半导体元件101、105及高频半导体元件110。例如，可从存储元件和/或逻辑元件例如微处理器选择适当的半导体元件作为半导体元件101和105，以及具有处理模拟信号功能的半导体元件可被选作高频半导体元件110。
此外，根据电子装置的结构以及半导体元件的端子结构/排列形成支撑衬底71。注意，此时，通孔81形成在支撑衬底71上相应于高频半导体元件110的高频外部连接端子121的安装位置的位置处。
然后，在支撑衬底71的一侧(上表面)上，安装半导体元件101、105和高频半导体元件110。
半导体元件101通过正面向上安装经由接合层104被接合到支撑衬底71上，并且半导体元件105通过正面向上安装经由接合层109被接合到半导体元件101上。
高频半导体元件110通过正面向下(倒装)安装被安装在支撑衬底71上。此时，高频外部连接端子121被设置在相应于通孔81位置的位置处，并且被连接到相应的连接焊盘87。
半导体元件101和105的电极焊盘经由相应的导线103和108被电连接到在支撑衬底71的上表面上设置的电极焊盘。
然后，半导体元件101、105及高频半导体元件110被模制树脂122沿着导线103和108密封。
然后，外部连接端子97和98被设置在支撑衬底71的另一侧(下表面)上形成的连接焊盘93。
通过根据如上所述的制造方法制造半导体器件70，相比传统方法可使半导体元件在支撑衬底上的高密度封装变得容易，并且考虑到设计和制造半导体器件所需的时间以及制造成本可使高频半导体元件110的优化变得容易。
此外，可以减少在高频外延连接端子121和外部连接端子98之间传输的高频信号的传输损耗。
(第二实施例)
在下文中，参考图11描述根据本发明第二实施例的半导体器件135。注意根据本实施例的半导体器件135的特征在于实施一防护部件用以覆盖高频半导体元件。
在图11中，半导体器件135与第一实施例的半导体器件70相同的组件被赋予相同的标号。
如图11所示，半导体器件135包括支撑衬底71、外部连接端子97、98、半导体元件101、105、高频半导体元件110、以及覆盖高频半导体元件110的防护部件136。
半导体元件101、105和覆盖高频半导体元件110的防护部件136被模制树脂122沿着导线103和108覆盖。
在本实例中，覆盖高频半导体元件110的防护部件136被电连接到在支撑衬底71上设置的接地端子(未示出)。
注意例如铝(Al)或者镍黄铜(铜[Cu]-镍[Ni]-锌[Zn]合金)可用作防护部件136的材料。
通过设置覆盖高频半导体元件110的防护部件136，可以减少或者防止半导体元件101、105和高频半导体元件110之间的相互干扰。
(第三实施例)
在下文中，参考图12和13描述根据本发明第三实施例的半导体器件140。
图12为根据本实施例的半导体器件140结构的剖面图。图13为图12的半导体器件140的高频半导体元件145结构的放大剖面图。注意根据本实施例的半导体器件140的特征在于包括电容器元件，该电容器元件被安装在高频半导体元件145的重布线形成表面上。
注意在图12和图13中，与根据第一和第二实施例的半导体器件相同的组件被赋予相同的标号。
参考图12，根据本实施例的半导体器件140包括：支撑衬底71、外部连接端子97、98、半导体元件101、105、高频半导体元件145、以及模制树脂122，该模制树脂被设置在支撑衬底71的一侧上，以覆盖半导体元件101、105以及高频半导体元件145。
参考图13，高频半导体元件145包括：高频元件111，其在一侧上形成有绝缘层114；重布线115和116，其设置在绝缘层114上；柱状电极(导体柱)151-153，其被设置在重布线115、116上；以及外部连接端子120、121，其被设置在柱状电极151-153的顶部。此外，高频半导体元件145包括电容器元件146，该电容器元件包括在重布线116上形成的介电层147以及在介电层147上形成的重布线层148。
重布线115、116、电容器元件146、以及柱状电极151-153被模制树脂119覆盖。
注意重布线115和116根据需要或者要求可以包括图6所述的重布线124A、124B、124C、125A、125B、及/或126。
例如，通过在高频半导体元件145上设置电容器元件146，实现电感和电容器元件146的重布线126可被组合，以相对容易地形成滤波器，从而提高高频半导体元件145的高频特性。
注意柱状电极(导体柱)151一端被连接到高频元件111的重布线115，而另一端151A从模制树脂119露出，并且外部连接端子121被设置在这个端部151A。
柱状电极152一端被连接到重布线116，而另一端152A从模制树脂119露出，并且外部连接端子120被设置在这个端部152A。
柱状电极153一端被连接到重布线148，而另一端153A从模制树脂119露出，并且外部连接端子120被设置在这个端部153A。注意柱状电极151-153的端部151A-153A被设置为位于基本相同的平面。
通过在重布线115、116及148上设置柱状电极151-153，重布线115和电容器元件146可被模制树脂119密封，该模制树脂例如可以通过压模来成型。注意柱状电极151-153例如可以由铜(Cu)制成。
图14为显示相应于图13的高频半导体元件145的修改实例的高频半导体元件155的结构图。
注意根据本实例的高频半导体元件155不包括柱状电极(导体柱)。在图14中，与图13所示相同的组件被赋予相同的标号。
图14的高频半导体元件155包括：半导体元件111，其一侧上形成有绝缘层114；重布线115和116，其设置在绝缘层114；通孔156，其设置在重布线115和116；以及外部连接端子，其设置在通孔156的一侧。
此外，高频半导体元件155包括电容器元件146，该电容器元件146通过在重布线115和116上设置的介电层147以及在介电层147上设置的重布线层148来实现。在本实例中，外部连接端子120被直接设置在实现电容器元件146的一个电极的重布线层148上。
重布线115、116、电容器元件146、以及通孔156被模制树脂157覆盖，以及绝缘层158例如抗焊层被设置在模制树脂157的表面上，以保护重布线148的表面部分。
注意重布线115和116根据需要或者要求可以包括重布线124A、124B、124C、125A、125B和/或126。
根据一个实施例，如上所述的高频半导体元件155可以替换高频半导体元件145而被用于半导体器件140中，以实现本发明的一种或更多的效果和优点。
(第四实施例)
在下文中，参考图15和16描述根据本发明第四实施例的半导体器件160。
图15是根据本实施例的半导体器件160的结构剖面图。图16为从底侧(从图15中的箭头G表示的方向)观看的半导体器件160的支撑衬底71的平面图。
根据本实施例的半导体器件160的特征在于包括高频半导体元件的多个半导体元件被设置成分层(堆叠)结构，以被安装在支撑衬底71的一侧上。
注意在图15和16中，与前述实施例的半导体器件相同的组件被赋予相同的标号。
在本实例中，半导体器件160的支撑衬底71包括基材72、以及穿过基材72的多个通孔73。基材72相应于半导体元件安装表面的一侧(上表面)上，设置有：上布线75，其电连接到通孔73；上绝缘层77，其覆盖上布线75；以及上通孔78，其穿过上绝缘层76。此外，在上绝缘层76上设置电连接到通孔78的导线连接部分83、84以及布线85、86。
在基材72相应于外部连接端子安装表面的另一侧(下表面)上，设置有：下布线88，其电连接到通孔73；下绝缘层89，覆盖下布线88；下通孔91，其穿过下绝缘层89；以及连接焊盘，其电连接到下通孔91。此外，在下绝缘层89上设置抗焊层96，该抗焊层被设置为围绕连接焊盘93。
并且，在相应于高频半导体元件110的安装位置的位置处，设置有：通孔81，其穿过包括基材72的分层结构；上绝缘层76；以及下绝缘层89。
根据本实施例，高频半导体元件110被正面向下安装在支撑衬底71的一侧(上表面)上其中心部分周围处，并且外部连接端子120和121被直接连接到布线85和连接焊盘87。
此外，半导体元件101经由接合层104被安装在高频半导体元件110的上表面上，并且半导体元件105经由接合层109被安装在半导体元件101的上表面上。以这种方式，多个半导体元件110、101和105被设置成分层(堆叠)结构，以被安装在支撑衬底71上。
注意通过在将高频外部连接端子121连接到相应的连接焊盘87时，设置高频外部连接端子121的中心轴位于通孔81的直径(外围)或者由通孔81占据的区域内，可以减少传输高频信号的传输路径长度，并且可以减少在高频外部连接端子121和外部连接端子98之间传输的高频信号的传输损耗。
此外，在本实例中，半导体元件101的电极焊盘102经由导线103被电连接到在支撑衬底上设置的导线连接部分83和布线85。半导体元件105的电极焊盘106经由导线108被电连接到在支撑衬底71上设置的导线连接部分84。
注意为了便于半导体元件101和105的导线连接，导线连接部分83和布线85被关于导线连接部分84向内放置。
在支撑衬底71的一侧上设置的半导体元件101、105和高频半导体元件110被模制树脂122沿着导线103和108密封。
通过在高频半导体元件110上堆叠半导体元件101和105，以及将堆叠的半导体元件安装在支撑衬底71上，可以减少支撑衬底71的尺寸，从而可以实现半导体器件160的微型化。
注意在一个实施例中，可使用图10的高频半导体元件130替代半导体器件160中的高频半导体元件110。
此外，注意包括电容器元件146的高频半导体元件145或者155可根据需要或者要求用于半导体器件160中。例如，通过使用包括电容器元件146的高频半导体元件145或者155，由重布线126实现的电感和电容器元件146可被组合，以相对容易实现滤波器，从而提高半导体器件160的高频特性。
(第五实施例)
在下文中，参考图17描述根据本发明第五实施例的半导体器件165。
根据本实施例的半导体器件165的特征在于包括防护部件166，该防护部件覆盖高频半导体元件110的高频元件111。注意在图7中，与图15所示相同的组件被赋予相同的标号。
在根据本实施例的半导体器件165中，正面向下(倒装)安装且经由电极120和121电连接到布线85、86以及连接焊盘87的高频元件111被防护部件166覆盖，并且半导体元件101被安装在防护部件166上。
根据本实施例，防护部件166覆盖高频元件111，并被电连接到在支撑衬底71上设置的接地端子(未示出)。注意例如铝(Al)或者镍黄铜(铜[Cu]-镍[Ni]-锌[Zn]合金)可用作防护部件166的材料，如同本发明的第二实施例中的一样。
通过设置覆盖高频元件111的防护部件166，可以减少或者防止半导体元件101、105和高频元件111之间的相互干扰。
注意本发明不限于上述特定实施例，并且在不背离本发明的范围条件下可进行变化和修改。
例如，在上述实施例中，为高频半导体元件的高频电极(高频外部连接端子)而设置的通孔被设置为从支撑衬底的一侧延伸到支撑衬底另一侧的一个通孔。但是，本发明不限于这种设置，并且其他实施例是可行的，其中用于高频电极的通孔在纵向上即在支撑衬底的深度方向上被分成几个部分，并且例如经由在分离的部分之间设置的布线层或者电极焊盘来实现电连接。在这种情况下，位置偏差可能出现在关于通孔纵向的垂直方向上。在此，对高频信号传输的影响可与通孔部分之间的位置偏差的减少(即当通孔的相互匹配部分的面积增加时)成比例降低。
本申请基于并要求2005年2月18日提交的日本专利申请号2005-042872的在先申请的权益，其全部内容由此通过参考并入。

Claims (8)

1.一种半导体器件，包括：
支撑衬底；
第一半导体元件，安装在该支撑衬底的一侧上；
第二半导体元件，包括安装在该支撑衬底的所述一侧上的高频电极以及耦合至该高频电极并面向该支撑衬底的重布线；
通孔，设置在与该高频电极相关联的支撑衬底上；以及
外部连接电极，设置在与该通孔相关联的支撑衬底的另一侧上。
2.如权利要求1所述的半导体器件，其中
该第二半导体元件被正面向下安装在该支撑衬底的所述一侧上。
3.如权利要求1所述的半导体器件，其中
该高频电极的中心轴被置于该通孔的外围之内。
4.如权利要求1所述的半导体器件，其中
该第一半导体元件被堆叠在该第二半导体元件上。
5.如权利要求1所述的半导体器件，其中
该第二半导体元件包括被设置为地电势的防护部件。
6.如权利要求1所述的半导体器件，其中
该重布线形成无源元件。
7.如权利要求1所述的半导体器件，其中
该第二半导体元件包括一对重布线结构，所述结构包括相互平行的部分。
8.如权利要求1所述的半导体器件，其中
该第二半导体元件包括具有相等布线长度的一组重布线结构。
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KR100690545B1 (ko) 2007-03-09
US9076789B2 (en) 2015-07-07
US8344490B2 (en) 2013-01-01
CN1822364A (zh) 2006-08-23
JP2006229072A (ja) 2006-08-31
US20060186524A1 (en) 2006-08-24
US20130082402A1 (en) 2013-04-04
TWI300618B (en) 2008-09-01

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