CN100382290C - 具有最优化的线接合配置的半导体封装 - Google Patents

具有最优化的线接合配置的半导体封装 Download PDF

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Publication number
CN100382290C
CN100382290C CNB2004800158306A CN200480015830A CN100382290C CN 100382290 C CN100382290 C CN 100382290C CN B2004800158306 A CNB2004800158306 A CN B2004800158306A CN 200480015830 A CN200480015830 A CN 200480015830A CN 100382290 C CN100382290 C CN 100382290C
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Prior art keywords
connection pads
signal
leads
lead
adjacent
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CN1802742A (zh
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罗伯特·J·文塞尔
彼得·R·哈珀
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Vlsi Technology Co ltd
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Freescale Semiconductor Inc
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Abstract

密排接合导线可用于不同的封装应用中，以实现改善的电气性能。在一个实施例中，如果对于导线分组中的两个相邻的接合导线中的较短导线的至少50%的长度，满足两个相邻导线之间的间距D，则这两个相邻导线是密排的。在一个实施例中，间距D至多是两个相邻导线中的具有较大直径的导线的直径的两倍。在另一实施例中，间距D至多是两个相邻导线之间的导线-导线心距的三倍。每个导线分组可以包括多个密排导线中的两个。密排接合导线的导线分组可用于形成，例如，电源-信号-地三元组、信号-地对、信号-电源对、或者差分信号对或三元组。

Description

具有最优化的线接合配置的半导体封装
技术领域
本发明通常涉及半导体封装，更具体地，涉及具有最优的线接合配置的半导体封装。
背景技术
在半导体封装中，线接合可用于提供从半导体管芯到封装基板的电气连接。例如，线接合可用于提供半导体管芯的接合焊盘到封装基板上的接合焊柱之间的电气连接。然而，随着半导体技术的发展，半导体管芯和封装基板之间所需的电气连接的数目增加，而半导体管芯和封装的尺寸持续减小。因此，随着对更多的连接的需要，目前的线接合半导体管芯，其同沿管芯外围的一行或多行焊盘接合，变为受焊盘限制。一旦受焊盘限制，在不减少连接数目的前提下，进一步减小管芯尺寸是不可能的。例如，一旦受焊盘限制，可能牺牲附加的地和电源焊盘，其可能损害电气性能。而且，在目前的线接合技术中，要尽可能地使导线保持分离，以防止短路。这还导致了具有增加的电感的较长的导线。因此，需要一种半导体封装，其具有改善的线接合配置，其考虑到减少的管芯尺寸和改善的电气性能。
发明内容
根据本发明第一方面，提供一种半导体封装，包括：第一器件，其具有表面和多个外围边缘，该第一器件具有多个连接焊盘，其配置在表面上并且沿垂直于多个外围边缘中的预定的一个边缘的轴配置；多个导线，多个导线的每一个具有第一末端，其电气连接到多个连接焊盘中的预定的一个连接焊盘，多个导线的每一个具有直径；第二器件，其具有表面，该表面具有多个连接焊盘，每个连接焊盘连接到多个导线中的预定的一个导线的第二末端，并且沿所述轴配置，其中，在沿多个导线的最短导线的至少50％的长度上，使多个导线中的相邻导线之间的间距保持不大于多个导线的最大直径的两倍。
根据本发明第二方面，提供一种半导体封装，包括：表面的第一部分，该第一部分具有多个连接焊盘，其配置在所述表面上并且沿预定的轴配置；多个导线，多个导线的每一个具有第一末端，其电气连接到多个连接焊盘中的预定的一个连接焊盘，多个导线的每一个具有直径；和所述表面的第二部分，其具有多个连接焊盘，每个连接焊盘连接到多个导线中的预定的一个导线的第二末端，所述多个连接导线沿所述轴配置，并且，在沿多个导线中的最短导线的至少50％的长度上，使多个导线中的相邻导线之间的间距保持不大于多个导线的最大直径的两倍。
附图简述
本发明是借助于示例说明的，并且不限于附图，在附图中，相同的参考符号表示相似的元件，并且其中：
图1说明了根据本发明的一个实施例的封装半导体器件的三维视图；
图2说明了根据本发明的一个实施例的图1的封装半导体器件的剖视图；
图3说明了根据本发明另一实施例的封装半导体器件的顶视图；
图4和5说明了根据本发明的替换实施例的空腔向下的带状球栅阵列(TPGA)封装半导体器件的剖视图；
图6说明了根据本发明的一个实施例的使用引线框的封装半导体器件的剖视图；
图7说明了根据本发明的一个实施例的使用中心接合焊盘的封装半导体器件的剖视图；
图8说明了根据本发明的一个实施例的多器件封装的剖视图。
技术人员应认识到，为了简化和清楚而说明了图中的元件，并且其不必依比例绘制。例如，图中的某些元件的尺寸可以相对于其他的元件放大，以协助增进对本发明的实施例的理解。
具体实施方式
随着半导体技术的发展，半导体管芯的尺寸持续减小，由此减少了可用于接合焊盘的空间量(并且因此，减少了针对半导体管芯的电气连接的数量)。此处公开的一个实施例涉及使用密排导线，以便于增加可能的电气连接的数量，并且改善电气性能。在一个实施例中，密排导线接合是这样的接合导线，其相互隔开一定的间距，其中对于至少50％导线长度(在某些实施例中，至少70％或至少80％的导线长度)，该间距不大于两倍的接合导线直径。在某些情况下，这些密排导线可用于改善信号-地比(或信号-电源-地对比)，其是用于表示半导体管芯的电气性能潜力的度量标准。即，从同步切换(地电反弹)的视点来考虑，该比越低，电气性能就越好，而该比越高，电气性能就越差。
在一个实施例中，对于半导体管芯的一部分或者全部的信号，为了改善电气性能，可以以地-信号-电源三元组、信号-地对、信号-电源对或电源-地对的设置使用密排导线。可替换地，密排导线还可用于差分信号(例如，用于具有对应于差分信号的正信号和负信号的对中或者用于还具有地信号的三元组中)。三元组或对中的密排导线提供了基本受控的阻抗，并且允许减少信号-地、信号-电源、或电源-地的回路电感。而且，还减少了相邻信号之间的串扰以及同信号总线关联的同步切换噪声。而且，在一个实施例中，三元组或对可以包括绝缘导线，由此可使两个或更多的导线接触。而且，在替换实施例中，可以使用多于两个或三个密排导线的导线分组设置。参考下文的图1～8将进一步理解这些实施例。
如此处使用的密排导线是如间距D定义的密排在一起的导线。即，如果对于两个相邻接合导线中的较短导线的至少50％的长度，满足间距D，则这两个相邻的接合导线是密排的。在一个实施例中，两个相邻导线之间的间距D指两个相邻导线的外表面之间的最短测量距离，并且其至多是两个相邻接合导线中的具有较大直径的导线的直径的两倍。(应当注意，两个相邻接合导线可以具有相同的直径或不同的直径。)因此，尽管两个相邻导线之间的距离可以沿导线的长度而改变，但是如果对于较短导线的至少50％的长度，满足间距D至多为具有较大直径的导线的直径的两倍，则认为它们是密排的。因此，应当注意，如此处所使用的，除非另外指出，否则图1～8的间距D对应于上文描述的相同的间距D(即，所描述的至多为具有较大直径的导线的直径的两倍)。
图1说明了根据本发明的一个实施例的封装半导体器件10的三维视图。封装半导体器件10包括覆于封装基板11上的半导体器件12。(应当注意，封装基板11也可以是引线框或其他的器件。)而且，在所说明的实施例中，半导体器件12的表面和封装基板11的表面位于在不同的平面中。封装半导体器件10还包括多个接合导线24～26、47～49和59～61，其提供了从半导体器件12的接合焊盘28、30、32、42、44、46、54、56和58到接合焊柱18、20和22以及封装基板11的接合位置36、38、50、52、62和64的电气连接。即，接合导线24、25和26分别提供了从接合焊盘28、30和32到接合位置38、接合焊柱18和接合位置36的电气连接。接合导线47、48和49分别提供了从接合焊盘42、44和46到接合位置52、接合焊柱20和接合位置50的电气连接。接合导线59、60和61分别提供了从接合焊盘54、56和58到接合位置64、接合焊柱22和接合位置62的电气连接。
应当注意，接合焊盘28、30、32、42、44、46、54、56和58、接合焊柱18、20和22以及电源总线14和16还可被称为连接点或连接焊盘。而且，这些连接点的每一个可以由本领域已知的任何电传导材料形成，诸如金、铜、铝等。而且，接合导线24～26、47～49和59～61可以是本领域已知的任何类型的电传导导线，诸如金、铜、铝等，并且在某些实施例中，可以是绝缘导线。例如，在一个实施例中，仅有导线25是绝缘的，而导线24和26可以不是绝缘的。可以使用任何类型的线接合工艺和设备形成接合导线24～26、47～49和59～61，例如，现今本领域中目前已知的工艺和设备。而且，如此处使用的，导线分组对应于一组两个或更多的密排导线，例如，导线24～26或导线47～49或导线59～61。应当注意，如上文所提及的，每个导线分组可以包括两个或更多的导线，并且不仅限于两个或三个导线。
封装基板11还包括电源总线14和电源总线16，其中电源总线14包括接合位置36、50和62，并且电源总线16包括接合位置38、52和64。在一个实施例中，电源总线14是地总线，电源总线16是Vdd总线。然而，在替换实施例中，电源总线14是Vdd总线，电源总线16是地总线。可替换地，接合位置36、50、62、38、52和64可以是分离的接合焊柱(诸如接合焊柱18、20和22)，而非总线基板上的接合位置。而且，应当注意，在一个实施例中，电源总线14和电源总线16均是环形结构，其围绕器件12，或者可替换地，是分段的环形结构。在所说明的实施例中，封装基板11上的每组连接位置以散开的设置相互隔开。即，接合位置62和64以及接合焊柱22的组可以同接合位置50和52以及接合焊柱20的组隔开，其之间的距离不同于接合位置50和52以及接合焊柱20的组同接合位置36和38以及接合焊柱18之间的距离。可替换地，可以平均地隔开连接位置的组。
半导体器件12可以是任何类型的半导体器件或管芯。例如，在一个实施例中，半导体器件12可以包括任何类型的电路，以实现任何所需的功能。可替换地，半导体管芯12可以是单独的有源或无源元件。可替换地，半导体器件12可以是由任何半导体材料，诸如，金属或陶瓷，制成的无源或有源元件。而且，半导体封装基板11可以是使用多种不同的材料，以多种不同的方法制造的任何类型的半导体封装，如本领域已知的。例如，在一个实施例中，如将参考图2描述的，封装基板11可以是球栅阵列(BGA)或基板栅格阵列(LGA)封装基板。
在所说明的实施例中，对于接合导线24和25中的较短的导线的至少50％的长度，接合导线24和接合导线25隔开间距D。如上文所述，在一个实施例中，间距D至多是接合导线24和接合导线25中的直径较大的导线的直径的两倍。即，在一个实施例中，接合导线24和接合导线25可以具有基本不同的预定的直径，并且在该情况中，导线24和25之间的间距D(对应于导线24和25的外边缘之间的最短测量距离)将至多是直径较大的导线的直径的两倍。而且，应当注意，间距D可以沿导线的长度而改变，但是沿最短导线(在该示例中是接合导线25)的至少50％的长度，其至多是较大直径的两倍。而且，应当注意，沿接合导线25和接合导线26中的最短导线的至少50％的长度，接合导线25和26保持间距D(其在一个实施例中也被定义为，至多为接合导线25和接合导线26中的直径较大的导线的直径的两倍)。应当注意，在接合导线24和25中的一个或两个绝缘的实施例中，间距D可以是0，由此接合导线24和25可以接触。
可替换地，应当注意，两个相邻接合导线之间的间距D可被定义为心距(separation pitch)(即，导线-导线心距)，其至多是较大直径的导线的直径的三倍。在该实施例中，如果假设接合导线25在直径上大于接合导线24，则对于接合导线25的至少50％的距离，接合导线24和25之间的心距(被定义为导线24的中心和导线25的中心之间的距离)至多是接合导线25的直径的三倍。
应当注意，接合导线24和25用作示例，然而，该段落中提供的关于导线24和25的相同描述同样适用于接合导线25和26、接合导线47和48、接合导线48和49。即，相同的描述通常适用于相同的导线分组中的任何两个相邻的导线(或密排导线)。
在所说明的实施例中，接合焊盘28、30和32被配置为，它们同基本上垂直于半导体器件12的外围边缘13的直线或轴(由虚线34表示)成一直线。相似地，应当注意，在所说明的实施例中，接合位置36和38以及接合焊柱18被配置为，它们同这样的直线(由虚线40表示)成一直线，该直线也垂直于由半导体器件12的相同边缘13定义的直线。然而，如下文所将讨论的，应当注意，在替换的实施例中，接合焊盘28、30、32可以相互不在同一直线上，并且可以不垂直于半导体器件12的边缘13。相似地，在替换实施例中，接合位置36和38以及接合焊柱18可以相互不在同一直线上，并且可以不垂直于由半导体器件12的边缘13定义的直线。例如，在一个实施例中，半导体器件12的拐角处(或者半导体器件12的任何其他位置处的)的接合焊盘可以是错列的。然而，在多种实施例中，不论接合焊盘、接合焊柱或接合位置在这些实施例中是如何配置的，对于两个相邻导线的较短导线的至少50％的长度，在导线分组中的两个相邻导线之间，保持间距D。还应当注意，在所说明的实施例中，接合焊盘28、30和32的组、接合焊盘42、44和46的组以及接合焊盘54、56和58的组全部平均地相互隔开，由此接合焊盘28、30和32的组同接合焊盘42、44和46的组之间的间距与接合焊盘42、44和46的组同接合焊盘54、56和58的组之间的间距相同。然而，可替换地，它们可以是不平均地隔开的，由此相邻的接合焊盘的组之间的间距是不同的。
在图1的所说明的实施例中，导线分组(诸如接合导线24～26)中的每个接合导线对于全部导线长度或者至少大部分导线长度，相互成一直线。即，至少50％的接合导线26直接位于接合导线25下面(隔开间距D)并与之成一直线，并且至少50％的接合导线25直接位于接合导线24下面(隔开间距D)并与之成一直线，由此在从顶部视角观察时(如将参考图3讨论的)，沿大部分导线长度看到单一的直线。在一个实施例中，如图1所说明的，对于尽可能长的导线长度，大部分接合导线相互成一直线，或者至少以间距D相互隔开。
在本发明的一个实施例中，图1的每个导线分组可以对应于电源-信号-地分组。例如，使用包括接合引线24～26的导线分组作为示例，接合焊盘30可以对应于经由接合导线25路由至或路由自接合焊柱18的半导体器件12的信号，而接合焊盘28可以对应于关于半导体器件12的VDD电源连接，其经由接合导线24路由自电源总线16，并且接合焊盘32可以对应于关于半导体器件12的地连接，其经由接合引线26路由自电源总线14。即，接合焊盘30可以是用于传导信号的信号总线，接合焊盘28可以是用于传导Vdd电源电压的电源总线，而接合焊盘32可以是用于传导地参考电压的电源总线。(可替换地，接合焊盘32、接合导线26和电源总线14可以对应于VDD电源连接，而接合焊盘28、接合导线24和电源总线16可以对应于地连接。)在这些实施例中，使信号接合导线位于对应的Vdd电源接合导线和地接合导线之间，通过充分控制阻抗，其允许，可以改善电气性能。而且，这样还可以减少串扰噪声。
然而，在另一实施例中，接合焊盘32可以对应于经由接合导线26路由至或路由自接合位置(其可以是接合焊柱，诸如接合焊柱18，但是位于接合位置36，其未在图1中示出)的半导体器件12的信号，而接合焊盘28或30中的一个对应于VDD电源连接，且另一个对应于地连接。在另一实施例中，接合焊盘28可以对应于经由接合导线24路由至或路由自接合位置(其可以是接合焊柱，诸如接合焊柱18，但是位于接合位置38，其未在图1中示出)的半导体器件12的信号，而接合焊盘30或32中的一个对应于VDD电源连接，且另一个对应于地连接。因此，在一个实施例中，对应于半导体器件12的信号的每个接合焊盘可以具有对应的VDD电源连接和地连接，其中所有连接经由密排接合导线路由至封装基板11，以便于通过充分控制阻抗，其允许减少信号-地和信号-电源回路电感，改善电气性能。然而，在替换实施例中，仅有一部分对应于半导体器件12的信号的接合焊盘可以在导线分组中。
还应当注意，可以在导线分组中以任何顺序提供信号、VDD电源和地连接，与此相似，也可以以任何顺序提供封装基板上的连接。例如，接合位置36、接合焊柱18和接合位置38可以具有同接合焊盘28、30、32相同的顺序，由此接合导线24将接合焊盘32连接到接合位置36，接合导线25将接合焊盘30连接到接合焊柱18，并且接合导线26将接合焊盘28连接到接合位置38。然而，在替换实施例中，封装基板11上的接合位置和接合焊柱可以以不同的顺序提供，由此接合导线可能相互交叉，或者可能因此而被弯曲，以实现正确的连接。例如，导线分组中的接合导线可以以任何形式缠绕在一起、弯曲、卷曲或变形，只要对于导线分组中的最短导线的至少50％的长度，任何两个相邻的导线隔开不超过间距D。应当注意，在导线交叉或缠绕的情况中，相邻的导线可能沿导线的长度变化。而且，一个或多个导线可以是绝缘的，由此它们可以沿大部分或几乎全部的导线长度接触(并且因此具有0的间距)。
应当注意，在替换实施例中，图1的某些或全部的导线分组可以是两个导线的导线分组。在该实施例中，仅需要接合焊盘28、30和32，并且仅需要两个接合位置36和38以及接合焊柱18。然而，上文参考三个导线的导线分组而提供的相同的描述通常应用于两个导线的导线分组。即，对于两个接合焊盘，一个可以是用于半导体器件12的信号的连接，而另一个可以是Vdd电源或地连接中的一个。而且，它们可以以相对于半导体器件12的边缘13的任何顺序安置。(例如，信号接合焊盘、VDD电源接合焊盘或地接合焊盘可以同边缘13最接近。)而且，按照需要，封装基板11上的接合位置和接合焊柱可以以任何顺序安置，其中导线分组中的两个导线可以交叉或卷曲或缠绕。而且，一个或多个导线可以是绝缘的。
在替换实施例中，导线分组可以具有三个导线，其中两个对应于差分信号对，而一个对应于地连接，或者可以仅具有两个导线，其对应于差分信号对，不具有本地组内的地线。上文针对电源-信号-地分组或电源-地-信号分组的分组而提供的相同的描述同样应用于这些类型的用于差分信号的三元组和对分组。而且，替换实施例可以在导线分组中包括多于三个导线，其中按照需要，接合焊盘、接合位置、接合焊柱可以以任何顺序按照需要配置在器件和封装基板上，并且其中导线分组中的任何两个相邻导线沿该两个相邻导线的较短导线的至少50％，隔开间距D。
在所说明的图1的实施例中，应当注意，每个接合导线位于密排导线的分组中。然而，应当注意，在替换实施例中，仅有一部分用于半导体器件12的接合导线可以位于导线分组中。
图2说明了图1的半导体器件10的剖视图。在图2中，可以看到，相同的三个导线的导线分组中的接合导线59～61如何全部成一直线并且沿任何两个相邻导线的最短导线的至少50％，隔开间距D。即，在图2的实施例中，接合导线59～61全部位于基本上垂直于封装基板11的顶表面83的平面上。所说明的图2的实施例还说明了封装层88(在图1中未示出)，其覆于半导体器件12、接合导线59～61和封装基板11的顶表面上。应当注意，封装层88可以是本领域中已知的任何类型的封装材料，并且通常是绝缘材料。还应当注意，封装层88是任选的，并且可以完全不存在。可替换地，封装层可以简单地是空气，其中封装半导体器件10可以包括壁和盖，以容纳封装基板11、器件12和接合导线59～61，其中空气填充该容器内的空的空间。
所说明的图2的实施例将封装基板11说明为具有多个互连70、72和74，底表面81上的多个焊区76、78和80，相对的顶表面83，以及覆于焊区上的多个焊球82、84和86。互连70、72和74直到底表面81(即直到对应的焊球)，在电源总线和顶表面83上的接合焊盘之间，路由信号和电源。因此，焊球82、84和86提供了通过封装基板11和接合导线59～61到达半导体器件12的电气连接。应当注意，封装基板11被说明为单一的互连层；然而，在替换实施例中，封装基板11可以包括任何数目的互连层(即，金属层)，其具有层间互连和层内互连，如本领域中已知的。因此，图2的实施例说明了在球栅阵列(BGA)应用中使用密排导线的示例。可替换地，焊球82、84和85可以不存在，诸如在基板栅格阵列(LGA)应用中。还应当注意，在替换实施例中，半导体器件12可以位于封装基板11内的凹陷空腔中。在一个实施例中，半导体器件12可以位于凹陷空腔中，由此接合焊盘54、56和58基本上同接合位置62和64以及接合焊柱22共面，或者甚至可以低于接合位置62和64以及接合焊柱22。
图3说明了使用密排导线的一个实施例的顶视图。图3包括一部分封装基板90和覆于封装基板90上的半导体器件120。如同半导体器件12，半导体器件120可以是任何类型的半导体器件或管芯，或者可以是任何类型的有源或无源元件。而且，封装基板90可以是任何类型的封装基板，并且可以使用多种不同类型的封装技术。半导体器件120包括多个接合焊盘98、100、102、106、108、110、122、124、126、150、152、136、138、140、160、162、164、174和176，其覆于半导体器件120的顶表面上。封装基板包括多个接合焊柱92、94、95、112、114、116、128、130、132、142、144、146、154、156、166、168、170、178和180，其覆于封装基板90的顶表面上。应当注意，在替换实施例中，某些接合焊柱按照需要，可以替换为电源总线上的接合位置，诸如例如，电源环或分段电源环。图3还包括导线分组104、118、134、148、158、172和182，其使接合焊盘电气连接到接合焊柱。每个导线分组具有多个导线(两个或更多)，但是由于它们被配置为一个在另一个上面，因此对于大部分导线长度，其呈现为一个导线，由此它们可以定义基本上垂直于封装基板90的顶表面的平面。而且，应当注意，对于较短导线的至少50％的长度，每个导线分组中的任何两个相邻导线相互隔开间距D。(再者，在一个实施例中，间距D至多是两个相邻导线中的具有最大直径的导线的直径的两倍。)
图3说明了用于不同的导线分组的多个可行设置的示例。例如，接合焊盘98、100和102经由包括3个接合导线的导线分组104，分别电气连接到接合焊柱96、94和92。应当注意，接合焊盘98、100和102被安置在半导体器件120的拐角上，并且与图1中的拐角焊盘不同，这些焊盘具有错列的设置，如对应的接合焊柱。然而，即使接合焊盘和焊柱是错列的，三个导线的每一个仍相互成一直线，由此由图3的顶视图，其呈现为单一的直线。在所说明的实施例中，导线分组104中的每个导线位于基本上垂直于封装基板90的顶表面的平面中。而且，尽管不能从图3中辨别，但是对于较短导线的至少50％的长度，每个相邻导线相互处于间距D内。如果从侧面观察，将看到将接合焊盘102连接到接合焊柱92的第一接合导线。然后，在其上面的间距D处，对于第一接合导线的至少50％的长度，将看到将接合焊盘100连接到接合焊柱94的第二接合导线。然后，在其上面的间距D处，对于第二接合导线的至少50％的长度，将看到将接合焊盘98连接到接合焊柱96的第三接合导线。
仍然参考图3，接合焊盘106、108和110经由包括3个接合导线的导线分组118，分别电气连接到接合焊柱116、114和112。在该示例中，每个接合焊盘和接合焊柱是共线的，并且垂直于由半导体器件120的外部边缘定义的直线。然而，应当注意，接合焊盘106、108和110对于接合焊柱112、114和116而言不是共线的。因此，在一个实施例中，它们可以相互不共线，但是如上文所述，对于最短导线的至少50％的长度，三个接合导线相互至少在间距D内。应当注意，随着导线接近接合焊柱或接合焊盘，导线可以相互偏离，以便于正确地连接它们。接合焊盘122、124和126经由包括3个接合导线的导线分组134，分别电气连接到接合焊柱132、130和128。针对导线分组118提供的相同的描述也应用于导线分组134。
如图3所说明的，半导体器件120还可以包括未安置在器件外围处的接合焊盘。例如，接合焊盘136、138和140未安置在外围，并且可以，例如，安置在器件的中心区域。接合焊盘136、138和140经由导线分组148分别电气连接到接合焊柱146、144和142。应当注意，导线分组148也包括3个导线，由于该导线对于大部分长度也是相互共线的，因此其呈现为一个导线，由此它们全体定义了基本上垂直于封装基板90的顶表面的平面。而且，该导线支持上文描述的间距D的间隔。中心接合焊盘可以对应于，例如，电源-信号-地(以任何顺序)、电源-地-电源、或者地-电源-地(诸如例如，以提供用于半导体器件120的核心电源分配)。中心接合焊盘还可以对应于也具有地连接的差分信号对。可替换地，中心接合焊盘可以是用于提供针对存储器的电气连接的中心接合焊盘阵列的一部分。
图3还包括接合焊盘150和152，其经由导线分组158分别电气连接到接合焊柱156和154。应当注意，导线分组158仅包括两个导线，其可以对应于，例如，信号-电源对、信号-地对、电源-地对或者差分信号对。再者，该导线对于大部分导线长度是共线的。而且，应当注意，在一个实施例中，如同接合焊盘150和152以及接合焊柱154和156，每个接合焊盘和接合焊柱自身是共线的，并且它们相互共线，由此导线分组158基本上垂直于半导体器件120的外部边缘。(可替换地，仅具有2个导线的导线分组可以基本上不与半导体器件120的外部边缘垂直，并且该导线可以连接到被安置为远离器件120的外围或者相对于器件120的边缘是错列的焊盘，其同导线分组104和118类似。)图3还包括接合焊盘160、162和164，其经由导线分组172，其包括3个均基本垂直于半导体器件120的外部边缘的导线，分别电气连接到接合焊柱170、168和166。在一个示例中，导线分组172中的3个导线可以对应于电源-信号-地(以任何顺序)或具有地连接的差分对。
图3还包括接合焊盘174和176，其同样未被安置在半导体器件120的外围处。它们可以安置在，例如，半导体器件120的中心部分。在一个实施例中，它们提供用于半导体器件120的核心(未示出)的电源和地。可替换地，它们可以提供针对存储器的中心连接。可替换地，它们可以对应于差分信号对。接合焊盘174和176经由仅包括2个导线的导线分组182分别电气连接到接合焊柱180和178。应当注意，由于仅需要两个接合焊柱，因此接合焊柱178和180可以相互隔开更远。相似地，应当注意，由于仅需要两个接合焊盘，因此接合焊盘174和176可以相互隔开更远。
因此，图3说明了用于以多种方式配置导线分组的多种不同的实施例。应当注意，在一个实施例中，沿半导体器件120的外围或非外围部分的每个信号可以包括另一连接(诸如，电源或地连接)，其导致了自每个信号位置延伸的2个导线的导线分组。可替换地，每个信号可以包括另外两个连接(诸如，电源和地连接)，其导致了自每个信号位置延伸的3个导线的导线分组。如上文所述，包括这些额外的电源和地连接的能力允许改善电气性能。而且，在导线分组中使用密排导线允许增加连接数目并减少回路电感。应当注意，图3的导线分组全部被说明为共线的和共面的(如图2的剖视图所示)；然而，如上文所讨论的，替换实施例可以使用导线分组中的任何导线设置，只要对于两个相邻导线的最短导线的至少50％，保持间距D。
如参考图4～8所将看到的，上文参考图1～3描述的密排导线的导线分组可用于除了BGA和LGA应用以外的多种不同的封装应用中。参考图4～8提供了某些示例。应当注意，这些图中说明的接合导线是导线分组中的密排导线，由此对于任何两个相邻导线的较短导线的至少50％的长度，保持两个相邻导线之间的间距D(其中间距D可以被定义为至多是较大导线的直径的两倍)。此处将不详细讨论图4～8中说明的封装技术，这是因为，根据前面的讨论，现在对于本领域的普通技术人员应显而易见的是，将此处描述的密排导线如何用于多种不同的应用。而且，为了简化，图4～8的每一个不包括可以在封装中实际发现的每个细节。例如，焊接掩膜和额外的层将不被说明，但是应当理解，可以进行适当地修改和添加，同时仍然使用密排接合导线。
图4说明了根据本发明的实施例的封装半导体器件200的一部分。(即，应当注意，仅说明了末端部分。)在一个实施例中，封装半导体器件200是空腔向下的带状球栅阵列TBGA)。封装半导体器件200包括散热器202(诸如例如，铜散热器)，其具有空腔204，其中空腔204包括附连到散热器202的半导体器件206。散热器还包括围绕空腔的底表面203上的粘合绝缘层208，以及覆于层208上的带状层210。(应当注意，如此处所使用的，覆盖可用于指顶或底表面上的层，不论哪个面在说明中朝上。)封装半导体器件200还包括多个传导焊盘，诸如传导焊盘212，和多个接合焊柱，诸如覆于带状层210上的接合焊柱218。应当注意，在一个实施例中，接合焊柱可被安置为同传导焊盘相邻，由此焊球和线接合均可以与之连接，诸如传导焊盘和接合焊柱216。而且，应当注意，传导焊盘可以是任何类型的传导材料，诸如金、镍-金、铜、铝或焊料。应当注意，封装半导体器件200还可以包括多个焊球，诸如焊球214，其覆于传导焊盘上。在所说明的实施例中，器件206的暴露表面(或底表面)207相比于接收线接合连接的散热器202的底表面203，凹陷到空腔204中。然而，在替换实施例中，应当注意，器件206的底表面207和散热器202的底表面203可以基本上是共面的，或者器件206的底表面207可以延伸越过空腔204。
相同的导线分组中的接合导线222和220提供了从半导体器件206到接合焊柱218以及传导焊盘和接合焊柱216的电气连接。因此，应当注意，对于接合导线222的至少50％的长度，接合导线222和220保持间距D。而且，应当注意，接合焊柱218同对应的传导焊盘和焊球之间的信号可以通过覆于带状层210上的迹线(未示出)提供，如本领域中已知的。应当注意，在替换实施例中，焊球可以不存在。而且，应当注意，在替换实施例中，散热器202可由封装基板替换，其具有多个互连层(其中层208和210将不再出现)，以将来自器件206的信号路由至传导焊盘或焊球，诸如空腔向下的BGA或空腔向下的LGA应用中的。应当注意，封装基板或散热器202、层208和210、传导焊盘212、传导焊盘和接合焊柱216、接合焊柱218、焊球214和空腔204可以使用如本领域中已知的传统的工艺或材料形成。
图5说明了根据本发明的实施例的封装半导体器件201的一部分。(即，应当注意，仅说明了末端部分。)在一个实施例中，封装半导体器件201是空腔向下的TBGA的另一示例。封装半导体器件201包括散热器230(诸如例如，铜散热器)，其具有空腔205，其中空腔205包括附连到散热器230的半导体器件242。散热器230还包括围绕空腔205的底表面231上的粘合绝缘层244，以及覆于粘合绝缘层244上的传导互连层248。封装半导体器件201还包括覆于传导互连层248上的带状层250，和多个传导焊盘，诸如传导焊盘233，以及多个接合焊柱，诸如接合焊柱238和236，其覆于带状层250上。信号可以从传导焊盘经由互连层248路由至接合焊柱。即，带状层250可以包括多个电传导过孔，诸如电传导过孔240，以将信号从传导焊盘路由至互连层248，并且将信号从互连层248路由至接合焊柱238和236。
应当注意，在一个实施例中，接合焊柱可被安置为同传导焊盘相邻，由此焊球和线接合均可以与之连接，诸如传导焊盘和接合焊柱234。而且，应当注意，传导焊盘可以是任何类型的传导材料，诸如铜、铝、金或焊料。应当注意，封装半导体器件201还可以包括多个焊球，诸如焊球232，其覆于传导焊盘上。而且，在所说明的实施例中，器件242的暴露表面(或底表面)241基本上同带状层250共面；然而，在替换实施例中，应当注意，器件242的暴露表面241可以进一步凹陷到空腔205中，或者可以进一步延伸越过空腔205。相同的导线分组中的接合导线224、226和228分别提供了从半导体器件242到接合焊柱和接合焊盘234、接合焊柱236以及接合焊柱238的电气连接。因此，应当注意，对于两个相邻导线的较短导线的至少50％的长度，接合导线224、226和228保持间距D。应当注意，在替换实施例中，焊球可以不存在。应当注意，散热器230、层244、248和250、电传导过孔240、传导焊盘233、传导焊盘和接合焊柱234、接合焊柱238、焊球232和空腔205可以使用如本领域中已知的传统的工艺或材料形成。
应当注意，在图5的替换实施例中，散热器230可由封装基板替换，其具有多个互连层，其中层244、248和250将不再出现，以将来自器件242的信号路由至传导焊盘或焊球，诸如空腔向下的BGA或空腔向下的LGA应用中的。在本实施例中，器件242的表面可以基本上同所述封装基板的底表面共面。
图6说明了根据本发明的实施例的封装半导体器件252的一部分。封装半导体器件252说明了四方扁平无引脚(QFN)封装的一个示例。封装半导体器件252包括覆于引线框258的第一部分260上的半导体器件256。引线框258还包括第二部分262，由此在一个实施例中，部分260对应于地连接，而第二部分262可以对应于信号或VDD电源连接。在所说明的实施例中，接合导线264和266是相同导线分组中的密排导线(具有间距D)，并且提供了器件256同引线框258的部分260和262之间的电气连接。而且，成型(molding)化合物254可以覆于器件256和引线框258上，以及引线框258的部分260和262之间。应当注意，引线框258和成型化合物254可以使用如本领域已知的传统的工艺和材料形成。而且，应当注意，封装半导体器件252可被修改为四方扁平封装(QFP)或小外形封装(SOP)，其均能够使用导线分组中的密排导线实现改善的电气性能和改善的间隔。
图7说明了根据本发明的一个实施例的封装半导体器件300，其使用中心接合焊盘连接。如上文讨论的，除了器件外围以外，或者作为器件外围的替换，接合焊盘也可被安置在器件的中心部分中。因此，封装半导体器件300包括具有暴露部分的半导体器件302，其具有中心接合焊盘，诸如接合焊盘307和308。封装基板306覆于器件302的顶表面上，并且暴露该暴露部分。封装材料304可以覆于器件302的底表面303和封装基板306上，如本领域已知的。封装基板306还可以包括传导焊盘，诸如传导焊盘321，和多个接合焊盘，诸如接合焊盘314和313，其覆于封装基板306的顶表面305上。封装基板306还可以包括焊球，诸如焊球320，其覆于传导焊盘上。接合导线311和310位于第一密排导线的导线分组中，并且分别提供了从接合焊柱307和308到接合焊盘313和314的电气连接。接合导线316、317和318还提供了从器件302到封装基板306的电气连接，并且可以是第二密排导线的导线分组的一部分。封装基板306可以包括一个或多个互连或金属层，以将信号从接合焊盘路由到焊球。封装半导体基板还可以包括第二封装材料301，其覆于器件302的暴露表面部分、一部分封装基板306的顶表面305、以及接合导线310、311316、317和318上。在一个实施例中，器件302可以包括静态随机存取存储器(SRAM)或动态随机存取存储器(DRAM)或者任何其他类型的存储器或其他的具有中心接合焊盘的器件。应当注意，封装基板306、器件302、封装材料301和304、以及焊球320可以使用如本领域中已知的传统的工艺或材料形成。
图8说明了多器件封装340的一个实施例。封装340包括封装基板346和器件342、344和350，其中器件342和344覆于封装基板346上，并且器件350覆于器件344上。应当注意，在一个实施例中，每个器件342、344和350可以是半导体器件或任何其它类型的有源器件，或者甚至可以是无源器件。因此，任何器件的组合可以安置在封装340中。封装340包括多个导线分组，每个导线分组被说明为具有3个密排导线(其中，在图8中，每个导线被说明为单一的导线)。导线分组358提供了从器件342到封装基板346的电气连接，导线分组356提供了从器件342的一部分到器件342的另一部分的电气连接，导线分组354提供了从器件342到器件344的电气连接，导线分组352提供了器件350和器件344之间的电气连接，而导线分组362提供了从封装基板346的一部分到封装基板346的另一部分的电气连接。应当注意，尽管没有示出，但是导线分组可以提供器件350和封装基板346之间的电气连接。封装340还可以包括封装材料360，其封装器件342、344和350，以及导线分组358、356、354、352和362。封装基板还可以包括传导焊盘，诸如传导焊盘349，其覆于封装基板346的底表面上(同具有器件342、344和350的表面相对)，以及焊球，诸如焊球348，其覆于传导焊盘上。因此，在相同的器件中，或者在相同的封装基板中，可以以多种方式使用如此处讨论的具有密排导线的导线分组，以提供从器件到器件，或从器件到封装基板的多种不同的电气连接。它们还可用于提供从诸如管芯的有源器件到无源器件的电气连接，或者堆叠器件之间的电气连接。
因此，现在可以认识到，导线分组中的密排导线的使用如何用于多种不同的应用中，以通过更好地控制阻抗实现改善的电气性能，并且减少信号-地、信号-电源和电源-地回路电感。而且，还可以减少相邻信号之间的串扰以及与信号总线关联的同步切换噪声。如上文描述的，导线分组中的密排导线是这样的接合导线，其沿两个相邻导线的最短导线的至少50％的长度，在两个相邻导线之间具有间距D。每个导线分组可以包含对应于不同类型的连接的导线，诸如对应于信号、Vdd电源、核心电源、地、差分信号等。而且，接合导线和对应的连接点(接合焊盘、接合焊柱和接合位置)可以以多种不同的方式配置，同时仍维持适当的间距D，以实现改善的电气性能。
而且，尽管上文的描述将密排导线描述为这样的导线，即对于较短导线的至少50％的长度，满足至多为较大导线的直径的两倍的间距D，但是替换实施例还可以定义不同的密排导线。例如，在一个实施例中，对于两个相邻的接合导线的较短导线的至少60％的长度，或者可替换地，对于两个相邻的接合导线的较短导线的至少70％或80％的长度，满足关于密排导线的间距D。在另一实施例中，如果对于两个相邻的接合导线的相反末端处的连接点(诸如连接焊盘、接合焊盘、接合焊柱等)之间的至少50％的距离，满足间距D至多为具有较大直径的导线的直径的两倍，则两个相邻导线被认为是密排导线。例如，参考图4，如果对于器件206的连接点和传导焊盘218之间的至少50％的距离，满足间距D至多为接合导线220和接合导线222中的较大的导线的直径的两倍，则接合导线220和222可被认为是密排的。可替换地，对于该实施例，对于器件之间的至少60％的距离，或者对于连接点之间的至少70％或80％的距离，满足关于密排导线的间距D。
还应当注意(如上文参考图1简要讨论的)，可替换地，间距D可用心距表述，由此密排导线可以指这样的导线，对于较短导线的至少50％的长度(或者对于连接到导线末端的两个器件之间的至少50％的距离)，其满足至多为较大的直径的三倍的心距P(在两个相邻导线的中心之间测量的最短距离，即导线-导线心距)。可替换地，可以针对较短导线的至少60％、70％或80％的长度(或者对于连接点之间的至少60％、70％或80％的距离)，满足心距。因此，这些提供用于密排导线的替换定义可以在上文参考图1～8描述的每个实施例中使用。
在前面的说明书中，通过参考具体的实施例描述了本发明。然而，本领域的普通技术人员应认识到，在不偏离所附权利要求中陈述的本发明的范围的前提下，可以进行多种修改和变化。因此，说明书和附图应被认为是说明性的，而非限制性的，并且所有该修改应涵盖在本发明的范围内。
上文通过针对具体的实施例，描述了优点、优势和针对问题的解决方案。然而，该优点、优势和针对问题的解决方案以及可以使任何优点、优势和针对问题的解决方案出现或变的更加显著的任何因素，不应被解释为任何或全部权利要求的关键的、必需的或基本的特征或因素。如此处使用的，术语“包括”或其任何变化形式，目的在于涵盖非排他性的内含物，由此包括一系列要素的工艺、方法、物体或装置不仅包括这些要素，而且可以包括未明确列出的或该工艺、方法、物体或装置所固有的其他的要素。

Claims (14)

1.一种半导体封装，包括：
第一器件，其具有表面和多个外围边缘，该第一器件具有多个连接焊盘，其配置在表面上并且沿垂直于多个外围边缘中的预定的一个边缘的轴配置；
多个导线，多个导线的每一个具有第一末端，其电气连接到多个连接焊盘中的预定的一个连接焊盘，多个导线的每一个具有直径；
第二器件，其具有表面，该表面具有多个连接焊盘，每个连接焊盘连接到多个导线中的预定的一个导线的第二末端，并且沿所述轴配置，其中，在沿多个导线的最短导线的至少50％的长度上，使多个导线中的相邻导线之间的间距保持不大于多个导线的最大直径的两倍。
2.权利要求1的半导体封装，其中，第一器件的表面配置在第一平面中，而第二器件的表面配置在不同于第一平面的第二平面中。
3.权利要求1的半导体封装，其中，第一器件的表面和第二器件的表面配置在相同的平面中。
4.权利要求1的半导体封装，进一步包括：
多个连接焊盘中的第一连接焊盘，其与多个外围边缘中的预定的一个边缘相邻，并且是用于传导第一电源信号的第一电源总线；
多个连接焊盘中的第二连接焊盘，其沿所述轴与第一连接焊盘相邻，并朝向第一器件的内部部分，并且是用于传导信号的信号总线；和
多个连接焊盘中的第三连接焊盘，其沿着所述轴，并且同第二连接焊盘相邻，其中，第二连接焊盘隔开第一连接焊盘和第三连接焊盘，第三连接焊盘是用于传导第二电源信号的第二电源总线，其中，将信号总线配置在第一电源总线和第二电源总线之间，对于第一电源信号、第二电源信号和在所述信号总线中传导的信号，实现了降低的回路电感。
5.权利要求1的半导体封装，进一步包括：
多个连接焊盘中的第一连接焊盘，其沿着所述轴，并且与多个外围边缘中的预定的一个边缘相邻，并且是用于传导第一电源信号的第一电源总线；
多个连接焊盘中的第二连接焊盘，其沿所述轴，并且与第一连接焊盘相邻，并朝向第一器件的内部部分，并且是用于传导第二电源信号的第二电源总线；和
多个连接焊盘中的第三连接焊盘，其同第二连接焊盘相邻，其中，第二连接焊盘沿所述轴隔开第一连接焊盘和第三连接焊盘，第三连接焊盘是用于传导信号的信号总线，由此将信号总线配置为与第一电源总线和第二电源总线相邻，对于第一电源信号、第二电源信号和在所述信号总线中传导的信号，实现了降低的回路电感。
6.权利要求1的半导体封装，进一步包括：
多个连接焊盘中的第一连接焊盘，其沿着所述轴，并且与多个外围边缘中的预定的一个边缘相邻，并且是用于传导电源信号的电源总线；和
多个连接焊盘中的第二连接焊盘，其沿所述轴并且与第一连接焊盘相邻，并朝向第一器件的内部部分，并且是用于传导信号的信号总线。
7.权利要求1的半导体封装，进一步包括：
多个连接焊盘中的第一连接焊盘，其沿着所述轴，并且与多个外围边缘中的预定的一个边缘相邻，该第一连接焊盘是用于传导信号的信号总线；和
多个连接焊盘中的第二连接焊盘，其沿所述轴并且与第一连接焊盘相邻，并朝向第一器件的内部部分，该第二连接焊盘是用于传导电源信号的电源总线。
8.权利要求1的半导体封装，进一步包括：
多个连接焊盘中的第一连接焊盘，其沿着所述轴，并且与多个外围边缘中的预定的一个边缘相邻，该第一连接焊盘是用于传导第一电源信号的第一电源总线；和
多个连接焊盘中的第二连接焊盘，其沿所述轴并且与第一连接焊盘相邻，并朝向第一器件的内部部分，该第二连接焊盘是用于传导第二电源信号的第二电源总线。
9.权利要求1的半导体封装，其中，第一器件进一步包括：
第二多个连接焊盘，其被安置为远离多个外围边缘，朝向第一器件的非外围部分，该第二多个连接焊盘具有作为第一电源总线的第一连接焊盘和作为第二电源总线的第二连接焊盘。
10.权利要求1的半导体封装，其中，第一器件进一步包括：
第二多个连接焊盘，其被安置为远离多个外围边缘，朝向第一器件的非外围部分，该第二多个连接焊盘具有至少三个连接焊盘，这三个连接焊盘中的任何一个都可以作为信号总线或电源总线。
11.权利要求1的半导体封装，其中，第一器件进一步包括额外的多个连接焊盘，其配置在所述表面上，并且沿着脱离第一器件的、第一器件的拐角附近的第二轴，额外的多个连接焊盘的每一个通过各自的导线电气连接到第二器件，所有的额外的多个连接焊盘都沿着所述第二轴，并且每个各自的导线同相邻的导线的间距不大于其最大直径的两倍。
12.权利要求1的半导体封装，其中，全部多个导线具有尺寸相同的导线直径。
13.权利要求1的半导体封装，其中，第一器件被配置为，覆于一部分第二器件上，以形成堆叠半导体结构。
14.一种半导体封装，包括：
表面的第一部分，该第一部分具有多个连接焊盘，其配置在所述表面上并且沿预定的轴配置；
多个导线，多个导线的每一个具有第一末端，其电气连接到多个连接焊盘中的预定的一个连接焊盘，多个导线的每一个具有直径；和
所述表面的第二部分，其具有多个连接焊盘，每个连接焊盘连接到多个导线中的预定的一个导线的第二末端，所述多个连接导线沿所述轴配置，并且，在沿多个导线中的最短导线的至少50％的长度上，使多个导线中的相邻导线之间的间距保持不大于多个导线的最大直径的两倍。
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