US9271390B2 - Semiconductor device with active shielding of leads - Google Patents
Semiconductor device with active shielding of leads Download PDFInfo
- Publication number
- US9271390B2 US9271390B2 US14/332,372 US201414332372A US9271390B2 US 9271390 B2 US9271390 B2 US 9271390B2 US 201414332372 A US201414332372 A US 201414332372A US 9271390 B2 US9271390 B2 US 9271390B2
- Authority
- US
- United States
- Prior art keywords
- wire
- shielding
- bond
- pad
- guarded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 description 11
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000006880 cross-coupling reaction Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the present invention relates generally to semiconductor devices and, more particularly, to shielding the leads of semiconductor devices.
- Some semiconductor devices have lead frames that include leads, and bond wires that extend between the leads and bonding pads of a die mounted on a paddle or flag of the lead frame.
- the leads transmit signals, power and ground to/from the die.
- Two leads that carry signals located near each other may couple to one another. This is referred to as “crosstalk” or “cross-coupling,” where variations in one signal can affect amplitudes of nearby signals.
- a ground shield may be provided between the leads.
- One approach for providing passive, ground shielding is to connect every other lead to ground to avoid coupling. However, this limits the number of leads that may be used to carry signals.
- Active shielding is another approach to providing shielding in electronic networks.
- Active shielding is a shielding technique in which one or more shielding lines transmit signals that are dependent upon the signals transmitted by the guarded line. Capacitive coupling is reduced with active shielding when the shielding lines transmit signals in the same direction as the guarded line and inductive coupling is reduced when the shielding lines transmit signals in the opposite direction as the guarded line.
- Active shielding is typically implemented using the layouts of one or both of the integrated circuits (dies) or printed circuit boards (PCBs).
- LQFP low-profile quad flat packages
- active shielding has not been implemented because conventional LFQP layouts and lead frame arrangements do not allow realization of active shielding.
- unwanted cross-coupling may occur.
- FIGURE is a simplified top plan view of a part of a semiconductor package made in accordance with an embodiment of the present invention.
- the present invention is a semiconductor device comprising a die having a multi-site bond pad; a multi-wire lead; at least one shielding wire extending from the multi-wire lead to the multi-site bond pad; and a guarded wire extending from the multi-wire lead to the multi-site bond pad.
- Another embodiment of the invention is a method of actively shielding a guarded wire on a semiconductor device.
- the method comprises (a) transmitting a first signal along the guarded wire extending between a multi-wire lead and a die having a multi-site bond pad; and (b) simultaneously transmitting the first signal along at least one shielding wire extending from the multi-wire lead to the multi-site bond pad.
- the FIGURE shows a simplified top plan view of a part of a partially assembled semiconductor device 100 made in accordance with an embodiment of the present invention.
- the semiconductor device 100 shown comprises a die 101 attached to a die flag or paddle 102 .
- the die 101 has bond pads 103 that are electrically connected to leads 104 with bond wires 105 .
- a lead frame is a collection of metal leads and possibly other elements (e.g., ground bars and power bars) that is used in semiconductor packaging.
- a lead frame Prior to assembly into a packaged device, a lead frame may have support structures (e.g., a rectangular metal frame) that keep those elements in place. During the assembly process, the support structures may be removed.
- the term “lead frame” may be used to refer to the collection of elements before assembly or after assembly, regardless of the presence or absence of those support structures.
- Signals are transmitted between at least some of the leads 104 and the corresponding die bond pads 103 via corresponding bond wires 105 .
- signals can suffer cross-coupling from signals transmitted on bond wires of adjacent leads.
- active shielding of the bond wires 105 is achieved through the use of a multi-wire lead 106 and a multi-site bond pad 107 .
- the multi-wire lead 106 can be formed as a unitary lead during formation of the lead frame or alternatively may be part of an overlay assembly that may be placed over an already existing lead frame.
- the multi-wire lead 106 is T-shaped.
- a multi-wire lead may be formed or placed on the lead to form a cross or other shape that is capable of having multiple bond wires attached to it.
- a conventional (e.g., straight) lead may be capable of accommodating multiple bond wires without modification.
- the three bond wires attached to the multi-wire lead 106 shown in the FIGURE are referred to herein as shielding wires 108 and guarded wire 109 .
- the shielding wires 108 are attached on opposite sides of the multi-wire lead 106 and carry the same signal as the guarded wire 109 , which is located between the two shielding wires 108 .
- the guarded wire 109 also is attached to the multi-wire lead 106 .
- the shielding wires 108 extend from the multi-wire lead 106 to the die 101 proximate and adjacent to the guarded wire 109 as it extends from the multi-wire lead 106 to the die 101 .
- the shielding wires 108 take the impact of any potential cross-talk that might otherwise occur between the guarded wire 109 and any signals being transmitted on adjacent bond wires 105 . This is active shielding of the guarded wire 109 . While two shielding wires 108 are shown in the embodiment disclosed, it should be understood that, in some instances, one shielding wire may be sufficient to prevent cross-talk with an adjacent wire, or in some instances more than two shielding wires may be needed to prevent cross-talk.
- the multi-site bond pad 107 has the two shielding wires 108 and the one guarded wire 109 attached to it at two shielding-wire bond-pad sites 110 and one guarded-wire bond-pad site 111 , respectively.
- the two shielding-wire bond-pad sites 110 and one guarded-wire bond-pad site 111 are physically connected to one another without having impedance between any two of them.
- the multi-site bond pad 107 may be formed during the formation of the die 101 or may be part of an overlay process that modifies an existing die to provide multiple sites for receiving the shielding wires and guarded wire.
- the shielding-wire bond-pad sites 110 are located on either side of the guarded-wire bond-pad site 111 .
- the same signals are transmitted between (i) the multi-wire lead 106 and (ii) the shielding-wire bond-pad sites 110 and the guarded-wire bond-pad site 111 by way of the shielding wires 108 and the guarded wire 109 , respectively.
- the shielding wires 108 extending between the multi-site bond pad 107 and the multi-wire lead 106 provide active shielding for the signals transmitted along the guarded wire.
- the active shielding reduces cross-talk between the guarded wire and adjacent bond wires connected to other leads. Active shielding comes at an increased cost of power consumption. Thus, sufficient current should be provided to the guarded wire to ensure that the transmitted signal is strong enough.
- the three bond wires electrically shorted to one another carry the electric field in the same direction. Due to the Miller Effect, the capacitance on the guarded wire becomes zero, and the guarded wire is not affected by the adjacent bond wires or the shielding wires.
- the Miller Effect states that the effective coupling capacitance between two nodes is zero if the transitions at the two nodes occur at the same time and in the same direction.
- the active shielding of the present invention is able to provide protection for signals transmitted on guarded wires. Active shielding is able to help protect global clock networks and high-speed networks in semiconductor packages.
- each may be used to refer to one or more specified characteristics of a plurality of previously recited elements or steps.
- the open-ended term “comprising” the recitation of the term “each” does not exclude additional, unrecited elements or steps.
- an apparatus may have additional, unrecited elements and a method may have additional, unrecited steps, where the additional, unrecited elements or steps do not have the one or more specified characteristics.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/332,372 US9271390B2 (en) | 2014-07-15 | 2014-07-15 | Semiconductor device with active shielding of leads |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/332,372 US9271390B2 (en) | 2014-07-15 | 2014-07-15 | Semiconductor device with active shielding of leads |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160021734A1 US20160021734A1 (en) | 2016-01-21 |
US9271390B2 true US9271390B2 (en) | 2016-02-23 |
Family
ID=55075813
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/332,372 Active US9271390B2 (en) | 2014-07-15 | 2014-07-15 | Semiconductor device with active shielding of leads |
Country Status (1)
Country | Link |
---|---|
US (1) | US9271390B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI545431B (en) * | 2015-04-30 | 2016-08-11 | 群暉科技股份有限公司 | Method for performing power management in an electronic system, and associated apparatus |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4891686A (en) * | 1988-04-08 | 1990-01-02 | Directed Energy, Inc. | Semiconductor packaging with ground plane conductor arrangement |
US5646451A (en) * | 1995-06-07 | 1997-07-08 | Lucent Technologies Inc. | Multifunctional chip wire bonds |
US6307272B1 (en) * | 1998-05-27 | 2001-10-23 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
US6476506B1 (en) | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
US6528880B1 (en) * | 2001-06-25 | 2003-03-04 | Lovoltech Inc. | Semiconductor package for power JFET having copper plate for source and ribbon contact for gate |
US6597065B1 (en) * | 2000-11-03 | 2003-07-22 | Texas Instruments Incorporated | Thermally enhanced semiconductor chip having integrated bonds over active circuits |
US6713881B2 (en) | 2000-05-29 | 2004-03-30 | Texas Instruments Incorporated | Semiconductor device and method of manufacturing same |
US6812580B1 (en) | 2003-06-09 | 2004-11-02 | Freescale Semiconductor, Inc. | Semiconductor package having optimized wire bond positioning |
US6882047B2 (en) * | 2001-10-19 | 2005-04-19 | Renesas Technology Corp. | Semiconductor package including a plurality of semiconductor chips therein |
US7030490B2 (en) * | 2003-07-22 | 2006-04-18 | Via Technologies, Inc. | Structure of multi-tier wire bonding for high frequency integrated circuit |
US7087993B2 (en) * | 2003-12-05 | 2006-08-08 | Via Technologies, Inc. | Chip package and electrical connection structure between chip and substrate |
US7501709B1 (en) | 2006-08-25 | 2009-03-10 | Altera Corporation | BGA package with wiring schemes having reduced current loop paths to improve cross talk control and characteristic impedance |
US20100032818A1 (en) * | 2008-08-05 | 2010-02-11 | Pilling David J | Lead frame package |
US7804167B2 (en) | 2006-12-01 | 2010-09-28 | Lsi Logic Corporation | Wire bond integrated circuit package for high speed I/O |
US20130043961A1 (en) | 2011-08-15 | 2013-02-21 | Avago Technologies Wireless Ip (Singapore) Pte.Ltd | Duplexer with shielding bondwires between filters |
US8536688B2 (en) * | 2004-05-25 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit leadframe and fabrication method therefor |
US8558398B1 (en) * | 2012-10-22 | 2013-10-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Bond wire arrangement for minimizing crosstalk |
-
2014
- 2014-07-15 US US14/332,372 patent/US9271390B2/en active Active
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4891686A (en) * | 1988-04-08 | 1990-01-02 | Directed Energy, Inc. | Semiconductor packaging with ground plane conductor arrangement |
US5646451A (en) * | 1995-06-07 | 1997-07-08 | Lucent Technologies Inc. | Multifunctional chip wire bonds |
US6307272B1 (en) * | 1998-05-27 | 2001-10-23 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
US6713881B2 (en) | 2000-05-29 | 2004-03-30 | Texas Instruments Incorporated | Semiconductor device and method of manufacturing same |
US6597065B1 (en) * | 2000-11-03 | 2003-07-22 | Texas Instruments Incorporated | Thermally enhanced semiconductor chip having integrated bonds over active circuits |
US6528880B1 (en) * | 2001-06-25 | 2003-03-04 | Lovoltech Inc. | Semiconductor package for power JFET having copper plate for source and ribbon contact for gate |
US6476506B1 (en) | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
US6882047B2 (en) * | 2001-10-19 | 2005-04-19 | Renesas Technology Corp. | Semiconductor package including a plurality of semiconductor chips therein |
US6812580B1 (en) | 2003-06-09 | 2004-11-02 | Freescale Semiconductor, Inc. | Semiconductor package having optimized wire bond positioning |
US7030490B2 (en) * | 2003-07-22 | 2006-04-18 | Via Technologies, Inc. | Structure of multi-tier wire bonding for high frequency integrated circuit |
US7087993B2 (en) * | 2003-12-05 | 2006-08-08 | Via Technologies, Inc. | Chip package and electrical connection structure between chip and substrate |
US8536688B2 (en) * | 2004-05-25 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit leadframe and fabrication method therefor |
US7501709B1 (en) | 2006-08-25 | 2009-03-10 | Altera Corporation | BGA package with wiring schemes having reduced current loop paths to improve cross talk control and characteristic impedance |
US7804167B2 (en) | 2006-12-01 | 2010-09-28 | Lsi Logic Corporation | Wire bond integrated circuit package for high speed I/O |
US20100032818A1 (en) * | 2008-08-05 | 2010-02-11 | Pilling David J | Lead frame package |
US20130043961A1 (en) | 2011-08-15 | 2013-02-21 | Avago Technologies Wireless Ip (Singapore) Pte.Ltd | Duplexer with shielding bondwires between filters |
US8558398B1 (en) * | 2012-10-22 | 2013-10-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Bond wire arrangement for minimizing crosstalk |
Non-Patent Citations (2)
Title |
---|
Himanshu Kaul, Dennis Sylvester, David Blauuw, "Active Shields: A New Approach to Shielding Global Wires", GLSVLSI '02, Apr. 18-19, 2002, New York, New York, USA; (c) 2002 ACM 1-58113-462-2/02/0004. |
Himanshu Kaul, Dennis Sylvester, David Blauuw, "Performance Optimization of Critical Paths Through Active Shielding", IEEE Transactions on Circuits and Systems-I, vol. 51, No. 12, Dec. 2004. |
Also Published As
Publication number | Publication date |
---|---|
US20160021734A1 (en) | 2016-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108140616B (en) | Semiconductor device with a plurality of transistors | |
US8558398B1 (en) | Bond wire arrangement for minimizing crosstalk | |
US9955581B2 (en) | SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern | |
US9018741B2 (en) | Semiconductor package and manufacturing method thereof | |
US20130320530A1 (en) | Semiconductor device with redistributed contacts | |
KR20140131813A (en) | Chip on film package including the distributed via plugs | |
US7015569B1 (en) | Method and apparatus for implementing a co-axial wire in a semiconductor chip | |
CN104966703A (en) | Integrated circuit package and method of forming same | |
KR20130019249A (en) | Memory device and and fabricating method thereof | |
US9271390B2 (en) | Semiconductor device with active shielding of leads | |
US8446735B2 (en) | Semiconductor package | |
US20110157852A1 (en) | Semiconductor device and circuit board | |
US9893001B2 (en) | Semiconductor device, corresponding methods of production and use and corresponding apparatus | |
KR101573283B1 (en) | Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same | |
US9299646B1 (en) | Lead frame with power and ground bars | |
US10765046B2 (en) | Electromagnetic interference shields for electronic packages and related methods | |
US9147656B1 (en) | Semiconductor device with improved shielding | |
US9070700B2 (en) | Apparatus for electrostatic discharge protection and noise suppression in circuits | |
CN204315564U (en) | Lead frame and semiconductor package body | |
US9954355B1 (en) | Transient voltage suppressor apparatus | |
JP5277491B2 (en) | Semiconductor device | |
CN101908514B (en) | Semiconductor device | |
US20160233183A1 (en) | Integrated circuit die with corner io pads | |
CN107658287A (en) | A kind of lead frame | |
US20150327390A1 (en) | Electronic module, electronic system and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SRIVASTAVA, SUNAINA;IMAM, RAZA;KANSAL, GAGAN;AND OTHERS;SIGNING DATES FROM 20140701 TO 20140703;REEL/FRAME:033330/0912 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034160/0370 Effective date: 20141030 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034160/0351 Effective date: 20141030 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034153/0027 Effective date: 20141030 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034153/0027 Effective date: 20141030 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034160/0370 Effective date: 20141030 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034160/0351 Effective date: 20141030 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0921 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037458/0460 Effective date: 20151207 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037458/0502 Effective date: 20151207 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: MERGER;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:041144/0363 Effective date: 20161107 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |