JP5257722B2 - 高周波モジュール - Google Patents
高周波モジュール Download PDFInfo
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- JP5257722B2 JP5257722B2 JP2012137437A JP2012137437A JP5257722B2 JP 5257722 B2 JP5257722 B2 JP 5257722B2 JP 2012137437 A JP2012137437 A JP 2012137437A JP 2012137437 A JP2012137437 A JP 2012137437A JP 5257722 B2 JP5257722 B2 JP 5257722B2
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- 239000000758 substrate Substances 0.000 claims abstract description 121
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000003795 chemical substances by application Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 241000238366 Cephalopoda Species 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
Description
スイッチIC素子SW−,SW+を基板101の部品実装面に重ねて実装することにより、二つのスイッチIC素子を用いて、平衡信号のスイッチ回路を構成する場合に、実装面積を小さくすることができる。
スイッチIC素子SW−,SW+を基板101Aの部品実装面に重ねて実装することにより、二つのスイッチIC素子を用いて、平衡信号のスイッチ回路を構成する場合に、実装面積を小さくすることができる。特に、本実施形態にように、選択線路数が増加するほど、より高周波モジュールの小型化に有効に作用する。
101,101A:基板、
120:ダイフィルム、
130:ダイボンド剤、
SW−,SW+,SW3−,SW3+:スイッチIC素子、
Claims (6)
- 平衡信号のスイッチ回路を構成し、パッド電極の配置構成が同じ第1スイッチICおよび第2のスイッチICと、
前記パッド電極に接続するランド電極を備え、前記第1スイッチICおよび第2のスイッチICを外部回路へ接続する電極を備える基板と、を備え、
前記第1スイッチICは、前記基板に実装され、
前記第2スイッチICは、前記第1スイッチICの前記基板と反対側の面に実装され、
前記第1スイッチICと前記第2スイッチICは、前記パッド電極が前記基板側と反対側の面に現れるように実装され、
前記パッド電極のそれぞれと、前記ランド電極とは、ワイヤーボンディングによって接続され、
前記ワイヤーボンディングによって接続される前記パッド電極のそれぞれと、前記ランド電極との間には、他のランド電極または他のパッド電極が配設されていない、高周波モジュール。 - 前記第1スイッチICと前記第2スイッチICは同じスイッチICである、請求項1に記載の高周波モジュール。
- 前記第2スイッチICは、前記第1スイッチICの前記基板と反対側の面に、接着剤を介して実装されている、請求項1または2に記載の高周波モジュール。
- 前記第1スイッチICと前記第2スイッチICは、同じ向きに実装されている、請求項1乃至請求項3のいずれかに記載の高周波モジュール。
- 平衡端子を構成する第1個別端子を前記第1スイッチICに備え、前記平衡端子を構成する第2個別端子を前記第2スイッチICに備え、
前記第1個別端子となる第1パッド電極と該第1パッド電極にワイヤーボンディングで接続される第1ランド電極との距離と、
前記第2個別端子となる前記第2パッド電極と該第2パッド電極にワイヤーボンディングで接続される第2ランド電極との距離とは、略等しい、請求項4に記載の高周波モジュール。 - 前記第1スイッチICの第3パッド電極と前記第2スイッチICの第4パッド電極とは、略重なり合うように配置されており、
前記第1スイッチICの第3パッド電極と前記第2スイッチICの第4パッド電極とは、同じ第3ランド電極に接続されており、
前記第3パッド電極と前記第3ランド電極とを接続するワイヤーが前記第3ランド電極に接続する位置は、
前記第4パッド電極と前記第3ランド電極とを接続するワイヤーが前記第3ランド電極に接続する位置よりも、前記第1、第2スイッチICの前記基板への実装位置から離間している、請求項4または請求項5に記載の高周波モジュール。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012137437A JP5257722B2 (ja) | 2011-10-17 | 2012-06-19 | 高周波モジュール |
CN201280010496.XA CN103403866B (zh) | 2011-10-17 | 2012-08-02 | 高频模块 |
PCT/JP2012/069652 WO2013058000A1 (ja) | 2011-10-17 | 2012-08-02 | 高周波モジュール |
TW101129167A TWI559489B (zh) | 2011-10-17 | 2012-08-13 | High frequency module |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011228050 | 2011-10-17 | ||
JP2011228050 | 2011-10-17 | ||
JP2012137437A JP5257722B2 (ja) | 2011-10-17 | 2012-06-19 | 高周波モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013102120A JP2013102120A (ja) | 2013-05-23 |
JP5257722B2 true JP5257722B2 (ja) | 2013-08-07 |
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ID=48140657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2012137437A Expired - Fee Related JP5257722B2 (ja) | 2011-10-17 | 2012-06-19 | 高周波モジュール |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP5257722B2 (ja) |
CN (1) | CN103403866B (ja) |
TW (1) | TWI559489B (ja) |
WO (1) | WO2013058000A1 (ja) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180426B1 (en) * | 1999-03-01 | 2001-01-30 | Mou-Shiung Lin | High performance sub-system design and assembly |
JP3913481B2 (ja) * | 2001-01-24 | 2007-05-09 | シャープ株式会社 | 半導体装置および半導体装置の製造方法 |
JP2005079421A (ja) * | 2003-09-02 | 2005-03-24 | Mitsubishi Electric Corp | 半導体スイッチ |
JP4185499B2 (ja) * | 2005-02-18 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
TWI327369B (en) * | 2006-08-07 | 2010-07-11 | Chipmos Technologies Inc | Multichip stack package |
JP5595314B2 (ja) * | 2011-03-22 | 2014-09-24 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2012
- 2012-06-19 JP JP2012137437A patent/JP5257722B2/ja not_active Expired - Fee Related
- 2012-08-02 WO PCT/JP2012/069652 patent/WO2013058000A1/ja active Application Filing
- 2012-08-02 CN CN201280010496.XA patent/CN103403866B/zh not_active Expired - Fee Related
- 2012-08-13 TW TW101129167A patent/TWI559489B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN103403866A (zh) | 2013-11-20 |
TW201318131A (zh) | 2013-05-01 |
TWI559489B (zh) | 2016-11-21 |
JP2013102120A (ja) | 2013-05-23 |
CN103403866B (zh) | 2015-04-08 |
WO2013058000A1 (ja) | 2013-04-25 |
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