WO2000005933A1 - Carte a circuit imprime et procede de fabrication correspondant - Google Patents
Carte a circuit imprime et procede de fabrication correspondant Download PDFInfo
- Publication number
- WO2000005933A1 WO2000005933A1 PCT/JP1999/003898 JP9903898W WO0005933A1 WO 2000005933 A1 WO2000005933 A1 WO 2000005933A1 JP 9903898 W JP9903898 W JP 9903898W WO 0005933 A1 WO0005933 A1 WO 0005933A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductor pattern
- substrate
- wiring board
- width
- printed wiring
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Definitions
- the present invention relates to a printed wiring board and a method for manufacturing the same, and more particularly, to a printed wiring board having a conductor pattern having excellent adhesion strength and a method for manufacturing the same.
- the printed wiring board 9 includes an insulating substrate 2, a plurality of conductor patterns 93 provided on the substrate 2, and an insulating protective film 94 covering these.
- the conductor pattern 93 is used as wiring and external terminals.
- the bottom surface 9 31 of the conductor pattern 93 is in close contact with the surface of the substrate 2.
- the width a of the bottom surface 931 is equal to the width b of the top surface 932 of the conductor pattern 3. That is, the cross section of the conductor pattern 93 is rectangular.
- the side surface 935 of the conductor pattern 93 is completely covered with the protective film 94.
- the conductor pattern 93 is formed after forming the protective film 94 on the substrate 2.
- the cross section of the conventional conductor pattern 93 is a rectangle in which the width a of the bottom surface 931 is equal to the width b of the top surface 932, the area of the contact portion between the conductor pattern 93 and the substrate 2 is relatively small. small. Therefore, the adhesion strength between substrate 2 and conductive pattern 93 is relatively low. Therefore, as shown in FIG. 5 (B), when external force such as thermal stress is applied to the printed wiring board 9, the conductor pattern 93 may be separated from the surface of the substrate 2.
- the cross-sectional shape of the conductor pattern 93 may be formed in a trapezoid where the width a of the bottom surface 931 is larger than the width b of the top surface 932. Conceivable.
- the material forming the conductor pattern 93 pushes up the protective film 94 having a shape corresponding to the conductor pattern 93. Therefore, as shown in FIG. 6 (B), there was a possibility that the protective film 94 was peeled off from the surface of the substrate 2. Also, as shown in Fig.
- the conductor pattern 93 is formed so that the solder ball 96 can enter between the side surface 935 of the conductor pattern 93 and the protective film 94. It is conceivable to completely expose the sides 9 3 5. In this case, the solder balls 96 contact the substrate 2 having relatively low mechanical strength. Due to the surface tension of the solder balls, the contact area between the solder balls 96 and the substrate 2 is very small. Therefore, when a lateral force as shown by an arrow acts on the solder ball 96, the force acts intensively on the contact portion of the substrate 2. As a result, a crack 99 is generated in the substrate 2 and the substrate 2 may be broken. Disclosure of the invention
- An object of the present invention is to provide a printed wiring board which has strong adhesion between a substrate and a conductor pattern and can prevent damage to the substrate, and a method for manufacturing the same.
- a printed wiring board includes a substrate, a conductor pattern formed on the substrate, and a protective film that covers the substrate and the conductor pattern.
- the conductor pattern has a bottom surface in contact with the substrate, an upper surface opposite to the bottom surface, and a pair of side surfaces. Each side surface has a lower side surface covered with a protective film and an upper side surface exposed from the protective film. The width of the bottom surface is larger than the width of the top surface.
- the width of the bottom of the conductor pattern is larger than the width of the top, and the lower side is covered with a protective film.
- the upper side surface is exposed from the protective film.
- the width of the bottom surface of the conductor pattern is larger than the width of the upper surface, and the area of the portion closely contacting the substrate is relatively large. Therefore, the adhesion strength of the conductor pattern to the substrate is improved as compared with the conductor pattern having a rectangular cross section. Therefore, peeling of the conductor pattern from the surface of the substrate is prevented.
- the upper side surface of the conductor pattern is exposed from the protective film. Therefore, when, for example, solder balls are joined to the conductor pattern, the solder balls penetrate into the upper side surface of the conductor pattern. Therefore, even if a lateral force acts on the solder ball after bonding, the solder ball has a portion that is hooked on the upper side surface, so that peeling of the solder ball from the conductor pattern is prevented.
- the lower side surface of the conductor pattern is covered with a protective film. Therefore, for example, the solder ball does not contact the substrate, but contacts the conductor pattern having higher mechanical strength than the substrate. Therefore, even if a lateral force acts on the solder ball after bonding, the force acts on the conductor pattern and does not act on the substrate, so that damage such as cracks on the substrate is prevented.
- the upper surface and the upper side surface of the conductor pattern are covered with a plating. In this case, the solder balls are easily joined to the conductor pattern.
- solder ball is in contact with the conductor pattern on the upper side surface of the conductor pattern. In this case, even if a lateral force is applied to the joined solder balls, the solder balls are in contact with the side surfaces of the conductive pattern, so that peeling of the solder balls from the conductive pattern is prevented. .
- a method for manufacturing a printed wiring board includes a step of forming a conductor pattern by etching a substrate having a conductor, a step of applying a protective film on the conductor pattern and the substrate, and a step of removing a part of the protective film. including.
- the conductor pattern is formed such that the width of the bottom surface in contact with the substrate is larger than the width of the upper surface opposite to the bottom surface.
- the removing step the upper part of the conductor pattern is exposed.
- the conductor pattern is formed before forming the protective film. Therefore, since the protective film does not exist when the conductive pattern is formed, the conductive pattern does not push up the protective film.
- FIG. 1 is a sectional view showing a printed wiring board according to a first embodiment of the present invention.
- 2 (A) to 2 (E) are views showing a manufacturing process of the printed wiring board according to the first embodiment.
- FIG. 3 is a sectional view showing a printed wiring board according to a second embodiment.
- 4 (A) to 4 (E) are views showing the manufacturing process of the printed wiring board of FIG.
- FIG. 5A is a cross-sectional view showing a first conventional printed wiring board.
- FIG. 5 (B) is a view showing a state where the conductor pattern has been peeled off from the printed wiring board of FIG. 5 (A).
- FIG. 6A is a cross-sectional view showing a second conventional printed wiring board.
- FIG. 6 (B) is a view showing a state where the solder resist has been peeled off from the printed wiring board of FIG. 6 (A).
- FIG. 6 (C) is a view showing a state where the conductor pattern is short-circuited in the printed wiring board of FIG. 6 (A).
- FIG. 7 (A) is a view showing a state in which solder balls have been peeled off from a printed wiring board of a third conventional example.
- FIG. 7B is a diagram showing a state in which the substrate is cracked in the fourth conventional printed wiring board.
- the printed wiring board 1 includes an insulating substrate 2, a conductive pattern 3 formed on the substrate 2, and an insulating protective film or a solder resist 4 covering the substrate 2 and the conductive pattern 3.
- the conductor pattern 3 extends in a direction orthogonal to the paper surface. As shown in FIG. 1, the conductor pattern 3 has an upper part 32 and a lower part 31.
- the bottom surface 3 10 of the conductor pattern 3 is in close contact with the surface of the substrate 2.
- the width c of the bottom surface 310 is larger than the width d of the top surface 320. Therefore, the cross-sectional shape orthogonal to the longitudinal direction of the conductor pattern 3 is a trapezoid.
- the side surface 3 15 of the lower portion 31 is covered with the solder resist 4.
- the side surface 3 25 of the upper portion 32 is not covered with the solder resist 4.
- the height h of the lower part 31 is 95% of the height p of the conductor pattern. 5% of the remaining conductor pattern height p is the height of the upper part 32.
- the upper surface 32 0 and the side surface 3 25 of the upper portion 32 are covered with a plating 5 for connection terminals. Further, the solder ball 6 is joined to the conductor pattern 3 via the plating 5. The solder ball 6 is locked on the side surface 3 25 of the upper portion 32.
- the material of the substrate 2 is preferably glass epoxy.
- the printed wiring board 1 is manufactured from a copper-clad laminate in which a copper foil is pasted on a substrate 2.
- the copper-clad laminate is etched to form a plurality of conductor patterns 3 on the substrate 2.
- the cross section of the conductor pattern 3 is formed in a trapezoid in which the width c of the bottom surface 310 is larger than the width d of the top surface 320.
- the width c of the bottom surface 310 is preferably 30 to 200 ⁇ , and the width d of the top surface 320 is preferably 10 to: L 800 im.
- the width c of the bottom surface 310 is 80 ⁇
- the width d of the top surface 320 is 70 ⁇ m
- the height p of the conductor pattern 3 is 35 ⁇ m. is there.
- a dark resist 4 is applied so as to cover the entirety of the conductor pattern 3 and the substrate 2.
- the height of the resist 4 is substantially constant, that is, the surface 41 is flat.
- the solder resist 4 is applied.
- the surface 41 of the solder resist 4 is irradiated with a laser, and the solder resist 4 is removed along the conductor pattern 3 as shown in FIG. 2 (C). Laser irradiation is stopped when 5% of the height p of the conductor pattern 3 is exposed. By laser irradiation, the upper part 32, that is, the upper surface 320 and the upper side surface 325 are exposed from the opening 40 of the solder resist 4. At this time, the height h of the lower part 31 of the conductor pattern 3 is about 33 ⁇ m.
- a plating process is performed on a predetermined conductor pattern 3.
- the upper portion 32 of the predetermined conductor pattern 3 is covered with the plating 5 for the connection terminal.
- a metal such as copper, gold or nickel can be used.
- solder is supplied onto the plating 5, and the solder is heated and melted.
- the solder balls 6 are joined to the upper portions 32 of the conductor patterns 3 via the plating 5 as shown in FIG. 2 (E).
- the solder ball 6 has a locking portion 63 hooked on both side surfaces 3 25 of the upper portion 32.
- the uppermost portion of the plating 5 is more preferably formed at a position higher than the surface 41 of the solder resist 4.
- a solder ball or a solder paste for connection is easily joined.
- terminals used in the test for example, a probe or an anisotropic conductive rubber, easily come into contact with the plating 5.
- joining and contact may be difficult.
- the height h of the lower part 31 is preferably 50% or more and less than 100% of the height p of the conductor pattern 3. In this case, the side surfaces 3 15 of the lower portion 31 can be surely covered with the solder resist 4. If the height h of the lower part 31 is less than 50% of the height p of the conductor pattern 3, the side face 315 of the lower part 31 may not be reliably covered with the solder resist 4. . Therefore, for example, The force acting in the lateral direction on the solder ball 6 bonded to the wire 3 is likely to be transmitted to the substrate 2 below the lower part 31, and the substrate 2 may be damaged by cracks or the like.
- the upper portion 32 of the conductor pattern 3 does not exist. In this case, the solder balls 6 are not joined to the conductor pattern 3 with sufficient strength.
- the cross-sectional shape of the conductor pattern 3 is preferably a bilaterally symmetric isosceles trapezoid in terms of ease of manufacturing.
- the value obtained by dividing half the value obtained by subtracting the top surface width from the bottom surface width by the height of the conductor pattern 3 ⁇ (c — d) / 2 ⁇ / p (hereinafter referred to as the value X) is 0 It is preferably set in the range of 1-2.5.
- the contact area between the side surface 3 15 of the lower portion 31 and the solder resist 4 increases.
- the conductor pattern 3 is pressed toward the substrate 2 by the solder resist 4.
- the value X is less than 0.1, the contact area between the side surface 3 15 of the lower portion 31 and the solder resist 4 becomes small.
- the conductor pattern 3 may not be sufficiently pressed toward the substrate 2 by the solder resist 4 in some cases.
- the value X is larger than 2.5, the exposed portion of the conductor pattern 3 decreases, and the connection area between the conductor pattern 3 and the semiconductor component decreases. As a result, the connection strength of the semiconductor component may be reduced.
- the width c of the bottom surface 310 is larger than the width d of the upper surface 320 of the upper portion 32, that is, the cross section of the conductor pattern 3 is It is trapezoidal. Therefore, as compared with the conventional conductor pattern 93 having a rectangular cross section, the conductor pattern 3 adheres to the substrate 2 with a relatively large area. With this shape, the adhesion strength of the conductor pattern 3 to the substrate 2 is improved. As a result, peeling of the conductor pattern 3 from the surface of the substrate 2 is prevented.
- the conductor pattern 3 is formed before the formation of the solder register 4 as shown in FIG. Therefore, as in the conventional example, solder-resist 4 will not be pushed up. Therefore, peeling of the solder resist 4 from the surface of the substrate 2 is prevented. In addition, since a part of the conductor pattern 3 does not penetrate between the bottom surface of the solder resist 4 and the surface of the substrate 2, short circuit between adjacent conductor patterns is also prevented.
- the solder ball 6 can contact the side surface 3 25. Furthermore, since the solder ball 6 has a locking portion 6 3 that hooks on the side surface 3 2 5 of the upper part 32, even if a lateral force is applied to the solder ball 6, the solder ball 6 is separated from the conductor pattern 3. Is prevented.
- solder resist 4 The sides 3 15 of the lower part 31 are covered with the solder resist 4. Therefore, the solder ball 6 does not contact the substrate 2 but contacts the conductor pattern 3 having higher mechanical strength than the substrate 2. Therefore, even if a lateral force is applied to the solder ball 6 after bonding, the force acts on the conductor pattern 3 and does not act on the base 2. For this reason, the occurrence of damage such as cracks in the substrate 2 is prevented.
- the conductor pattern 3 Since the cross section of the conductor pattern 3 is substantially an isosceles trapezoid, the conductor pattern 3 is easily formed.
- the value obtained by dividing half the value obtained by subtracting the width d of the upper surface 320 from the width c of the lower surface 310 by the height p of the conductor pattern 3 X ((c-d) / 2 ⁇ 7 is about 0,14.
- the solder resist 4 can contact the side surface 3 15 of the lower portion 31 with a large area. Therefore, the conductor pattern 3 is firmly pressed down by the solder resist 4. Therefore, the adhesion strength of the conductor pattern 3 to the substrate 2 is further improved.
- side surfaces 3 15 and 3 25 of the conductor pattern 3 are not limited to flat slopes as in the first embodiment, but may be concave curved surfaces.
- the side surface 3 15 of the lower portion 31 is surely covered with the solder resist 4. Therefore, even if a lateral force is applied to the solder ball 6 bonded to the conductor pattern 3, the substrate 2 is not damaged. It is surely prevented.
- the upper part 32 is covered with a plating 5. Thereby, the solder balls 6 are easily joined to the conductor patterns 3.
- the printed wiring board of the second embodiment will be described focusing on the differences from the first embodiment.
- the surface 42 of the solder register 4 has a shape corresponding to the arrangement of the conductor pattern 3.
- the printed wiring board of the second embodiment differs from the first embodiment only in this point.
- each conductor pattern 3 is formed on the substrate 2 by subjecting the copper-clad laminate to etching or the like.
- the width c of the bottom surface 310 of each conductor pattern 3 is larger than the width d of the top surface 320. Therefore, the cross section of each conductor pattern 3 is trapezoidal.
- solder resist 4 as an insulating protective film is applied to the entire surface of the conductor pattern 3 and the substrate 2. At this time, since the solder resist 4 is applied so that its thickness is substantially constant, the surface 42 of the solder resist 4 becomes wavy according to the arrangement of the conductor pattern 3.
- the surface 41 of the solder resist 4 is irradiated with a laser beam, and the solder resist 4 is removed along the conductor pattern 3 as shown in FIG. 4 (C). Laser irradiation is stopped when 5% of the height p of the conductor pattern 3 is exposed. As a result, the upper portion 32 of the conductor pattern 3, that is, the upper surface 320 and the side surface 325 are exposed from the opening 40 of the solder resist 4. At this time, the height h of the lower part 31 of the conductor pattern 3 is 95% of the height p of the conductor pattern 3.
- the plating process is performed on the predetermined conductor pattern 3.
- the plating 5 for the connection terminal covers the upper part 32 of the predetermined conductor pattern 3.
- solder is supplied onto the plating 5, and the solder is heated and melted.
- the solder balls 6 become the conductor pattern 3 as shown in Fig. 4 (E).
- the upper part 32 is joined to the upper part 32 via a hook 5.
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69935009T DE69935009T2 (de) | 1998-07-22 | 1999-07-21 | Gedruckte leiterplatte und deren herstellungsverfahren |
EP99931459A EP1143776B1 (en) | 1998-07-22 | 1999-07-21 | Printed-circuit board and method of manufacture thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10/206189 | 1998-07-22 | ||
JP20618998A JP4066522B2 (ja) | 1998-07-22 | 1998-07-22 | プリント配線板 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000005933A1 true WO2000005933A1 (fr) | 2000-02-03 |
Family
ID=16519294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1999/003898 WO2000005933A1 (fr) | 1998-07-22 | 1999-07-21 | Carte a circuit imprime et procede de fabrication correspondant |
Country Status (6)
Country | Link |
---|---|
US (1) | US6809415B2 (ja) |
EP (1) | EP1143776B1 (ja) |
JP (1) | JP4066522B2 (ja) |
KR (1) | KR100385422B1 (ja) |
DE (1) | DE69935009T2 (ja) |
WO (1) | WO2000005933A1 (ja) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100396787B1 (ko) * | 2001-11-13 | 2003-09-02 | 엘지전자 주식회사 | 반도체 패키지용 인쇄회로기판의 와이어 본딩패드 형성방법 |
JP2004066017A (ja) * | 2002-08-01 | 2004-03-04 | Nippon Paint Co Ltd | ソルダーレジスト膜の形成方法 |
US7012050B2 (en) * | 2002-12-06 | 2006-03-14 | Colgate-Palmolive Company | Skin cleansing composition comprising a quaternized lanolin |
CN1326432C (zh) * | 2002-12-23 | 2007-07-11 | 矽统科技股份有限公司 | 无焊垫设计的高密度电路板及其制造方法 |
US7081209B2 (en) * | 2003-07-09 | 2006-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Solder mask removal method |
US7307222B2 (en) * | 2003-09-24 | 2007-12-11 | Agilent Technologies, Inc. | Printed circuit board test access point structures and method for making the same |
JP2005183464A (ja) * | 2003-12-16 | 2005-07-07 | Nitto Denko Corp | 配線回路基板 |
WO2005076683A1 (ja) | 2004-02-04 | 2005-08-18 | Ibiden Co., Ltd. | 多層プリント配線板 |
TWI231028B (en) * | 2004-05-21 | 2005-04-11 | Via Tech Inc | A substrate used for fine-pitch semiconductor package and a method of the same |
JP4351129B2 (ja) * | 2004-09-01 | 2009-10-28 | 日東電工株式会社 | 配線回路基板 |
US7626829B2 (en) * | 2004-10-27 | 2009-12-01 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
JP4955263B2 (ja) * | 2004-12-15 | 2012-06-20 | イビデン株式会社 | プリント配線板 |
GB0505826D0 (en) * | 2005-03-22 | 2005-04-27 | Uni Microelektronica Ct Vsw | Methods for embedding of conducting material and devices resulting from said methods |
JP4738971B2 (ja) * | 2005-10-14 | 2011-08-03 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP2007317852A (ja) * | 2006-05-25 | 2007-12-06 | Fujikura Ltd | プリント配線板及び基板間接続構造 |
US7964800B2 (en) | 2006-05-25 | 2011-06-21 | Fujikura Ltd. | Printed wiring board, method for forming the printed wiring board, and board interconnection structure |
JP5072283B2 (ja) * | 2006-07-31 | 2012-11-14 | 三洋電機株式会社 | 回路基板 |
TWI320680B (en) * | 2007-03-07 | 2010-02-11 | Phoenix Prec Technology Corp | Circuit board structure and fabrication method thereof |
JP5227531B2 (ja) * | 2007-03-30 | 2013-07-03 | 日本発條株式会社 | ディスク装置用サスペンション |
US8709934B2 (en) * | 2007-06-05 | 2014-04-29 | Stats Chippac Ltd. | Electronic system with vertical intermetallic compound |
TWI340614B (en) * | 2007-08-03 | 2011-04-11 | Unimicron Technology Corp | Circuit board and method of fabricating the same |
KR100951449B1 (ko) * | 2008-01-03 | 2010-04-07 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US8058726B1 (en) * | 2008-05-07 | 2011-11-15 | Amkor Technology, Inc. | Semiconductor device having redistribution layer |
US20100032194A1 (en) * | 2008-08-08 | 2010-02-11 | Ibiden Co., Ltd. | Printed wiring board, manufacturing method for printed wiring board and electronic device |
JP5426122B2 (ja) * | 2008-08-21 | 2014-02-26 | セイコーインスツル株式会社 | 回路基板 |
US8686300B2 (en) * | 2008-12-24 | 2014-04-01 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
JP5360221B2 (ja) * | 2009-09-16 | 2013-12-04 | 株式会社村田製作所 | 電子部品内蔵モジュール |
US8528200B2 (en) * | 2009-12-18 | 2013-09-10 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
US8755196B2 (en) * | 2010-07-09 | 2014-06-17 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP2012142557A (ja) * | 2010-12-15 | 2012-07-26 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
US9449933B2 (en) | 2012-03-29 | 2016-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packaging device and method of making the same |
US8664090B1 (en) | 2012-04-16 | 2014-03-04 | Amkor Technology, Inc. | Electronic component package fabrication method |
JP2013229491A (ja) * | 2012-04-26 | 2013-11-07 | Kyocera Corp | 電極構造、半導体素子、半導体装置、サーマルヘッドおよびサーマルプリンタ |
JP5341227B1 (ja) * | 2012-05-16 | 2013-11-13 | 日本特殊陶業株式会社 | 配線基板 |
JP5410580B1 (ja) * | 2012-08-09 | 2014-02-05 | 日本特殊陶業株式会社 | 配線基板 |
TWI536508B (zh) * | 2012-08-24 | 2016-06-01 | Ngk Spark Plug Co | Wiring board |
US9245862B1 (en) | 2013-02-12 | 2016-01-26 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US9412702B2 (en) | 2013-03-14 | 2016-08-09 | Intel Corporation | Laser die backside film removal for integrated circuit (IC) packaging |
US8975177B2 (en) * | 2013-03-14 | 2015-03-10 | Intel Corporation | Laser resist removal for integrated circuit (IC) packaging |
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JP6368657B2 (ja) * | 2015-02-02 | 2018-08-01 | 日本発條株式会社 | 金属ベース回路基板及びその製造方法 |
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US10446515B2 (en) | 2017-03-06 | 2019-10-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate and semiconductor packaging device, and method for forming the same |
US10381296B2 (en) * | 2017-03-06 | 2019-08-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and a method of manufacturing the same |
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JP2020161728A (ja) * | 2019-03-27 | 2020-10-01 | イビデン株式会社 | 配線基板 |
JP2020188209A (ja) * | 2019-05-16 | 2020-11-19 | イビデン株式会社 | プリント配線板とプリント配線板の製造方法 |
JP2022133504A (ja) * | 2021-03-02 | 2022-09-14 | イビデン株式会社 | プリント配線板 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04348587A (ja) * | 1991-05-27 | 1992-12-03 | Matsushita Electric Ind Co Ltd | 回路基板およびその製造方法 |
JPH05206209A (ja) * | 1991-07-26 | 1993-08-13 | Internatl Business Mach Corp <Ibm> | はんだ量の増加方法、プリント回路デバイス、及びはんだ容積の増大方法 |
JPH08181423A (ja) * | 1994-12-27 | 1996-07-12 | Nippon Telegr & Teleph Corp <Ntt> | はんだバンプ実装用端子電極構造 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4289834A (en) * | 1977-10-20 | 1981-09-15 | Ibm Corporation | Dense dry etched multi-level metallurgy with non-overlapped vias |
JPS5828846A (ja) * | 1981-08-14 | 1983-02-19 | Nec Corp | ボンデイング端子電極 |
JPS60234982A (ja) * | 1984-05-09 | 1985-11-21 | Alps Electric Co Ltd | パタ−ン形成方法 |
JPS6292453A (ja) * | 1985-10-18 | 1987-04-27 | Fuji Electric Co Ltd | 半導体装置の製造方法 |
US5207103A (en) * | 1987-06-01 | 1993-05-04 | Wise Kensall D | Ultraminiature single-crystal sensor with movable member |
JPH0666290B2 (ja) * | 1987-12-29 | 1994-08-24 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH01238132A (ja) * | 1988-03-18 | 1989-09-22 | Oki Electric Ind Co Ltd | 半田接続用電極及び半田接続用電極の製造方法 |
JPH03153049A (ja) * | 1989-11-10 | 1991-07-01 | Fujitsu Ltd | 半導体装置 |
JP2764632B2 (ja) | 1990-04-09 | 1998-06-11 | イビデン株式会社 | 電子回路基板とその製造方法 |
JPH0529363A (ja) * | 1991-07-22 | 1993-02-05 | Sony Corp | 配線基板 |
JP3141364B2 (ja) * | 1992-05-06 | 2001-03-05 | 住友電気工業株式会社 | 半導体チップ |
JPH05327179A (ja) | 1992-05-15 | 1993-12-10 | Sony Corp | プリント配線基板の製造方法 |
US5609704A (en) * | 1993-09-21 | 1997-03-11 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating an electronic part by intaglio printing |
JP3578232B2 (ja) * | 1994-04-07 | 2004-10-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電気接点形成方法、該電気接点を含むプローブ構造および装置 |
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
JPH08125341A (ja) * | 1994-10-25 | 1996-05-17 | Hitachi Ltd | 電子回路装置 |
JP3291950B2 (ja) | 1994-12-28 | 2002-06-17 | 日産自動車株式会社 | 設計支援装置 |
US5597469A (en) * | 1995-02-13 | 1997-01-28 | International Business Machines Corporation | Process for selective application of solder to circuit packages |
JP2671851B2 (ja) * | 1995-02-21 | 1997-11-05 | 日本電気株式会社 | プリント配線板の製造方法 |
US5634268A (en) * | 1995-06-07 | 1997-06-03 | International Business Machines Corporation | Method for making direct chip attach circuit card |
US5886877A (en) * | 1995-10-13 | 1999-03-23 | Meiko Electronics Co., Ltd. | Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board |
US5801689A (en) | 1996-01-22 | 1998-09-01 | Extended Systems, Inc. | Hypertext based remote graphic user interface control system |
KR100216839B1 (ko) * | 1996-04-01 | 1999-09-01 | 김규현 | Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조 |
US5796169A (en) * | 1996-11-19 | 1998-08-18 | International Business Machines Corporation | Structurally reinforced ball grid array semiconductor package and systems |
US5929521A (en) * | 1997-03-26 | 1999-07-27 | Micron Technology, Inc. | Projected contact structure for bumped semiconductor device and resulting articles and assemblies |
JPH10270624A (ja) * | 1997-03-27 | 1998-10-09 | Toshiba Corp | チップサイズパッケージ及びその製造方法 |
JP3346263B2 (ja) * | 1997-04-11 | 2002-11-18 | イビデン株式会社 | プリント配線板及びその製造方法 |
US6335571B1 (en) * | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
JP3446825B2 (ja) * | 1999-04-06 | 2003-09-16 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
-
1998
- 1998-07-22 JP JP20618998A patent/JP4066522B2/ja not_active Expired - Fee Related
-
1999
- 1999-07-21 WO PCT/JP1999/003898 patent/WO2000005933A1/ja active IP Right Grant
- 1999-07-21 KR KR10-2000-7011431A patent/KR100385422B1/ko not_active IP Right Cessation
- 1999-07-21 DE DE69935009T patent/DE69935009T2/de not_active Expired - Lifetime
- 1999-07-21 EP EP99931459A patent/EP1143776B1/en not_active Expired - Lifetime
-
2000
- 2000-12-19 US US09/740,424 patent/US6809415B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04348587A (ja) * | 1991-05-27 | 1992-12-03 | Matsushita Electric Ind Co Ltd | 回路基板およびその製造方法 |
JPH05206209A (ja) * | 1991-07-26 | 1993-08-13 | Internatl Business Mach Corp <Ibm> | はんだ量の増加方法、プリント回路デバイス、及びはんだ容積の増大方法 |
JPH08181423A (ja) * | 1994-12-27 | 1996-07-12 | Nippon Telegr & Teleph Corp <Ntt> | はんだバンプ実装用端子電極構造 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1143776A4 * |
Also Published As
Publication number | Publication date |
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DE69935009D1 (de) | 2007-03-15 |
KR100385422B1 (ko) | 2003-05-27 |
EP1143776A4 (en) | 2006-05-03 |
JP2000040868A (ja) | 2000-02-08 |
JP4066522B2 (ja) | 2008-03-26 |
DE69935009T2 (de) | 2007-08-23 |
KR20010042711A (ko) | 2001-05-25 |
EP1143776B1 (en) | 2007-01-24 |
EP1143776A1 (en) | 2001-10-10 |
US20010002728A1 (en) | 2001-06-07 |
US6809415B2 (en) | 2004-10-26 |
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