TWI536508B - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
TWI536508B
TWI536508B TW102129999A TW102129999A TWI536508B TW I536508 B TWI536508 B TW I536508B TW 102129999 A TW102129999 A TW 102129999A TW 102129999 A TW102129999 A TW 102129999A TW I536508 B TWI536508 B TW I536508B
Authority
TW
Taiwan
Prior art keywords
insulating layer
wiring board
underfill
point
connection terminal
Prior art date
Application number
TW102129999A
Other languages
English (en)
Other versions
TW201419459A (zh
Inventor
Tomohiro Nishida
Seiji Mori
Makoto Wakazono
Original Assignee
Ngk Spark Plug Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2012258208A external-priority patent/JP5491605B1/ja
Application filed by Ngk Spark Plug Co filed Critical Ngk Spark Plug Co
Publication of TW201419459A publication Critical patent/TW201419459A/zh
Application granted granted Critical
Publication of TWI536508B publication Critical patent/TWI536508B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09018—Rigid curved substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0594—Insulating resist or coating with special shaped edges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description

配線基板
本發明係關於配線基板。
周知有一種能安裝半導體晶片之配線基板(例如，參照專利文獻1、2)。此種配線基板上形成有構成為能與半導體晶片連接之連接端子。
專利文獻1記載有，為了防止因電鍍材料而造成之連接端子間的電性短路，形成具有露出複數個連接端子之開口的絕緣層，並於此開口中之複數個連接端子之間形成絕緣層，然後對複數個連接端子實施電鍍。專利文獻2記載有，為了防止因銲料而造成之連接端子間的電性短路，將形成於連接端子間的絕緣層作成薄於連接端子之厚度以下。
於對配線基板安裝半導體晶片時，配線基板之連接端子被銲接於半導體晶片上，並於連接端子周圍之配線基板與半導體晶片的間隙內填充有被稱為底部填充膠的液狀硬化性樹脂(例如，參照專利文獻3)。
專利文獻
專利文獻1 日本特開2007-103648號公報
專利文獻2 日本特開2011-192692號公報
專利文獻3 日本特開2010-153495號公報
專利文獻1、2中，針對防止因電鍍或銲料而造成之連接端子間的短路進行了考量，但對連接端子周圍之底部填充膠的填充卻沒有足夠的考量，存在底部填充膠的流動受到阻礙，進而有因底部填充膠之填充不良而形成孔洞(空洞)的情況之課題。專利文獻3中，對吸入配線基板與半導體晶片之間隙內之後的底部填充膠之流動亦未充分考量，存在因底部填充膠之填充不良而形成孔洞之情況的課題。
本發明係為了解決上述課題而完成者，其可作為以下之形態實現。
(1)根據本發明之一形態，提供一種配線基板，其具備：絕緣性之基層；絕緣層，其積層於該基層上，且具有形成有開口部之第一表面、及於該開口部之內側相對於該第一表面朝該基層側凹陷的第二表面；及導電性之連接端子，其於該開口部之內側自該絕緣層突出。於此配線基板中，該第二表面係於該開口部之內側自該第一表面形成至該連接端子，且於沿對該基層積層有該絕緣層之積層方向的平面、亦即截面中，自該第二表面之任意點朝向該絕緣層外側之法線、與自該任意點與該第一表面平行地朝向該連接端子之平行線所夾之角度係大於0度、小於90度。根據該形態之配線基板，藉由於第二表面之各部分將底部填充膠的液流朝連接端子側引導，可穩定地使底部填充膠流動。結果能抑制因底部填充膠之填充不良而造成的孔洞的形成。
(2)於上述形態之配線基板中，該第二表面也可由曲面構成。根據該形態之配線基板，與第二表面由平面所構成之情況相比，可增加與底部填充膠接觸之第二表面的表面積，因此可提高第二表面與底部填充膠之密接性。此外，與第二表面由平面所構成之情況相比，隨著底部填充膠的硬化而產生的絕緣層之應力得以降低，因此可抑制絕緣層中之裂痕(裂縫)的產生。
(3)於上述形態之配線基板中，該第二表面也可由平面構成。根據該形態之配線基板，與第二表面由曲面所構成之情況相比，可縮短底部填充膠流動於第二表面上的距離，因此可縮短底部填充膠之填充所需的時間。
(4)於上述形態之配線基板中，該第二表面之表面粗度也可大於該第一表面。根據該形態之配線基板，不會阻礙底部填充膠之流動性，可利用毛細管現象使底部填充膠遍布於第二表面上之各部分。
本發明也可於配線基板以外之各種形態中實現。例如，能以具備配線基板之裝置、製造配線基板的製造方法等的形態實現。
10,10B,10,10D‧‧‧配線基板
20‧‧‧半導體晶片
30‧‧‧底部填充膠
120‧‧‧基層
130‧‧‧導體層
132‧‧‧連接端子
136‧‧‧內部配線
140‧‧‧絕緣層
141‧‧‧第一表面
142‧‧‧第二表面
150‧‧‧開口部
232‧‧‧連接端子
SD‧‧‧銲料
P1‧‧‧連接點
P2‧‧‧連接點
MP‧‧‧中間點
AP‧‧‧任意點
NL‧‧‧法線
PL‧‧‧平行線
第1圖為顯示第一實施形態之配線基板的構成之局部剖面示意圖。
第2為顯示安裝了半導體晶片之配線基板的構成之局部剖面示意圖。
第3圖為顯示第二實施形態之配線基板的構成之局部剖面示意圖。
第4圖為顯示第三實施形態之配線基板的構成之局部剖面示意圖。
第5圖為顯示第四實施形態之配線基板的構成之局部剖面示意圖。
A.第一實施形態
第1圖為顯示第一實施形態之配線基板10的構成之局部剖面示意圖。第2為顯示安裝了半導體晶片20之配線基板10的構成之局部剖面示意圖。配線基板10係使用有機材料所形成，是亦被稱為有機基板(organic substrate)之板狀構件。本實施形態中，如第2圖所示，配線基板10係構成為能安裝半導體晶片20之覆晶晶片安裝基板。
配線基板10具備基層120、導體層130及絕緣層140。本實施形態中，配線基板10係於基層120上形成導體層130之後，再於導體層130上形成絕緣層140。其他實施形態中，配線基板10可具有於基層120上交互地積層複數層導體層及複數層絕緣層之多層構造，也可於基層120之兩面分別具有此種多層構造。
第1圖圖示了相互正交之XYZ軸。第1圖之XYZ軸係與其他圖中之XYZ軸對應。將第1圖之XYZ軸中的沿絕緣層140相對於基層120積層之積層方向的 軸作為Z軸。並將沿Z軸之Z軸方向中的自基層120朝絕緣層140的方向作為+Z軸方向，將+Z軸方向之反方向作為-Z軸方向。將第1圖之XYZ軸中的沿與Z軸正交之層面方向的2個軸作為X軸及Y軸。第1圖之說明中，將沿X軸之X軸方向中的自紙面左側朝紙面右側的方向作為+X軸方向，將+X軸方向之反方向作為-X軸方向。第1圖之說明中，將沿Y軸之Y軸方向中的自紙面前面側朝紙面裏面側的方向作為+Y軸方向，將+Y軸方向之反方向作為-Y軸方向。
配線基板10之基層120係由絕緣性材料構成的板狀構件。本實施形態中，基層120之絕緣性材料係熱硬化性樹脂(例如，雙馬來醯亞胺-三嗪樹脂(Bismaleimide-Triazine Resin，BT)、環氧樹脂等)。其他實施形態中，基層120之絕緣性材料也可為纖維強化樹脂(例如，玻璃纖維強化環氧樹脂等)。第1及第2圖中雖未圖示，於基層120之內部還形成有構成連接於導體層130之配線的一部分之導體(例如，貫通孔(through hole)、通孔(via)等)。
配線基板10之導體層130係由形成於基層120上之導電性材料所構成的導體圖案。本實施形態中，導體層130係藉由將形成於基層120之表面上的鍍銅層蝕刻成所需之形狀而形成。導體層130包含露出於絕緣層140之連接端子132、及由絕緣層140所被覆的內部配線136。
如第2圖所示，導體層130之連接端子132係構成為經由銲料SD而可與半導體晶片20的連接端子232連接。本實施形態中，於連接端子132之表面實施了電鍍。
配線基板10之絕緣層140係由也稱為抗銲劑之絕緣性材料所構成的層。絕緣層140具有第一表面141及第二表面142。
絕緣層140之第一表面141係形成有開口部150之絕緣層140的表面。本實施形態中，第一表面141係沿X軸及Y軸且朝向+Z軸方向側的面，其構成絕緣層140之+Z軸方向側的表面。
絕緣層140之第二表面142係於開口部150之內側相對於第一表面141朝基層120側凹陷的絕緣層140之表面。導體層130之連接端子132露出於第二表面142，本實施形態中，連接端子132係自第二表面142朝+Z軸方向側突出。本實施形態中，於第二表面142設有一個連接端子132。其他實施形態中，也可於第二表面142設置2個以上的連接端子132。
第1圖中之配線基板10的截面係與Z軸及X軸平行的ZX平面。於ZX平面中，第二表面142係自連接於第一表面141的連接點P1形成至連接於連接端子132之連接點P2。
第1圖係於ZX平面上圖示有點AP、法線NL、平行線PL及角度θ。點AP係構成涵蓋自連接點P1至連接點P2間的第二表面142上之任意點。法線NL係 與第二表面142上的任意點AP的切線垂直的線段，是自任意點AP朝向絕緣層140之外側(+Z軸方向)的線段。平行線PL係自任意點AP與第一表面141平行地朝向連接端子132的線段。本實施形態中，平行線PL係沿X軸之線段。於ZX平面上，第二表面142上之任意點AP上的法線NL與平行線PL所構成之角度θ，係大於0度、小於90度。
本實施形態中，第二表面142係由曲面構成。本實施形態中，第二表面142中之第一表面141側係由朝向絕緣層140之外側(+Z軸方向)凸起的凸狀曲面所構成，第二表面142中之連接端子132側係由朝向絕緣層140之內側(-Z軸方向)凹陷的凹狀曲面所構成。
本實施形態中，第二表面142之表面粗度係大於第一表面141。本實施形態中，第二表面142之中心線平均粗度Ra為0.06~0.8μm(微米)，第二表面142之十點平均粗度Rz為1.0~9.0μm。相對於此種第二表面142之表面粗度，第一表面141之中心線平均粗度Ra為0.02~0.25μm，第一表面141之十點平均粗度Rz為0.6~5.0μm。
本實施形態中，絕緣層140係於形成有導體層130之基層120上塗布光硬化型絕緣性樹脂之後，經由曝光、顯像而形成。絕緣層140中之開口部150相當於曝光時被遮蔽之部分，藉由顯像時對未硬化部分進行沖洗，形成絕緣層140中之第二表面142。如此，絕緣層140中之第一表面141及第二表面142，係作為構成 單一層之部位而一體形成。本實施形態中，第二表面142之形狀及表面粗度，係藉由對光硬化型絕緣性樹脂之材質、曝光時之遮罩的形狀、及曝光時之照射光的強度、照射時間及照射角度等進行調整而加以實現。
如第2圖所示，於將半導體晶片20安裝在配線基板10時，連接端子132係被銲接於半導體晶片20之連接端子232上，並且於形成在開口部150中之第二表面142與半導體晶片20之間的間隙內填充有底部填充膠30。
根據以上說明之第一實施形態，藉由於第二表面142之各部分將底部填充膠30之液流朝連接端子132側引導，可穩定地使底部填充膠30流動。結果能抑制因底部填充膠30的填充不良而造成之孔洞的形成。
此外，由於第二表面142係由曲面所構成，與第二表面142由平面所構成之情況相比，可增加與底部填充膠30接觸之第二表面142的表面積，因此可提高第二表面142與底部填充膠30之密接性。此外，與第二表面142由平面所構成之情況相比，隨著底部填充膠30的硬化而產生的絕緣層140之應力得以降低，因此可抑制絕緣層140中之裂痕的產生。
B.第二實施形態
第3圖為顯示第二實施形態之配線基板10B的構成之局部剖面示意圖。於第二實施形態之說明中，對與第一實施形態相同之構成，賦予相同之符號並省略其說明。
第二實施形態之配線基板10B，除第二表面142之形狀不同外，其餘與第一實施形態相同。第二實施形態之第二表面142，除連接點P1至連接點P2之間由朝向絕緣層140之內側(-Z軸方向)凹陷的凹狀曲面所構成之點外，其餘與第一實施形態相同。第二實施形態中，與第一實施形態相同，於ZX平面上，第二表面142上之任意點AP上的法線NL與平行線PL所構成之角度θ，係大於0度、小於90度。第二實施形態中，隨著任意之點AP的位置自連接點P1向連接點P2移動，角度θ即增大。
根據以上說明之第二實施形態，與第一實施形態相同，能抑制因底部填充膠30的填充不良而造成之孔洞的形成。此外，由於第二表面142係由曲面所構成，與第一實施形態相同，可提高第二表面142與底部填充膠30之密接性。此外，由於第二表面142係由曲面所構成，與第一實施形態相同，能抑制絕緣層140中之裂痕(裂縫)的產生。
C.第三實施形態
第4圖為顯示第三實施形態之配線基板10C的構成之局部剖面示意圖。於第三實施形態之說明中，對與第一實施形態相同之構成，賦予相同之符號並省略其說明。
第三實施形態之配線基板10C，除第二表面142之形狀不同外，其餘與第一實施形態相同。第三實施形態之第二表面142，除由平面所構成外，其餘與第 一實施形態相同。第三實施形態中，第二表面142係由涵蓋連接點P1與連接點P2間之平面所構成。
第三實施形態中，與第一實施形態相同，於ZX平面上，第二表面142上之任意點AP上的法線NL與平行線PL所構成之角度θ，係大於0度、小於90度。第三實施形態中，即使任意之點AP的位置為連接點P1至連接點P2間的任一位置，角度θ也一定
根據以上說明之第三實施形態，與第一實施形態相同，能抑制因底部填充膠30的填充不良而造成之孔洞的形成。此外，與第二表面142係由曲面所構成之情況相比，可縮短底部填充膠30流動於第二表面142上的距離，因此可縮短底部填充膠30之填充所需的時間。
D.第四實施形態
第5圖為顯示第四實施形態之配線基板10D的構成之局部剖面示意圖。於第四實施形態之說明中，對與第一實施形態相同之構成，賦予相同之符號並省略其說明。
第四實施形態之配線基板10D，除第二表面142之形狀不同外，其餘與第一實施形態相同。第四實施形態之第二表面142，除由平面所構成外，其餘與第一實施形態相同。第四實施形態中，第二表面142係由涵蓋連接點P1至中間點MP之平面、及涵蓋中間點MP至連接點P2的平面所構成。中間點MP係第二表面142上位於連接點P1與連接點P2之間的點。
第四實施形態中，與第一實施形態相同，於ZX平面上，第二表面142上之任意點AP上的法線NL與平行線PL所構成之角度θ，係大於0度、小於90度。第四實施形態中，任意之點AP的位置比中間點MP靠近連接點P2側的情況下的角度θ係比任意之點AP的位置比中間點MP靠近連接點P1側的情況下的角度θ大。
根據以上說明之第四實施形態，與第一實施形態相同，能抑制因底部填充膠30的填充不良而造成之孔洞的形成。此外，與第二表面142係由曲面所構成之情況相比，可縮短底部填充膠30流動於第二表面142上的距離，因此可縮短底部填充膠30之填充所需的時間。
E.其他實施形態
本發明不限於上述實施形態、實施例或變化例，於未超出其實質內容之範圍內即能以各種構成實現。例如，為了解決一部分或全部上述課題、或者為了達成一部分或全部上述效果，可適宜地對與發明內容一欄中所記載之各形態中的技術特徵對應之實施形態、實施例、變化例中的技術特徵進行替換、組合。此外，只要其技術特徵於本說明書中未載明為必須的特徵，即可適宜地加以刪除。
只要第二表面142滿足0度<θ<90度的條件，即能以各種形狀加以實現。例如，第二表面142也可為於連接點P1與連接點P2之間具有3個以上之反曲點的曲面。此外，第二表面142也可由連接點P1與連接 點P2之間角度θ的值不同之3個以上的平面所構成。此外，第二表面142也可為曲面與平面組合而成之形狀。
10‧‧‧配線基板
120‧‧‧基層
130‧‧‧導體層
140‧‧‧絕緣層
141‧‧‧第一表面
142‧‧‧第二表面
150‧‧‧開口部
P1‧‧‧連接點
P2‧‧‧連接點
AP‧‧‧任意點
NL‧‧‧法線
PL‧‧‧平行線

Claims (2)

  1. 一種配線基板，其具備：絕緣性之基層；絕緣層，其積層於該基層上，且具有形成有開口部之第一表面、及於該開口部之內側相對於該第一表面朝該基層側凹陷的第二表面；及導電性之連接端子，其於該開口部之內側自該絕緣層突出；該配線基板之特徵為：該第二表面係於該開口部之內側自該第一表面形成至該連接端子，且於沿對該基層積層有該絕緣層之積層方向的平面、亦即截面中，自該第二表面之任意點朝向該絕緣層外側之法線、與自該任意點與該第一表面平行地朝向該連接端子之平行線所夾之角度係大於0度、小於90度，及該第二表面係由曲面構成。
  2. 如申請專利範圍第1項之配線基板，其中該第二表面之表面粗度大於該第一表面。
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