CN104902682A - 配线基板及配线基板的制造方法 - Google Patents
配线基板及配线基板的制造方法 Download PDFInfo
- Publication number
- CN104902682A CN104902682A CN201510093012.8A CN201510093012A CN104902682A CN 104902682 A CN104902682 A CN 104902682A CN 201510093012 A CN201510093012 A CN 201510093012A CN 104902682 A CN104902682 A CN 104902682A
- Authority
- CN
- China
- Prior art keywords
- hole
- electronic device
- protuberance
- wiring substrate
- electric capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09154—Bevelled, chamferred or tapered edge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10522—Adjacent components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10651—Component having two leads, e.g. resistor, capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
一种配线基板,包含:核层,其内形成有贯穿孔,并具有从所述贯穿孔的内壁向所述贯穿孔的内侧突出的突起部;多个电子器件,其在平面视图中相互分离地并排设置在所述贯穿孔的内部,并具有与所述多个电子器件的并排排列方向相对的侧部,所述侧部与所述突出部卡合;及树脂层,其被填充在所述贯穿孔的内部,并对所述电子器件进行支撑。
Description
技术领域
本发明涉及一种配线基板及配线基板的制造方法。
背景技术
现有技术中存在一种配线板,其具有形成了空腔的基板和设置(容纳)在所述空腔内的电子器件。所述配线板还具有以覆盖所述空腔的开口的方式所形成的绝缘层(例如,参照专利文献1)。
专利文献1:(日本)特开2011-216740号公报
如上所述,现有技术中存在的配线板在1个空腔内部设置了1个电子器件。
然而,如果在1个空腔内部设置多个(本文中,多个指2个以上)电子器件,则例如在将绝缘层填充至空腔内部时,多个电子器件的位置可能会出现偏差。多个电子器件的位置偏差可能会产生由于相互接触而导致短路或难以与配线层等进行良好连接的现象,进而导致出现电气可靠性的问题。
发明内容
所以,本发明的目的在于,提供一种在将多个电子器件配设在1个贯穿孔的内部时可提高电气可靠性的配线基板及配线基板的制造方法。
[用于解决课题的手段]
本发明的一实施方式的配线基板包含:核层,其内形成有贯穿孔,并具有在平面视图中从所述贯穿孔的内壁向所述贯穿孔的内侧突出的突出部;多个电子器件,其在平面视图中以互相分离的状态并排设置在所述贯穿孔的内部,并具有与并排排列方向相对的侧部,所述侧部与所述突出部卡合;及树脂层,其填充在所述贯穿孔的内部,并对所述电子器件的侧部进行支撑。
[发明的效果]
能够提供一种在将多个电子器件配设在1个贯穿孔的内部时可提高电气可靠性的配线基板及配线基板的制造方法。
附图说明
图1A至图1B表示一实施方式的配线基板100的截面图。
图2A至图2C表示核层110的截面图。
图3A至图3C表示在核层110的贯穿孔110H的内部配置了电容芯片200的状态的图。
图4A至图4B表示一实施方式的配线基板100的制造步骤的图。
图5A至图5E表示一实施方式的配线基板100的制造步骤的图。
图6A至图6C表示一实施方式的配线基板100的制造步骤的图。
图7表示在配线基板100上实装了LSI芯片的状态的图。
图8A至图8C表示一实施方式的变形例的核层110X的截面图。
其中,附图标记说明如下:
100 配线基板
110、110X 核层(Core)
110A、110XA1、110XA2 突出部
110A1 顶部
110H、110HX 贯穿孔
111A 配线层
120A、120B 贯穿电极
130A、130B 绝缘层
140A1、140A2、140A3、140A4、140A5、140A6、140B1、140B2、140B3、140B4、140B5、140B6 通孔
150A1、150A2、150A3、150A4、150A5、150A6、150B1、150B2、150B3、150B4、150B5、150B6 配线层
160A、160B 阻焊层
200 电容芯片
具体实施方式
以下对发明的配线基板及配线基板的制造方法的实施方式进行说明。
<实施方式>
图1A至图1B是表示本实施方式的配线基板100的截面图。以下使用作为直角坐标系的一个例子的、包含与配线基板100的表面及里面平行的XY平面的XYZ座标系进行说明。
图1A表示与配线基板100的XZ平面平行的截面;图1B表示与配线基板100的YZ平面平行的截面,其表示的是图1A中从X轴的负方向侧向正方向侧进行观察时的A1-A1截面。
配线基板100包含核层110、配线层111A、贯穿电极120A、120B、绝缘层130A、130B及电容芯片200。
配线基板100还包含通孔140A1、140A2、140A3、140A4、140A5、140A6、140B1、140B2、140B3、140B4、140B5及140B6。
配线基板100还包含配线层150A1、150A2、150A3、150A4、150A5、150A6、150B1、150B2、150B3、150B4、l150B5、150B6及阻焊层160A、160B。
下面,为了便于说明,将图中位于上侧的面称为上表面,并将位于下侧的面称为下表面。另外,为了便于说明,还采用了上方及下方的表现。然而,需要说明的是,这里所说的上表面、下表面、上方、下方、上侧、下侧等,并不是用于表示一般意义的上下关系,仅是用于表示图中的上下关系的用语。
核层110(即、核)例如是用环氧树脂浸渍过的玻璃布基材,并在两面贴附了铜箔,其作为堆积(buildup)基板的核。通过对核层110的上表面所贴附的铜箔进行图案化,可形成配线层111A,另外,通过对下表面所贴附的铜箔通过图案化,还可形成另一配线层。然而,如果核层110的下表面不需要形成配线层,则也可仅在核层110的上表面贴附铜箔。
核层110具有贯穿孔110H。贯穿孔110H沿厚度方向(图1A至图1B中的Z轴方向)贯穿核层110。核层110的贯穿孔110H的内壁具有向贯穿孔110H的内侧突出的突出部110A。关于该突出部110A,将在后面使用图2A至图2C及图3A至图3C对其进行说明。
配线层111A是在核层110的上表面所形成的金属层。配线层111A例如通过对核层110的上表面所贴附的铜箔进行图案化而形成。配线层111A在平面视图中具有包围贯穿孔110H的开口的矩形环状的形状。
贯穿电极120A、120B是沿厚度方向对核层110进行贯穿的电极。贯穿电极120A、120B位于贯穿孔110H的两胁。通过在核层110的贯穿孔110H的两胁所形成的贯穿孔内部填充镀铜,可形成贯穿电极120A、120B。
需要说明的是,这里尽管对贯穿电极120A、120B是通过填充镀铜而形成的形态进行了说明,但是,也可使用在贯穿孔内壁由镀铜形成为圆筒状的透孔来代替贯穿电极120A、120B。
绝缘层130A被形成为覆盖核层110、配线层111A、贯穿电极120A、120B及电容芯片200的上表面。绝缘层130A例如通过对环氧系或聚酰亚胺系等树脂材料进行加热、加压以使其热硬化的方式而形成。需要说明的是,绝缘层130A是在与图1A至图1B上下颠倒的状态下形成了绝缘层130B之后再形成的层。
绝缘层130B可使用与形成绝缘层130A的环氧系或聚酰亚胺系等树脂材料相同的树脂材料。绝缘层130B通过将加热溶融后的树脂填充至贯穿孔110H的内部,并对核层110、贯穿电极120A、120B及电容芯片200的下表面进行覆盖的方式而形成。绝缘层130B例如通过对环氧系或聚酰亚胺系等树脂材料进行加热、加压以使其热硬化的方式而形成。
通孔140A1、140A2、140A3、140A4、140A5及140A6形成在绝缘层130A内所形成的通路孔的内部。通孔1401、140A2及140A3分别与贯穿电极120A、图中左侧的电容芯片200的电极202(图中左侧)及电极202(图中右侧)连接。
通孔140A4、140A5及140A6分别与图中右侧的电容芯片200的电极202(图中左侧)、电极202(图中右侧)及贯穿电极120B连接。通孔140A1、140A2、140A3、140A4、140A5及140A6例如由镀铜膜形成。
通孔140B1、140B2、140B3、140B4、140B5及140B6形成在绝缘层130B内所形成的通路孔的内部。通孔140B1、140B2及140B3分别与贯穿电极120A、图中左侧的电容芯片200的电极202(图中左侧)及电极202(图中右侧)连接。
通孔140B4、140B5、140B6分别与图中右侧的电容芯片200的电极202(图中左侧)、电极202(图中右侧)及贯穿电极120B连接。通孔140B1、140B2、140B3、140B4、140B5及140B6例如由镀铜膜形成。
配线层150A1、150A2、150A3、150A4、150A5及150A6形成在绝缘层130A的上表面,并分别与通孔140A1、140A2、140A3、140A4、140A5及140A6连接。配线层150A1、150A2、150A3、150A4、150A5及150A6例如由镀铜膜形成。
配线层150B1、150B2、150B3、150B4、150B5及150B6形成在绝缘层130B的下表面,并分别与通孔140B1、140B2、140B3、140B4、140B5及140B6连接。配线层150B1、150B2、150B3、150B4、150B5及150B6例如由镀铜膜形成。
阻焊层160A形成在绝缘层130A和配线层150A1、150A2、150A3、150A4、150A5、150A6之上。配线层150A1、150A2、150A3、150A4、150A5及150A6中的从阻焊层160A的表面露出的部分作为端子来使用。
阻焊层160B形成在绝缘层130B和配线层150B1、150B2、150B3、150B4、150B5、150B6之下。配线层150B1、150B2、150B3、150B4、150B5及150B6中的从阻焊层160B的表面露出的部分作为端子来使用。
电容芯片200是电子器件的一个例子,在贯穿孔110H的内部配设有2个。2个电容芯片200分别具有主体201和一对电极202。主体201例如为陶瓷制,并对设置在两侧的电极202进行支撑。电容芯片200的介电常数(电容率)由主体201的材料决定。
如图1B所示,电极202在YZ面视图中(即、从X轴方向观察时)大于主体201,并从主体201沿Y轴正方向和Y轴负方向以及Z轴正方向和Z轴负方向突出。另外,一对电极202分别形成为覆盖主体201的X轴正方向侧的面和X轴负方向侧的面。即,一对电极202分别形成为帽(cap)状,以对长方体状的主体201的X轴正方向侧和X轴负方向侧进行覆盖。每个电容芯片200都具有长方体形状,并沿长度方向(纵向方向)平排排列。
如图1B所示,电容芯片200的一对电极202的Y轴正方向侧的侧面和Y轴负方向侧的侧面与突出部110A的前端卡合,据此,电容芯片200通过与Y轴正方向侧的突出部110A和Y轴负方向侧的突出部110A卡合而被支撑。
另外,电容芯片200的侧面和下表面被绝缘层130B支撑,并且,其上表面侧被绝缘层130A固定。
2个电容芯片200在如上所述的状态下在贯穿孔110H的内部沿X轴方向并排设置,以使一对电极202分别位于X轴正方向侧和X轴负方向侧。另外,2个电容芯片200互相分离并互相绝缘。
接下来,参照图2A至图2C和图3A至图3C对核层110的贯穿孔110H进行说明。
图2A至图2C是表示核层110的截面图。图2A是平面图(表示XY平面的图);图2B表示与图1A的XZ平面相平行的截面;图2C表示与图1B的YZ平面相平行的截面,其表示的是图2A中从X轴的负方向侧向正方向侧进行观察时的A2-A2截面。需要说明的是,图2A至图2C表示的是核层110上形成了配线层111A和贯穿电极120A、120B的状态。
如上所述,核层110例如是用环氧树脂浸渍过的玻璃布基材,用作堆积基板的核,并具有沿厚度方向贯穿的贯穿孔110H。
贯穿孔110H的内壁具有突出部110A。突出部110A在平面视图中向贯穿孔110H的内侧突出,如图2B、图2C所示,其截面为渐细状。突出部110A沿贯穿孔110H的内壁被形成为矩形环状。
这样的渐细状的突出部110A的形状是通过如下方式形成的,即,贯穿孔110H的内壁不是被形成为沿Z轴垂直,而是被形成为从核层110的上表面及下表面开始小于90度的角度,以使核层110的厚度方向的大致中央处向贯穿孔110H的内侧突出的最多。
突出部110A中的向贯穿孔110H的内侧突出最多的部分形成顶部110A1;贯穿孔110H具有从顶部110A1开始的向核层110的上表面侧和下表面侧的开口逐渐变大的形状。
突出部110A例如通过由激光加工来制作贯穿孔110H的方式形成。
图3A至图3C是表示在核层110的贯穿孔110H的内部配置了电容芯片200的状态的图。图3A至图3C表示的是形成绝缘层130A、130B之前的状态。
图3A~图3C是与图2A~图2C对应的平面图和截面图,图3C表示的是图3B中从X轴的负方向侧向正方向侧进行观察时的A3-A3截面。
如图3A所示,在贯穿孔110H的内部,电容芯片200的一对电极202的Y轴正方向侧的侧面和Y轴负方向侧的侧面与突出部110A的前端卡合。据此,电容芯片200可被突出部110A支撑。
在贯穿孔110H的内部,Y轴正方向侧的突出部110A的顶部110A1和Y轴负方向侧的突出部110A的顶部110A1之间的距离被设定为,比电容芯片200的电极202的Y轴方向的宽度小一点。
例如,顶部110A1之间的Y轴方向的间隔被设定为,比电容芯片200的电极202的Y轴方向的宽度大约窄2μm~70μm左右。
其目的在于,为了在Y轴方向相对的顶部110A1之间对电极202进行压装(卡合)支撑,尤其在于,为了对电容芯片200的X轴方向的移动进行抑制。
其原因在于,2个电容芯片200由于沿X轴方向平排排列,如果沿X轴方向发生了移动,则可能会导致电极202之间进行接触,进而发生短路,或者,可能会导致电极202难以与通孔140A2~140A5、140B2~140B5进行有效的连接。
基于这样理由,在本实施方式的配线基板100中,使相对于2个电容芯片200的并排排列方向的侧部与从贯穿孔110H的内壁突出的突出部110A卡合。
另外,如上所述,就电容芯片200而言,由于电极202的Y轴方向的宽度比主体201宽,所以,顶部110A1之间的Y轴方向的间隔最好比主体201的Y轴方向的宽度还宽。其原因在于,由于主体201是形成电容芯片200的电容的部分,并被设定为具有预定的介电常数,所以,如果设计为不使其与顶部110A1和突出部110A相接触,则电容芯片200的电气特性就不会受到影响,为优选。
电容芯片200即使不形成如图1A至图1B所示的绝缘层130A、130B等,如图3A~图3C所示,在被设置在贯穿孔110H的内部的状态下,也会被支撑在沿Y轴方向相对的顶部110A1之间。
另外,如图3A所示,贯穿孔110H的X轴方向的长度在2个电容芯片200之间间隔了绝缘所需的间隔的状态下被设定如下。即,贯穿孔110H的X轴方向的长度被设定为,位于X轴正方向侧的电容芯片200的X轴正方向侧存在空间,并且,位于X轴负方向侧的电容芯片200的X轴负方向侧也存在空间。
如此这样地在2个电容芯片200的X轴正方向侧和X轴负方向侧设置空间的理由如下。即,在从贯穿孔110H的上方将电容芯片200配置在贯穿孔110H的内部时,可以容易地将电容芯片200插入贯穿孔110H的内部。另外,还可以防止电容芯片200卡在贯穿孔110H的X轴正方向侧和X轴负方向侧的内壁上。
例如,在核层110的上方沿X轴方向搬送电容芯片200以将其配置在贯穿孔110H的内部的情况下,电容芯片200的位置即使相对于贯穿孔110H沿X轴方向发生了一点偏移,也可以确实地将2个电容芯片200配置在贯穿孔110H的内部。
接下来,参照图4A至图6C对本实施方式的配线基板100的制造方法进行说明,并且参照图7对在配线基板100上实装LSI(Large Scale Integratedcircuit)芯片的步骤进行说明。
图4A至图6C是表示本实施方式的配线基板100的制造步骤的图。以下所示的截面是与图1A、图2B、图3B相对应的截面。
首先,如图4A、图4B所示,准备一形成了配线层111A和贯穿电极120A、120B的核层110,并进行激光加工,以形成贯穿孔110H(参照图2A、图2B)。
例如,如图4A、图4B所示,通过对激光束的直径和输出功率进行调整,以使1次激光照射就可形成孔部110H1。如图4A所示,孔部110H1例如具有贯穿孔110H的Y轴方向的宽度的大约1/3左右的直径,并具有比核层110的厚度的一半还深一点的深度。另外,如图4B所示,孔部110H1具有随着深度的增加开口逐渐变小的截面形状。这样的孔部110H1的形状可通过激光加工实现。
这样,在形成贯穿孔110H的区域内,通过如图4A中虚线圆所示的那样连续地移动激光照射的位置,然后,再使核层110上下颠倒并进行同样的激光照射,就可形成贯穿孔110H。
此时,在从核层110的两面进行激光照射时,如果对激光束的直径和输出功率进行调整,以使贯穿孔110H的内壁留下突出部110A,则还可在核层110内形成具有突出部110A的贯穿孔110H。
需要说明的是,这里尽管示出了在形成了配线层111A和贯穿电极120A、120B的核层110内形成贯穿孔110H的步骤,然而,也可以先在核层110上形成贯穿孔110H,然后再形成配线层111A和贯穿电极120A、120B。
接下来,如图5A所示,对核层110进行上下倒转,并在核层110的形成了配线层111A的面上贴附临时胶带300。临时胶带300在图5A中的上表面具有黏着层。临时胶带300例如为PET等树脂膜制。
之后,如图5B所示,在核层110的贯穿孔110H的内部插入2个电容芯片200,并使电容芯片200的电极202卡合在Y轴正方向侧的突出部110A的顶部110A1和Y轴负方向侧的突出部110A的顶部110A1之间(参照图3A至图3C)。另外,在该状态下,电容芯片200贴附在临时胶带300上,据此,可对电容芯片200进行临时固定。
接下来,如图5C所示,将加热溶融后的树脂材料填充至贯穿孔110H的内部,并使其覆盖核层110、贯穿电极120A、120B及电容芯片200。具体为,以覆盖贯穿孔110H的方式在核层110之上积层(形成)树脂膜,并对其进行加热溶融。然后,对树脂材料进行加热和加压,并使其热硬化,据此,形成绝缘层130B。
在该步骤中,由于电容芯片200被突出部110A所支撑,并且还被临时胶带300进行了临时固定,所以,可防止2个电容芯片200的位置偏移。因此,可防止2个电容芯片200之间的接触,进而可维持电容芯片200之间的绝缘性。
另外,由于配线层111A在平面视图中为矩形环状,并包围贯穿孔110H的开口,所以,可防止绝缘层130B进入配线层111A的外侧。需要说明的是,在绝缘层130B的所述进入(乱入)不成问题或不会发生所述进入(乱入)的情况下,也可不设置包围贯穿孔110H的开口的配线层111A。
接下来,取下临时胶带300,然后,如图5D所示,再使核层110上下颠倒。
接下来,如图5E所示,以覆盖核层110、配线层111A、贯穿电极120A、120B及电容芯片200的上表面的方式形成绝缘层130A。绝缘层130A可通过对与绝缘层130B相同的树脂材料进行加热和加压,并使其热硬化的方式形成。
需要说明的是,在该步骤中,由于电容芯片200被突出部110A和绝缘层130B所支撑,所以,可防止出现2个电容芯片200的位置偏差。因此,可防止2个电容芯片200之间的接触,进而可维持电容芯片200之间的绝缘性。另外,在图5C~图5E的步骤中,还由绝缘层130A和130B对电容芯片200进行了密封。
接下来,如图6A所示,形成通路孔131A、131B。就通路孔131A而言,可在之后要形成通孔140A1~140A6的位置,例如通过激光加工来形成该通路孔131A。对通路孔131B而言,使核层110上下颠倒后,可在之后要形成通孔140B1~140B6的位置,例如通过激光加工来形成该通路孔131B。
接下来,如图6B所示,形成通孔140A1~140A6和140B1~140B6、以及、配线层150A1~150A6和150B1~150B6。
通孔140A1~140A6和140B1~140B6可分别在通路孔131A、131B的内部例如采用半进加(semi-additive)法来形成。这里,通孔140A1~140A6是同时形成的,并且,通孔140B1~140B6也是同时形成的。
另外,就配线层150A1~150A6和150B1~150B6而言,可在电镀形成了通孔140A1~140A6和140B1~140B6之后马上再采用半加法,以使这些配线层分别与这些通孔一体形成。
接下来,如图6C所示,形成阻焊层160A和160B。
阻焊层160A可通过如下方式形成,即,在绝缘层130A和配线层150A1~150A6之上整面地形成阻焊材料之后,再通过曝光·显影等,使配线层150A1~150A6中的要被用作为端子的部分从表面露出来。需要说明的是,阻焊材料为感光性环氧树脂制或感光性丙烯树脂制。
同样,阻焊层160B可通过如下方式形成,即,在绝缘层130B和配线层150B1~150B6之上整面地形成阻焊材料之后,再通过曝光·显影等,使配线层150B1~150B6中的要被用作为端子的部分从表面露出来。
至此,完成了本实施方式的配线基板100的制作。
图7是表示在配线基板100上实装了LSI芯片400的状态的图。
如图7所示,在配线层150A1~150A6中的作为端子使用的部分,可介由凸块(bump)401实装LSI芯片400。LSI芯片400之下可填充底部填充树脂402。
根据本实施方式可知,2个电容芯片200通过被卡合在贯穿孔110H的内壁的突出部110A上以被进行了定位后,才开始形成绝缘层130A、130B至阻焊层160A、160B。
这样,可防止出现沿X轴方向并排排列的2个电容芯片200的位置偏差的问题,进而可防止出现电极202之间接触所导致的短路、以及、电极202和通孔140A2~140A5、140B2~140B5的连接不良的问题。
因此,能提供一种在将2个电容芯片200配设在1个贯穿孔110H的内部时可提高电气可靠性的配线基板100及配线基板100的制造方法。
这里,需要说明的是,在配线基板100上安装CPU等工作在高频下的半导体芯片的情况下,为了提高电气特性,一般需要内置多个电容芯片200。
如果1个贯穿孔110H内仅可设置1个电容芯片200,则在需要内置多个电容芯片200的情况下,需要增加贯穿孔110H的数量,并需要增大配线基板100上的贯穿孔110H的专用面积。这样,贯穿孔110H的存在就会降低配线设置的自由度。另外,为了设置多个贯穿孔110H,还需要增加配线基板100的平面面积。
为了解决上述问题,在本实施方式中,1个贯穿孔110H的内部设置了多个电容芯片200。
需要说明的是,也可以设置多个贯穿孔110H。
还需要说明的是,尽管上面对1个贯穿孔110H的内部设置了2个电容芯片200的形态进行了说明,然而,1个贯穿孔110H的内部所配置的电容芯片200的数量只要为2个以上,可为任意多个。
另外,尽管上面对贯穿孔110H的内部配设了电容芯片200的形态进行了说明,然而,贯穿孔110H的内部所配置的器件并不限定于电容芯片200,只要是外面具有端子等的电子器件,可为任何器件。例如,贯穿孔110H的内部也可配置多个CPU(Central Processing Unit)芯片。
另外,尽管上面对通过进行激光加工形成了贯穿孔110H,并且,突出部110A为进行激光加工时残留在核层110的厚度方向的中央处的部分的形态进行了说明,然而,贯穿孔110H也可通过刳刨(routing)加工或其他机械加工来形成。
另外,尽管上面对使电容芯片200的主体201不与突出部110A接触的形态进行了说明,然而,在电容芯片200的电气特性不会发生问题的情况下,也可通过突出部110A对主体201进行支撑。
另外,尽管上面对突出部110A沿着贯穿孔110H的内壁被形成为矩形环状的形态进行了说明,然而,突出部110A并不一定需要沿着贯穿孔110H的内壁被形成为环状,只要能与2个电容芯片200相卡合并能实现定位,也可形成在贯穿孔110H的一部分上。例如,可为如后所述的图8A至图8C所示的状态。
另外,尽管上面对通过在2个电容芯片200的X轴正方向侧和X轴负方向侧设置空间的方式来形成贯穿孔110H的形态进行了说明,然而,如果在贯穿孔110H的内部配置电容芯片200时不会发生问题,则也可在2个电容芯片200的X轴正方向侧和X轴负方向侧不设置空间。
另外,尽管上面对核层110的上下各形成了1层绝缘层130A、130B的配线基板100进行了说明,然而,配线基板100也可包含多层与绝缘层130A、130B同样的绝缘层,还可包含多层配线层。
图8A至图8C是表示本实施方式的变形例的核层110X的截面图。图8A~图8C与图2A~图2C相对应。
核层110X内所形成的贯穿孔110HX在内壁上具有突出部110XA1、110XA2。突出部110XA1、110XA2在平面视图中从贯穿孔110HX的沿着X轴的内壁开始向贯穿孔110HX的内侧突出,如图8C所示,其截面为渐细状。突出部110XA1、110XA2没有形成在贯穿孔110HX的沿着Y轴的内壁上。
这样的渐细状的突出部110XA1、110XA2为图2A至图2C所示的突出部110A中的、贯穿孔110H的沿着Y轴的内壁上所形成的部分被除掉了的形状。另外,在贯穿孔110HX的平面视图中的四角,被设计为突出量徐々变小的形状。
这样,在贯穿孔110HX的内部配置了2个电容芯片200的情况下,就2个电容芯片200而言,Y轴正方向侧的侧面和Y轴负方向侧的侧面分别与突出部110XA1、110XA2卡合。这与图2A至图2C所示的突出部110A与2个电容芯片200的Y轴正方向侧的侧面和Y轴负方向侧的侧面分别卡合相同。
由于突出部110XA1、110XA2没有被形成在贯穿孔110HX的沿着Y轴的内壁,所以,电容芯片200在为某些形状时,要比图2A至图2C所示的状态更容易地配置在贯穿孔110H的内部。
另外,由于突出部110XA1、110XA2没有被形成在贯穿孔110HX的沿着Y轴的内壁,所以,可将贯穿孔110HX的X轴方向的长度设定为短于图2A至图2C所示的贯穿孔110H。
需要说明的是,为了使突出部110XA1、110XA2不形成在贯穿孔110HX的沿着Y轴的内壁,例如,可通过激光加工除去图2A至图2C所示的突出部110A中的位于贯穿孔110H的沿着Y轴的内壁的部分。
以上尽管对本发明的较佳实施方式的配线基板及配线基板的制造方法进行了说明,但是本发明并不限定于上述具体公开的实施方式,只要不脱离权利要求书记载的范围,还可进行各种各样的变形和变更。
Claims (11)
1.一种配线基板,包含:
核层,其沿厚度方向形成有贯穿孔,并具有从所述贯穿孔的内壁向所述贯穿孔的内侧突出的突起部;
多个电子器件,其在平面视图中相互分离地并排设置在所述贯穿孔的内部,并具有侧部,所述侧部与所述突出部卡合;及
树脂层,其被填充在所述贯穿孔的内部,并对所述电子器件进行支撑。
2.如权利要求1所述的配线基板,其中:
所述平面视图与所述厚度方向垂直,
所述侧部与所述多个电子器件的并排排列方向相对。
3.如权利要求2所述的配线基板,其中:
所述贯穿孔在所述平面视图中为矩形形状,
所述突出部至少从位于与所述多个电子器件的并排排列方向相对的侧面的一对所述内壁突出,
所述电子器件的与所述并排排列方向相对的两侧的侧部与所述突出部卡合。
4.如权利要求3所述的配线基板,其中:
所述突出部在所述平面视图中沿着矩形形状的所述贯穿孔的所述内壁被形成为矩形环状,
所述电子器件的与所述并排排列方向相对的两侧的侧部与所述突出部卡合。
5.如权利要求3所述的配线基板,其中:
所述贯穿孔在所述平面视图中为矩形形状,
所述突出部为从位于与所述多个电子器件的并排排列方向相对的侧面的一对所述内壁突出的一对突出部,
所述电子器件的所述两侧的侧部与所述一对突出部分别卡合。
6.如权利要求2至5中任一项所述的配线基板,其中:
由所述突出部的突出方向和所述核层的厚度方向所定义的所述突出部的截面形状为从所述核层的两个面开始被形成为渐细状的形状。
7.如权利要求2至5中任一项所述的配线基板,其中:
所述电子器件为长方体形状,所述并排排列方向的两端形成有电极,所述电极的侧部与所述突出部卡合。
8.如权利要求2至5中任一项所述的配线基板,其中:
所述电子器件为长方体形状,沿所述电子器件的长度方向并排排列所述多个电子器件。
9.如权利要求2至5中任一项所述的配线基板,其中:
所述电子器件为电容芯片。
10.一种配线基板的制造方法,包含:
第一步骤,通过从核层的一个面和另一个面形成孔部,沿厚度方向在所述核层形成贯穿孔,所述贯穿孔具有从内壁向内侧突出的突出部;
第二步骤,将多个电子器件在平面视图中相互分离地设置在所述贯穿孔的内部,并使所述多个电子器件的侧部与所述突出部卡合;及
第三步骤,通过在所述贯穿孔的内部填充树脂材料,形成对所述电子器件进行支撑的树脂层。
11.如权利要求10所述的配线基板的制造方法,其中:
所述平面视图与所述厚度方向垂直,
所述侧部与所述多个电子器件的并排排列方向相对。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014043318A JP6334962B2 (ja) | 2014-03-05 | 2014-03-05 | 配線基板、及び、配線基板の製造方法 |
JP2014-043318 | 2014-03-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104902682A true CN104902682A (zh) | 2015-09-09 |
Family
ID=54018868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510093012.8A Pending CN104902682A (zh) | 2014-03-05 | 2015-03-02 | 配线基板及配线基板的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9497863B2 (zh) |
JP (1) | JP6334962B2 (zh) |
CN (1) | CN104902682A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111508923A (zh) * | 2019-01-31 | 2020-08-07 | 奥特斯奥地利科技与系统技术有限公司 | 在部件承载件材料中制造具有低偏移的通孔 |
WO2021083367A1 (zh) * | 2019-07-07 | 2021-05-06 | 深南电路股份有限公司 | 线路板及其制作方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6373605B2 (ja) * | 2014-03-05 | 2018-08-15 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
JP6334962B2 (ja) | 2014-03-05 | 2018-05-30 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
KR102356810B1 (ko) * | 2015-01-22 | 2022-01-28 | 삼성전기주식회사 | 전자부품내장형 인쇄회로기판 및 그 제조방법 |
JP6016965B2 (ja) * | 2015-03-02 | 2016-10-26 | 三菱電機株式会社 | 電子機器ユニット及びその製造金型装置 |
US20160315024A1 (en) * | 2015-04-21 | 2016-10-27 | Qualcomm Incorporated | Mechanical handling support for thin cores using photo-patternable material |
JP6693441B2 (ja) * | 2017-02-27 | 2020-05-13 | オムロン株式会社 | 電子装置およびその製造方法 |
JP7042384B1 (ja) | 2021-11-04 | 2022-03-25 | 東京瓦斯株式会社 | 水素ステーション |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101594740A (zh) * | 2008-05-27 | 2009-12-02 | 华通电脑股份有限公司 | 嵌埋电子器件的电路板及其方法 |
US20130333930A1 (en) * | 2012-06-15 | 2013-12-19 | Shinko Electric Industries Co., Ltd. | Wiring board and method of manufacturing the same |
CN103563498A (zh) * | 2011-05-13 | 2014-02-05 | 揖斐电株式会社 | 电路板及其制造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7876577B2 (en) | 2007-03-12 | 2011-01-25 | Tyco Electronics Corporation | System for attaching electronic components to molded interconnection devices |
JP5001395B2 (ja) * | 2010-03-31 | 2012-08-15 | イビデン株式会社 | 配線板及び配線板の製造方法 |
JP2012079994A (ja) | 2010-10-05 | 2012-04-19 | Yamaichi Electronics Co Ltd | 部品内蔵プリント配線板およびその製造方法 |
JP2012164952A (ja) * | 2011-01-20 | 2012-08-30 | Ibiden Co Ltd | 電子部品内蔵配線板及びその製造方法 |
US8957320B2 (en) | 2011-10-11 | 2015-02-17 | Ibiden Co., Ltd. | Printed wiring board |
US9439289B2 (en) | 2012-01-12 | 2016-09-06 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP2014107431A (ja) * | 2012-11-28 | 2014-06-09 | Ibiden Co Ltd | 電子部品内蔵配線板、及び、電子部品内蔵配線板の製造方法 |
JP5462404B1 (ja) | 2013-09-12 | 2014-04-02 | 太陽誘電株式会社 | 部品内蔵基板及び部品内蔵基板用コア基材 |
JP2015159153A (ja) | 2014-02-21 | 2015-09-03 | イビデン株式会社 | 電子部品内蔵多層配線板 |
JP6334962B2 (ja) | 2014-03-05 | 2018-05-30 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
JP2015185828A (ja) | 2014-03-26 | 2015-10-22 | イビデン株式会社 | 電子部品内蔵多層配線板およびその製造方法 |
JP2015220281A (ja) | 2014-05-15 | 2015-12-07 | イビデン株式会社 | プリント配線板 |
-
2014
- 2014-03-05 JP JP2014043318A patent/JP6334962B2/ja active Active
-
2015
- 2015-02-19 US US14/625,809 patent/US9497863B2/en active Active
- 2015-03-02 CN CN201510093012.8A patent/CN104902682A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101594740A (zh) * | 2008-05-27 | 2009-12-02 | 华通电脑股份有限公司 | 嵌埋电子器件的电路板及其方法 |
CN103563498A (zh) * | 2011-05-13 | 2014-02-05 | 揖斐电株式会社 | 电路板及其制造方法 |
US20130333930A1 (en) * | 2012-06-15 | 2013-12-19 | Shinko Electric Industries Co., Ltd. | Wiring board and method of manufacturing the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111508923A (zh) * | 2019-01-31 | 2020-08-07 | 奥特斯奥地利科技与系统技术有限公司 | 在部件承载件材料中制造具有低偏移的通孔 |
CN111508923B (zh) * | 2019-01-31 | 2024-03-26 | 奥特斯奥地利科技与系统技术有限公司 | 在部件承载件材料中制造具有低偏移的通孔 |
WO2021083367A1 (zh) * | 2019-07-07 | 2021-05-06 | 深南电路股份有限公司 | 线路板及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
JP6334962B2 (ja) | 2018-05-30 |
JP2015170670A (ja) | 2015-09-28 |
US20150257274A1 (en) | 2015-09-10 |
US9497863B2 (en) | 2016-11-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104902682A (zh) | 配线基板及配线基板的制造方法 | |
US8952262B2 (en) | Component-incorporated wiring substrate and method of manufacturing the same | |
US20160155713A1 (en) | Semiconductor package and method of manufacturing the same | |
US9526177B2 (en) | Printed circuit board including electronic component embedded therein and method for manufacturing the same | |
KR102100209B1 (ko) | 배선 기판 | |
US10237978B2 (en) | Component built-in multilayer substrate fabricating method | |
US9560768B2 (en) | Wiring substrate and method of making wiring substrate | |
TWI536508B (zh) | Wiring board | |
US20160081191A1 (en) | Printed circuit board and manufacturing method thereof | |
US20150237712A1 (en) | Radio frequency module | |
US20160093546A1 (en) | Package stucture and method of fabricating the same | |
KR101434039B1 (ko) | 전력 반도체 모듈 및 전력 반도체 제조 방법 | |
US20150068795A1 (en) | Substrate with built-in electronic component and core base-material for substrate with built-in electronic component | |
US9485878B2 (en) | Substrate structure having electronic components and method of manufacturing substrate structure having electronic components | |
CN104081885A (zh) | 元器件内置基板 | |
US20130258623A1 (en) | Package structure having embedded electronic element and fabrication method thereof | |
US9899360B2 (en) | Semiconductor device | |
US9905503B2 (en) | Package stucture and method of fabricating the same | |
CN103633069A (zh) | 封装结构和电子设备 | |
JP2011151274A (ja) | 回路モジュール及び回路モジュールの製造方法 | |
US20140284081A1 (en) | Wiring substrate | |
US9192050B2 (en) | Method of manufacturing printed circuit board | |
US20140131083A1 (en) | Printed circuit board and method for manufacturing the same | |
JP2013214765A (ja) | 部品内蔵基板 | |
KR20160116837A (ko) | 인쇄회로기판 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150909 |
|
RJ01 | Rejection of invention patent application after publication |