US20120056202A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US20120056202A1
US20120056202A1 US13/320,247 US201013320247A US2012056202A1 US 20120056202 A1 US20120056202 A1 US 20120056202A1 US 201013320247 A US201013320247 A US 201013320247A US 2012056202 A1 US2012056202 A1 US 2012056202A1
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layer
silicon carbide
sic
semiconductor device
substrate
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Keiji Wada
Shin Harada
Takeyoshi Masuda
Misako Honaga
Makoto Sasaki
Taro Nishiguchi
Yasuo Namikawa
Shinsuke Fujiwara
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD. reassignment SUMITOMO ELECTRIC INDUSTRIES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJIWARA, SHINSUKE, HARADA, SHIN, MASUDA, TAKEYOSHI, NAMIKAWA, YASUO, NISHIGUCHI, TARO, SASAKI, MAKOTO, HONAGA, MISAKO, WADA, KEIJI
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD. reassignment SUMITOMO ELECTRIC INDUSTRIES, LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER TITLE, AND FILING DATE PREVIOUSLY RECORDED ON REEL 027217, FRAME 0994. Assignors: FUJIWARA, SHINSUKE, HARADA, SHIN, MASUDA, TAKEYOSHI, NAMIKAWA, YASUO, NISHIGUCHI, TARO, SASAKI, MAKOTO, HONAGA, MISAKO, WADA, KEIJI
Publication of US20120056202A1 publication Critical patent/US20120056202A1/en
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Definitions

  • the present invention relates to a semiconductor device, more particularly, a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process.
  • silicon carbide SiC
  • SiC silicon carbide
  • Silicon carbide is a wide band gap semiconductor having a band gap larger than that of silicon, which has been conventionally widely used as a material for semiconductor devices.
  • the semiconductor device can have a high breakdown voltage, reduced on-resistance, and the like.
  • the semiconductor device thus adopting silicon carbide as its material has characteristics less deteriorated even under a high temperature environment than those of a semiconductor device adopting silicon as its material, advantageously.
  • the high-performance semiconductor device adopting silicon carbide as its material, it is effective to employ a process of preparing a substrate made of silicon carbide (silicon carbide substrate), and forming an epitaxial growth layer made of SiC on the silicon carbide substrate. Further, on-resistance of the device can be reduced by reducing resistivity of the substrate in the thickness direction thereof as much as possible when manufacturing, for example, a vertical type power device (such as a vertical type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using the silicon carbide substrate.
  • a vertical type power device such as a vertical type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using the silicon carbide substrate.
  • an impurity which is an n type dopant such as nitrogen
  • a method of introducing an impurity for example, see R. C. GLASS et al., “SiC Seeded Crystal Growth”, Phys. stat. sol. (b), 1997, 202, p149-162 (Non-Patent Literature 1)
  • an impurity which is an n type dopant such as nitrogen
  • NPL 1 R. C. GLASS et al., “SiC Seeded Crystal Growth”, Phys. stat. sol. (b), 1997, 202, p149-162
  • the resistivity of the substrate is reduced by simply introducing the impurity into the substrate at a high concentration, the following problem takes place. That is, when fabricating a semiconductor device using the silicon carbide substrate, the silicon carbide substrate is subjected to heat treatment such as thermal cleaning for cleaning a surface of the silicon carbide substrate. On this occasion, stacking faults are produced in the silicon carbide substrate containing the impurity at a high concentration. When an epitaxial growth layer made of SiC is formed on the silicon carbide substrate, the stacking faults are propagated to the SiC layer.
  • each of the stacking faults to be produced has a structure of 3C type, which has a band gap smaller than that in the 4H type. Accordingly, the band gap becomes smaller locally in the region in which the stacking faults are produced. As a result, if a semiconductor device is fabricated using such a silicon carbide substrate, problems will take place such as reduced breakdown voltage and increased leakage current.
  • the present invention has its object to provide a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process.
  • a semiconductor device includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a first electrode disposed on the active layer; and a second electrode formed on the other main surface of the silicon carbide substrate.
  • the silicon carbide substrate includes a base layer made of silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer.
  • the base layer has an impurity concentration greater than 2 ⁇ 10 19 cm ⁇ 3
  • the SiC layer has an impurity concentration greater than 5 ⁇ 10 18 cm ⁇ 3 and smaller than 2 ⁇ 10 19 cm ⁇ 3 . Between the base layer and the SiC layer, there is a boundary in which a defect density is discontinuous.
  • the present inventors have fully studied approaches for reducing resistivity of a silicon carbide substrate in the thickness direction thereof while restraining stacking faults from being produced due to heat treatment in a device manufacturing process. As a result, it has been found that the stacking faults can be prevented from being produced due to the heat treatment when the impurity concentration thereof is less than 2 ⁇ 10 19 cm ⁇ 3 , whereas the stacking faults are less likely to be prevented when the impurity concentration exceeds 2 ⁇ 10 19 cm ⁇ 3 .
  • the silicon carbide substrate is provided with the layer (base layer) having an impurity concentration greater than 2 ⁇ 10 19 cm ⁇ 3 and having a small resistivity and the layer (SiC layer) having an impurity concentration smaller than 2 ⁇ 10 19 cm ⁇ 3 and placed on the base layer. Accordingly, even if heat treatment is subsequently performed in the device manufacturing process, stacking faults can be prevented from being produced at least in the SiC layer. Further, by forming an epitaxial growth layer (active layer) made of SiC on such a SiC layer so as to fabricate the semiconductor device, the resistivity of the silicon carbide substrate can be reduced by the existence of the base layer, while preventing influence of stacking faults, which can be produced in the base layer, over the characteristics of the semiconductor device. Meanwhile, when the impurity concentration of the SiC layer is equal to or smaller than 5 ⁇ 10 18 cm ⁇ 3 , the resistivity of the SiC layer can become too large, disadvantageously.
  • the semiconductor device of the present invention there can be provided a semiconductor device allowing for reduced on-resistance while restraining stacking fault from being produced due to heat treatment in the device manufacturing process.
  • impurity refers to an impurity to be introduced to produce a majority carrier in the silicon carbide substrate.
  • the base layer and the SiC layer are connected to each other, for example.
  • the silicon carbide substrate can be readily obtained in which the SiC layer is provided while preventing propagation of the defects of the base layer.
  • the base layer and the SiC layer may be directly connected to each other, or may be connected to each other via an intermediate layer.
  • the impurity contained in the base layer may be different from that contained in the SiC layer. In this way, a semiconductor device can be obtained which includes the silicon carbide substrate containing impurities appropriately depending on intended purpose of use.
  • the impurity contained in the base layer can be nitrogen or phosphorus, whereas the impurity contained in the SiC layer can be also nitrogen or phosphorus.
  • Each of nitrogen and phosphorus is suitable as an impurity for supplying the SiC with electrons, which serve as majority carriers.
  • the base layer may be made of single-crystal silicon carbide and a half width of X-ray rocking curve of the SiC layer may be smaller than that of the base layer.
  • SiC does not have a liquid phase at an atmospheric pressure.
  • the crystal growth temperature is very high, specifically, equal to or greater than 2000° C., which makes it difficult to control and stabilize the growth conditions. Accordingly, it is difficult for a substrate made of single-crystal SiC to keep its high quality and have a large diameter.
  • a substrate provided with predetermined uniform shape and size is required for efficient manufacturing in a process of manufacturing a semiconductor device using a silicon carbide substrate.
  • the silicon carbide substrate of the present invention on the base layer processed into the predetermined shape and size, there can be disposed the SiC layer having, for example, a smaller half width of the X-ray rocking curve, i.e., having higher crystallinity than that of the base layer but not formed into the desired shape and the like.
  • a silicon carbide substrate has the predetermined uniform shape and size corresponding to those of the base layer, thus attaining effective manufacturing of semiconductor devices.
  • such a silicon carbide substrate utilizes the high-quality SiC layer to manufacture a semiconductor device, thereby effectively utilizing the high-quality single-crystal silicon carbide. As a result, the manufacturing cost of the semiconductor device can be reduced.
  • the active layer may include: a drift layer having a first conductivity type, disposed on/over the silicon carbide substrate, and made of single-crystal silicon carbide; a well region having a second conductivity type and disposed to include a first main surface of the drift layer opposite to the silicon carbide substrate; a source region having the first conductivity type and disposed in contact with the first electrode to include the first main surface within the well region; an insulating film disposed on the first main surface in contact with the well region and made of an insulator; and a third electrode disposed on the insulating film.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the insulating film may be made of silicon dioxide. In this way, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be obtained.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the main surface of the SiC layer opposite to the base layer may have an off angle of not less than 50° and not more than 65° relative to a ⁇ 0001 ⁇ plane.
  • a high-quality single-crystal can be fabricated efficiently. From such a silicon carbide single-crystal grown in the ⁇ 0001> direction, a silicon carbide substrate having a main surface corresponding to the ⁇ 0001 ⁇ plane can be obtained efficiently. Meanwhile, by using a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to the plane orientation of ⁇ 0001 ⁇ , a semiconductor device with high performance may be manufactured.
  • a silicon carbide substrate used for fabrication of a MOSFET has a main surface having an off angle of approximately 0.3° to 8° relative to a plane orientation of ⁇ 0001 ⁇ .
  • An epitaxial growth layer (active layer) is formed on this main surface and an insulating film (oxide film), an electrode, and the like are formed on this active layer, thereby obtaining a MOSFET.
  • a channel region is formed in a region including an interface between the active layer and the insulating film.
  • the main surface of the SiC layer opposite to the base layer is adapted to have an off angle of not less than 50° and not more than 65° relative to the ⁇ 0001 ⁇ plane, thereby reducing formation of the interface states.
  • a MOSFET can be fabricated which allows for reduced on-resistance.
  • the main surface of the SiC layer opposite to the base layer has an off orientation forming an angle of 5° or smaller relative to a ⁇ 1-100> direction.
  • the ⁇ 1-100> direction is a representative off orientation in a silicon carbide substrate. Variation in the off orientation resulting from variation in a slicing process of the process of manufacturing the substrate is adapted to be 5° or smaller, which allows an epitaxial growth layer (active layer) to be formed readily on the silicon carbide substrate.
  • the main surface of the SiC layer opposite to the base layer may have an off angle of not less than ⁇ 3° and not more than 5° relative to a ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction. Accordingly, channel mobility can be further improved in the case where a MOSFET is fabricated using the silicon carbide substrate.
  • setting the off angle at not less than ⁇ 3° and not more than +5° relative to the plane orientation of ⁇ 03-38 ⁇ is based on a fact that particularly high channel mobility was obtained in this set range as a result of inspecting a relation between the channel mobility and the off angle.
  • the “off angle relative to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction” refers to an angle formed by an orthogonal projection of a normal line of the above-described main surface to a flat plane defined by the ⁇ 1-100> direction and the ⁇ 0001> direction, and a normal line of the ⁇ 03-38 ⁇ plane.
  • the sign of positive value corresponds to a case where the orthogonal projection approaches in parallel with the ⁇ 1-100> direction whereas the sign of negative value corresponds to a case where the orthogonal projection approaches in parallel with the ⁇ 0001> direction.
  • the plane orientation of the main surface is substantially ⁇ 03-38 ⁇ .
  • the expression “the main surface has a plane orientation of substantially ⁇ 03-38 ⁇ ” is intended to encompass a case where the plane orientation of the main surface of the substrate is included in a range of off angle such that the plane orientation can be substantially regarded as ⁇ 03-38 ⁇ in consideration of processing accuracy of the substrate.
  • the range of off angle is, for example, a range of off angle of ⁇ 2° relative to ⁇ 03-38 ⁇ . Accordingly, the above-described channel mobility can be further improved.
  • the main surface of the SiC layer opposite to the base layer may have an off orientation forming an angle of 5° or smaller relative to a ⁇ 11-20> direction.
  • ⁇ 11-20> is a representative off orientation in a silicon carbide substrate, as with the ⁇ 1-100> direction. Variation in the off orientation resulting from variation in the slicing process of the process of manufacturing the substrate is adapted to be ⁇ 5°, which allows an epitaxial growth layer (active layer) to be formed readily on the SiC substrate.
  • the base layer may be made of single-crystal silicon carbide.
  • the SiC layer preferably has a defect density smaller than that of the base layer.
  • the SiC layer preferably has a micro pipe density smaller than that of the base layer.
  • the SiC layer preferably has a dislocation density lower than that of the base layer.
  • the SiC layer preferably has a threading screw dislocation density smaller than that of the base layer. Further, in the semiconductor device, the SiC layer preferably has a threading edge dislocation density smaller than that of the base layer. Further, in the semiconductor device, the SiC layer preferably has a basal plane dislocation density smaller than that of the base layer. Further, in the semiconductor device, the SiC layer preferably has a composite dislocation density smaller than that of the base layer. Further, in the semiconductor device, the SiC layer preferably has a stacking fault density smaller than that of the base layer. Further, in the semiconductor device, the SiC layer preferably has a point defect density smaller than that of the base layer.
  • the SiC layer is adapted to have the reduced defect densities such as the micro pipe density, the threading screw dislocation density, the threading edge dislocation density, the basal plane dislocation density, the composite dislocation density, the stacking fault density, and the point defect density.
  • the SiC layer allows a high-quality active layer to be formed on the SiC layer.
  • the active layer can be formed by, for example, combining epitaxial growth and ion implantation of an impurity.
  • a plurality of the SiC layers may be provided. In this way, there can be obtained a semiconductor device including the plurality of SiC layers corresponding to intended functions.
  • the silicon carbide substrate may further include an intermediate layer disposed between the base layer and the SiC layer and made of a conductor or a semiconductor, and the intermediate layer connects the base layer and the SiC layer to each other.
  • the intermediate layer By thus employing the structure in which the base layer and the SiC layer are connected to each other by the intermediate layer, there can be readily obtained a semiconductor device including the silicon carbide substrate in which the SiC layer having an impurity concentration greater than 5 ⁇ 10 18 cm ⁇ 3 and smaller than 2 ⁇ 10 19 cm ⁇ 3 is disposed on the base layer having an impurity concentration greater than 2 ⁇ 10 19 cm ⁇ 3 . Further, when the intermediate layer is made of a conductor or a semiconductor, electric connection can be secured between the base layer and the SiC layer.
  • the intermediate layer may be made of a metal.
  • the metal constituting this intermediate layer may have a silicided portion.
  • the intermediate layer may be made of carbon.
  • the intermediate layer may be made of amorphous silicon carbide. Accordingly, electric connection can be readily secured between the base layer and the SiC layer in the thickness direction of the substrate.
  • the base layer may include a single-crystal layer made of single-crystal silicon carbide and including its main surface facing the SiC layer. Accordingly, a difference in physical property (for example, difference in linear expansion coefficient) becomes small between the base layer and the SiC layer, thereby restraining warpage of the silicon carbide substrate.
  • a region other than the single-crystal layer in the base layer may be a non single-crystal layer such as polycrystal silicon carbide, amorphous silicon carbide, or a silicon carbide sintered compact. Accordingly, the manufacturing cost of the semiconductor device can be reduced.
  • a half width of X-ray rocking curve of the SiC layer is preferably smaller than that of the single-crystal layer.
  • the SiC layer preferably has a micro pipe density smaller than that of the single-crystal layer.
  • the SiC layer preferably has a dislocation density lower than that of the single-crystal layer. This allows a high-quality active layer to be formed on the SiC layer.
  • the active layer can be formed by, for example, combining epitaxial growth and ion implantation of an impurity.
  • the semiconductor device of the present invention there can be provided a semiconductor device allowing for reduced on-resistance while restraining stacking fault from being produced due to heat treatment in a device manufacturing process.
  • FIG. 1 is a schematic cross sectional view showing a structure of a MOSFET.
  • FIG. 2 is a schematic cross sectional view showing a structure of a silicon carbide substrate.
  • FIG. 3 is a flowchart schematically showing a method for manufacturing the MOSFET.
  • FIG. 4 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET.
  • FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET.
  • FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET.
  • FIG. 7 is a flowchart schematically showing a method for manufacturing the silicon carbide substrate.
  • FIG. 8 is a flowchart schematically showing a method for manufacturing a silicon carbide substrate in a second embodiment.
  • FIG. 9 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the second embodiment.
  • FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the second embodiment.
  • FIG. 11 is a schematic cross sectional view for illustrating a method for manufacturing a silicon carbide substrate in the second embodiment.
  • FIG. 12 is a schematic cross sectional view showing a structure of the silicon carbide substrate in a third embodiment.
  • FIG. 13 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a fourth embodiment.
  • FIG. 14 is a flowchart schematically showing a method for manufacturing the silicon carbide substrate in the fourth embodiment.
  • FIG. 15 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a fifth embodiment.
  • FIG. 16 is a flowchart schematically showing a method for manufacturing the silicon carbide substrate in the fifth embodiment.
  • FIG. 17 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a sixth embodiment.
  • FIG. 18 is a flowchart schematically showing a method for manufacturing the silicon carbide substrate in the sixth embodiment.
  • FIG. 19 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the sixth embodiment.
  • FIG. 20 shows a relation between impurity concentration and mobility in n type 4H—SiC.
  • a MOSFET 100 which is a semiconductor device in the present embodiment, includes: a silicon carbide substrate 1 having n type conductivity (first conductivity type); a buffer layer 2 made of silicon carbide and having n type conductivity; a drift layer 3 made of silicon carbide and having n type conductivity; a pair of well regions 4 each having p type conductivity (second conductivity type); n + regions 5 each serving as a source region having n type conductivity; and p + regions 6 each serving as a high-concentration second conductivity type region having p type conductivity.
  • Buffer layer 2 is formed on one main surface of silicon carbide substrate 1 , and contains an n type impurity and therefore has n type conductivity.
  • Drift layer 3 is formed on buffer layer 2 , and contains an n type impurity and therefore has n type conductivity.
  • the n type impurity contained in drift layer 3 is, for example, N (nitrogen), and is contained therein at a concentration (density) lower than that of the n type impurity contained in buffer layer 2 .
  • the pair of well regions 4 are formed in drift layer 3 to be separated from each other and include a main surface 3 A of drift layer 3 opposite to its main surface at the silicon carbide substrate 1 side.
  • Each of well regions 4 contains a p type impurity (impurity having p type conductivity) and therefore has p type conductivity (second conductivity type).
  • the p type impurity contained in well region 4 is, for example, aluminum (Al), boron (B), or the like.
  • N + regions 5 which include main surface 3 A as described above, are surrounded by well regions 4 and are formed within the pair of well regions 4 .
  • Each of n + regions 5 contains an n type impurity such as P at a concentration (density) higher than that of the n type impurity contained in drift layer 3 .
  • P + regions 6 which include main surface 3 A, are surrounded by well regions 4 and are formed adjacent to n + regions 5 within the pair of well regions 4 respectively.
  • Each of p + regions 6 contains a p type impurity such as Al at a concentration (density) higher than that of the p type impurity contained in each of well regions 4 .
  • Buffer layer 2 , drift layer 3 , well regions 4 , n + regions 5 , and p + regions 6 constitute an active layer 7 .
  • MOSFET 100 further includes: a gate oxide film 91 serving as a gate insulating film; a gate electrode 93 ; a pair of source contact electrodes 92 ; an interlayer insulating film 94 ; a source wire 95 ; and a drain electrode 96 .
  • Gate oxide film 91 is formed on and in contact with main surface 3 A of drift layer 3 so as to extend from a location on the upper surface of one n + region 5 to a location on the upper surface of the other n + region 5 .
  • Gate oxide film 91 is made of, for example, silicon dioxide (SiO 2 ).
  • Gate electrode 93 is disposed in contact with gate oxide film 91 so as to extend from a location over one n + region 5 to a location over the other n + region 5 . Further, gate electrode 93 is made of a conductor such as polysilicon having an impurity added therein or Al.
  • Source contact electrodes 92 are disposed in contact with main surface 3 A, extend from respective locations on the pair of n + regions 5 in the directions getting away from gate oxide film 91 , and reach locations on p + regions 6 .
  • Each of source contact electrodes 92 is made of a material capable of ohmic contact with n + regions 5 , such as Ni x Si y (nickel silicide).
  • Interlayer insulating film 94 is formed to surround gate electrode 93 over main surface 3 A of drift layer 3 , and extends from a location over one well region 4 to a location over the other well region 4 .
  • Interlayer insulating film 94 is made of, for example, silicon dioxide (SiO 2 ), which is an insulator.
  • Source wire 95 surrounds interlayer insulating film 94 over main surface 3 A of drift layer 3 , and extends onto the upper surfaces of source contact electrodes 92 .
  • Source wire 95 is made of a conductor such as Al, and is electrically connected to n + regions 5 via source contact electrodes 92 .
  • Drain electrode 96 is formed in contact with the main surface of silicon carbide substrate 1 opposite to the side at which drift layer 3 is formed. Drain electrode 96 is made of a material capable of ohmic contact with silicon carbide substrate 1 , such as Ni x Si y . Drain electrode 96 is electrically connected to silicon carbide substrate 1 .
  • MOSFET 100 when the drain electrode is fed with a voltage while gate electrode 93 has a voltage smaller than a threshold voltage, i.e., during the OFF state, a pn junction of well regions 4 and drift layer 3 just below gate oxide film 91 is reverse-biased. Accordingly, MOSFET 100 is in the non-conductive state.
  • gate electrode 93 when gate electrode 93 is fed with a positive voltage equal to or greater than the threshold voltage, an inversion layer is formed in a channel region near locations at which well regions 4 make contact with gate oxide film 91 .
  • n + regions 5 and drift layer 3 are electrically connected to one another, whereby a current flows between source wire 95 and drain electrode 96 .
  • silicon carbide substrate 1 constituting MOSFET 100 includes a base layer 10 made of silicon carbide, and a SiC layer 20 made of single-crystal silicon carbide and arranged on one main surface 10 A of base layer 10 .
  • Base layer 10 has an impurity concentration greater than 2 ⁇ 10 19 cm ⁇ 3
  • SiC layer 20 has an impurity concentration greater than 5 ⁇ 10 18 cm ⁇ 3 and smaller than 2 ⁇ 10 19 cm ⁇ 3 .
  • MOSFET 100 in the present embodiment is a semiconductor device allowing for reduced on-resistance while restraining stacking fault from being produced due to heat treatment in the device manufacturing process.
  • base layer 10 employed may be made of, for example, single-crystal silicon carbide, polycrystal silicon carbide, amorphous silicon carbide, a silicon carbide sintered compact, or a combination thereof.
  • base layer 10 may be made of single-crystal silicon carbide.
  • SiC layer 20 preferably has a micro pipe density smaller than that of base layer 10 .
  • SiC layer 20 preferably has a threading screw dislocation density smaller than that of base layer 10 .
  • SiC layer 20 preferably has a threading edge dislocation density smaller than that of base layer 10 .
  • SiC layer 20 preferably has a basal plane dislocation density smaller than that of base layer 10 .
  • SiC layer 20 preferably has a composite dislocation density smaller than that of base layer 10 .
  • SiC layer 20 preferably has a stacking fault density smaller than that of base layer 10 .
  • SiC layer 20 preferably has a point defect density smaller than that of base layer 10 .
  • SiC layer 20 has the reduced defect densities such as the micro pipe density, the threading screw dislocation density, the threading edge dislocation density, the basal plane dislocation density, the composite dislocation density, the stacking fault density, and the point defect density.
  • Such a SiC layer 20 allows a high-quality active layer 7 to be formed on SiC layer 20 .
  • base layer 10 is made of single-crystal silicon carbide, and the half width of X-ray rocking curve of SiC layer 20 may be smaller than that of base layer 10 .
  • a single-crystal silicon carbide having predetermined uniform shape and size and having relatively low crystallinity is employed as base layer 10 of silicon carbide substrate 1 , while a single-crystal silicon carbide having a high crystallinity and not having the desired shape or the like is effectively utilized as SiC layer 20 .
  • the manufacturing cost of the semiconductor device can be reduced.
  • main surface 20 A of SiC layer 20 opposite to base layer 10 preferably has an off angle of not less than 50° and no more than 65° relative to the ⁇ 0001 ⁇ plane. This restrains formation of interface state in the vicinity of an interface of active layer 7 with gate oxide film 91 , in the case where active layer 7 is formed by means of epitaxial growth and ion implantation of impurity, thereby achieving reduced on-resistance of MOSFET 100 .
  • the vicinity of the interface serves as a channel region.
  • main surface 20 A of SiC layer 20 opposite to base layer 10 has an off orientation forming an angle of 5° or smaller relative to the ⁇ 1-100> direction.
  • the ⁇ 1- 100>p0 direction is a representative off orientation in a silicon carbide substrate. Variation in the off orientation resulting from variation in a slicing process of the process of manufacturing the substrate is adapted to be 5° or smaller, which allows an epitaxial growth layer (active layer 7 ) to be formed readily on silicon carbide substrate 1 .
  • main surface 20 A of SiC layer 20 opposite to base layer 10 preferably has an off angle of not less than ⁇ 3° and not more than 5° relative to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction. Accordingly, channel mobility can be further improved in the case where MOSFET 100 is fabricated using silicon carbide substrate 1 .
  • main surface 20 A of SiC layer 20 opposite to base layer 10 may have an off orientation forming an angle of not more than 5° relative to the ⁇ 11-20> direction.
  • ⁇ 11-20> is a representative off orientation in a silicon carbide substrate, as with the ⁇ 1-100> direction. Variation in the off orientation resulting from variation in the slicing process of the process of manufacturing the substrate is adapted to be ⁇ 5° , which allows an epitaxial growth layer (active layer 7 ) to be formed readily on SiC layer 20 .
  • the impurity contained in base layer 10 may be different from that contained in SiC layer 20 .
  • MOSFET 100 can be obtained which includes silicon carbide substrate 1 containing impurities appropriately depending on intended purpose of use.
  • the impurity contained in base layer 10 may be nitrogen or phosphorus, whereas the impurity contained in SiC layer 20 may be also nitrogen or phosphorus.
  • a silicon carbide substrate preparing step is first performed as a step (S 110 ).
  • silicon carbide substrate 1 is prepared which includes base layer 10 made of single-crystal silicon carbide, and SiC layer 20 made of single-crystal silicon carbide and disposed on base layer 10 .
  • Base layer 10 has an impurity concentration greater than 2 ⁇ 10 19 cm ⁇ 3
  • SiC layer 20 has an impurity concentration greater than 5 ⁇ 10 18 cm ⁇ 3 and smaller than 2 ⁇ 10 19 cm ⁇ 3
  • the following base layer 10 may be employed instead of base layer 10 entirely formed of single-crystal silicon carbide. That is, base layer 10 employed includes: a single-crystal layer 10 B made of single-crystal silicon carbide and including main surface 10 A facing SiC layer 20 , and the other region 10 C made of polycrystal silicon carbide, amorphous silicon carbide, or a silicon carbide sintered compact.
  • base layer 10 instead of base layer 10 entirely made of single-crystal silicon carbide, there may be employed a base layer 10 entirely made of polycrystal silicon carbide, amorphous silicon carbide, or a silicon carbide sintered compact. A method for manufacturing silicon carbide substrate 1 will be described below.
  • buffer layer 2 and drift layer 3 each made of silicon carbide are sequentially formed on and over one main surface of silicon carbide substrate 1 by means of epitaxial growth.
  • an ion implantation step is performed.
  • ion implantation is first performed to form well regions 4 .
  • Al (aluminum) ions are implanted into drift layer 3 , thereby forming well regions 4 .
  • ion implantation is performed to form n + regions 5 .
  • P (phosphorus) ions are implanted into well regions 4 , thereby forming n + regions 5 within well regions 4 .
  • ion implantation is performed to form p + regions 6 .
  • Al ions are implanted into well regions 4 , thereby forming p + regions 6 within well regions 4 .
  • the ions can be implanted using a mask layer formed on the main surface of drift layer 3 , made of silicon dioxide (SiO 2 ), and having openings at desired regions for the ion implantation, for example.
  • an activation annealing step is performed.
  • heat treatment is performed by heating them to 1700° C. in an inert gas atmosphere such as argon for 30 minutes. Accordingly, the impurities implanted in the above-described step (S 130 ) are activated.
  • an oxide film forming step is performed.
  • this step (S 150 ) referring to FIG. 5 and FIG. 6 , for example, heat treatment is performed by heating to 1300° C. in an oxygen atmosphere for 60 minutes, thereby forming oxide film 91 (gate oxide film).
  • gate electrode 93 is formed by means of a CVD method, photolithography, and etching.
  • Gate electrode 93 is made of a conductor such as polysilicon having an impurity added therein at a high concentration, for example.
  • interlayer insulating film 94 made of SiO 2 that is an insulator is formed to surround gate electrode 93 over main surface 3 A.
  • portions of interlayer insulating film 94 and oxide film 91 are removed from the regions in which source electrodes 92 are to be formed.
  • a nickel (Ni) film is formed by means of an evaporation method and is heated to be silicided, thereby forming source contact electrodes 92 and drain electrode 96 .
  • source wire 95 made of Al that is a conductor is formed to surround interlayer insulating film 94 over main surface 3 A and extend to the locations over and on the upper surfaces of n + regions 5 and source contact electrodes 92 .
  • step (S 110 ) base layer 10 that includes single-crystal layer 10 B made of single-crystal silicon carbide and including main surface 10 A facing SiC layer 20 and that includes the other region 10 C made of polycrystal silicon carbide, amorphous silicon carbide, or silicon carbide sintered compact
  • a step of removing the other region 10 C may be performed.
  • MOSFET 100 including base layer 10 made of single-crystal silicon carbide can be obtained (see FIG. 1 ). Meanwhile, the step of removing region 10 C described above may not be performed.
  • a non single-crystal layer (corresponding to region 10 C described above) made of polycrystal silicon carbide, amorphous silicon carbide, or silicon carbide sintered compact is formed on the main surface of base layer 10 opposite to SiC layer 20 in MOSFET 1 shown in FIG. 1 (i.e., as a lower layer in base layer 10 in FIG. 1 ).
  • This non single-crystal layer does not have great influence over the characteristics of MOSFET 100 as long as the resistivity thereof is low. Hence, when such a manufacturing process is employed, manufacturing cost of MOSFET 100 can be reduced without great influence over the characteristics thereof.
  • the half width of X-ray rocking curve of SiC layer 20 may be smaller than that of single-crystal layer 10 B.
  • SiC layer 20 having such a smaller half width of the X-ray rocking curve, i.e., having higher crystallinity than that of single-crystal layer 10 B of base layer 10 is provided, thereby allowing a high-quality active layer 7 to be formed on SiC layer 20 .
  • SiC layer 20 may have a micro pipe density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 may have a dislocation density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 may have a threading screw dislocation density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 may have a threading edge dislocation density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 may have a basal plane dislocation density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 has a composite dislocation density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 may have a stacking fault density smaller than that of single-crystal layer 10 B. Further, SiC layer 20 may have a point defect density smaller than that of single-crystal layer 10 B.
  • SiC layer 20 has the reduced defect densities such as the micro pipe density, the threading screw dislocation density, the threading edge dislocation density, the basal plane dislocation density, the composite dislocation density, the stacking fault density, and the point defect density. Accordingly, MOSFET 100 including high-quality layer 7 can be obtained.
  • step (S 10 ) the substrate preparing step is performed.
  • step (S 10 ) base substrate 10 formed of single-crystal silicon carbide and SiC substrate 20 formed of single-crystal silicon carbide are prepared.
  • SiC substrate 20 has main surface 20 A, which will be the main surface of silicon carbide substrate 1 that will be obtained by this manufacturing method.
  • the plane orientation of main surface 20 A of SiC substrate 20 is selected in accordance with desired plane orientation of main surface 20 A.
  • a SiC substrate 20 having a main surface corresponding to the ⁇ 03-38 ⁇ plane is prepared.
  • a substrate having an impurity concentration greater than 2 ⁇ 10 19 cm ⁇ 3 is adopted as base substrate 10 .
  • a substrate is employed which has an impurity concentration greater than 5 ⁇ 10 18 cm ⁇ 3 and smaller than 2 ⁇ 10 19 cm ⁇ 3 .
  • Step (S 20 ) is not an essential step, but can be performed when the smoothness of base substrate 10 and/or SiC substrate 20 prepared in step (S 10 ) is insufficient. Specifically, for example, the main surface(s) of base substrate 10 and/or SiC substrate 20 are polished.
  • step (S 20 ) may be omitted, i.e., step (S 30 ) may be performed without polishing the main surfaces of base substrate 10 and SiC substrate 20 , which are to be brought into contact with each other. This reduces manufacturing cost of silicon carbide substrate 1 .
  • a step of removing the damaged layers may be performed by, for example, etching instead of step (S 20 ) or after step (S 20 ), and then step (S 30 ) described below may be performed.
  • step (S 30 ) a stacking step is performed as step (S 30 ).
  • step (S 30 ) referring to FIG. 2 , base substrate 10 and SiC substrate 20 are stacked on each other to bring their main surfaces 10 A, 20 B into contact with each other, thereby fabricating a stacked substrate.
  • step (S 40 ) a connecting step is performed.
  • step (S 40 ) by heating the stacked substrate to fall within, for example, a range of temperature equal to or greater than the sublimation temperature of silicon carbide, base substrate 10 and SiC substrate 20 are connected to each other. In this way, referring to FIG. 2 , silicon carbide substrate 1 including base layer 10 and SiC layer 20 is completed. Further, by heating to the temperature equal to or greater than the sublimation temperature, base substrate 10 and SiC substrate 20 can be connected to each other readily even in the case where step (S 20 ) is not performed and step (S 30 ) is performed without polishing the main surfaces of base substrate 10 and SiC substrate 20 which are to be brought into contact with each other. It should be noted that in this step (S 40 ), the stacked substrate may be heated in an atmosphere obtained by reducing pressure of the atmospheric air. This reduces manufacturing cost of silicon carbide substrate 1 .
  • heating temperature for the stacked substrate in step (S 40 ) is preferably not less than 1800° C. and not more than 2500° C. If the heating temperature is lower than 1800° C., it takes a long time to connect base substrate 10 and SiC substrate 20 , which results in decreased efficiency in manufacturing silicon carbide substrate 1 . On the other hand, if the heating temperature exceeds 2500° C., surfaces of base substrate 10 and SiC substrate 20 become rough, which may result in generation of a multiplicity of crystal defects in silicon carbide substrate 1 to be fabricated. In order to improve efficiency in manufacturing while restraining generation of defects in silicon carbide substrate 1 , the heating temperature for the stacked substrate in step (S 40 ) is set at not less than 1900° C. and not more than 2100° C.
  • the stacked substrate may be heated under a pressure higher than 10 ⁇ 1 Pa and lower than 10 4 Pa.
  • the atmosphere upon the heating in step (S 40 ) may be inert gas atmosphere.
  • the atmosphere is the inert gas atmosphere
  • the inert gas atmosphere preferably contains at least one selected from a group consisting of argon, helium, and nitrogen.
  • MOSFET 100 is manufactured using silicon carbide substrate 1 thus obtained.
  • the following describes another method for manufacturing the silicon carbide substrate constituting the semiconductor device of the present invention with reference to FIG. 8-FIG . 11 .
  • a method for manufacturing a silicon carbide substrate in the second embodiment is performed in basically the same manner as in the first embodiment.
  • the method for manufacturing the silicon carbide substrate in the second embodiment is different from that of the first embodiment in terms of a process of forming base substrate 10 .
  • the substrate preparing step is first performed as step (S 10 ) in the method for manufacturing the silicon carbide substrate in the second embodiment.
  • step (S 10 ) SiC substrate 20 is prepared as with the first embodiment, and a material substrate 11 made of silicon carbide is prepared.
  • Material substrate 11 may be made of single-crystal silicon carbide or polycrystal silicon carbide, or may be a sintered compact of silicon carbide. Further, instead of material substrate 11 , material powder made of silicon carbide can be employed.
  • a closely arranging step is performed.
  • SiC substrate 20 and material substrate 11 are held by a first heater 81 and a second heater 82 disposed face to face with each other.
  • an appropriate value of a space between SiC substrate 20 and material substrate 11 is considered to be associated with a mean free path for a sublimation gas obtained upon heating in a below-described step (S 60 ).
  • the average value of the space between SiC substrate 20 and material substrate 11 can be set to be smaller than the mean free path for the sublimation gas obtained upon heating in the below-described step (S 60 ).
  • a mean free path for atoms and molecules depends on atomic radius and molecule radius at a pressure of 1 Pa and a temperature of 2000° C., but is approximately several cm to several ten cm.
  • the space is preferably set at several cm or smaller. More specifically, SiC substrate 20 and material substrate 11 are arranged close to each other such that their main surfaces face each other with a space of not less than 1 ⁇ m and not more than 1 cm therebetween. When the average value of the space is 1 cm or smaller, distribution in film thickness of base layer 10 can be reduced in the below-described step (S 60 ).
  • this sublimation gas is a gas formed by sublimation of solid silicon carbide, and includes Si, Si 2 C, and SiC 2 , for example.
  • step (S 60 ) a sublimation step is performed.
  • SiC substrate 20 is heated to a predetermined substrate temperature by first heater 81 .
  • material substrate 11 is heated to a predetermined material temperature by second heater 82 .
  • material substrate 11 is heated to reach the material temperature, thereby sublimating SiC from the surface of the material substrate.
  • the substrate temperature is set lower than the material temperature. Specifically, for example, the substrate temperature is set lower than the material temperature by not less than 1° C. and not more than 100° C.
  • the substrate temperature is preferably 1800° C. or greater and 2500° C. or smaller. Accordingly, as shown in FIG.
  • step (S 60 ) is completed, thereby completing silicon carbide substrate 1 shown in FIG. 2 .
  • a semiconductor device in the third embodiment has basically the same structure as that in the first embodiment. However, the semiconductor device of the third embodiment is different from that of the first embodiment in terms of its manufacturing method.
  • a silicon carbide substrate different in structure from that of the first embodiment is prepared in the silicon carbide substrate preparing step performed as step (S 110 ) in the method for manufacturing the semiconductor device (for example, MOSFET) in the third embodiment.
  • the semiconductor device for example, MOSFET
  • a plurality of SiC layers 20 are arranged side by side when viewed in a planar view.
  • the plurality of SiC layers 20 are arranged along main surface 10 A of base layer 10 .
  • the plurality of SiC layers 20 are arranged in the form of a matrix on base layer 10 such that adjacent SiC layers 20 are in contact with each other.
  • silicon carbide substrate 1 of the present embodiment can be handled as a substrate having high-quality SiC layers 20 and a large diameter. Utilization of such a silicon carbide substrate 1 allows for efficient manufacturing process of semiconductor devices. Further, referring to FIG. 12 , each of adjacent SiC layers 20 has an end surface 20 C substantially perpendicular to main surface 20 A of SiC layer 20 . In this way, silicon carbide substrate 1 of the present embodiment can be readily manufactured. Here, for example, when end surface 20 C and main surface 20 A form an angle of not less than 85° and not more than 95°, it can be determined that end surface 20 C and main surface 20 A are substantially perpendicular to each other.
  • silicon carbide substrate 1 in the third embodiment can be manufactured in a manner similar to that in the first embodiment or the second embodiment as follows. That is, in step (S 30 ) of the first embodiment, a plurality of SiC substrates 20 each having an end surface 20 C substantially perpendicular to main surface 20 A thereof are arranged side by side when viewed in a planar view (see FIG. 2 ). Alternatively, in step (S 50 ) of the second embodiment, a plurality of SiC substrates 20 each having an end surface 20 C substantially perpendicular to main surface 20 A thereof are arranged side by side on and held by first heater 81 (see FIG. 9 ).
  • MOSFET 100 is manufactured using silicon carbide substrate 1 thus obtained.
  • active layer 7 and the like on SiC layers 20 of silicon carbide substrate 1 shown in FIG. 12 .
  • each MOSFET 100 is fabricated so as not to extend across a boundary region between adjacent SiC layers 20 .
  • a MOSFET 100 (semiconductor device) in the fourth embodiment has basically the same structure and provides basically the same effects as those of MOSFET 100 in the first embodiment.
  • MOSFET 100 in the fourth embodiment is different from that of the first embodiment in terms of structure of silicon carbide substrate 1 .
  • an amorphous SiC layer 40 is disposed between base layer 10 and SiC layer 20 as an intermediate layer made of amorphous SiC. Then, base layer 10 and SiC layer 20 are connected to each other by this amorphous SiC layer 40 .
  • Amorphous SiC layer 40 thus existing facilitates fabrication of silicon carbide substrate 1 in which base layer 10 and SiC layer 20 different in impurity concentration are stacked on each other.
  • the substrate preparing step is performed as step (S 10 ) in the same way as in the first embodiment, so as to prepare base substrate 10 and SiC substrate 20 .
  • a Si layer forming step is performed as a step (S 11 ).
  • a Si layer having a thickness of 100 nm is formed on one main surface of base substrate 10 prepared in step (S 10 ), for example.
  • This Si layer can be formed using a sputtering method, for example.
  • step (S 30 ) SiC substrate 20 prepared in step (S 10 ) is placed on the Si layer formed in step (S 11 ). In this way, a stacked substrate is obtained in which SiC substrate 20 is provided over base substrate 10 with the Si layer interposed therebetween.
  • a heating step is performed.
  • the stacked substrate fabricated in step (S 30 ) is heated, for example, in a mixed gas atmosphere of hydrogen gas and propane gas under a pressure of 1 ⁇ 10 3 Pa at approximately 1500° C. for 3 hours.
  • the Si layer is supplied with carbon as a result of diffusion mainly from base substrate 10 and SiC substrate 20 , thereby forming amorphous SiC layer 40 as shown in FIG. 13 .
  • silicon carbide substrate 1 of the fourth embodiment can be readily manufactured in which base layer 10 and SiC layer 20 different in impurity concentration are connected to each other by amorphous SiC layer 40 .
  • a MOSFET 100 (semiconductor device) in the fifth embodiment has basically the same structure and provides basically the same effects as those of MOSFET 100 in the first embodiment.
  • MOSFET 100 in the fifth embodiment is different from that of the first embodiment in terms of structure of silicon carbide substrate 1 .
  • silicon carbide substrate 1 of the fifth embodiment is different from that of the first embodiment in that an ohmic contact layer 50 is formed between base layer 10 and SiC layer 20 as an intermediate layer obtained by siliciding at least a part of a metal layer. Then, base layer 10 and SiC layer 20 are connected to each other by this ohmic contact layer 50 .
  • Ohmic contact layer 50 thus existing facilitates fabrication of silicon carbide substrate 1 in which base layer 10 and SiC layer 20 different in impurity concentration are stacked on each other.
  • the substrate preparing step is performed as step (S 10 ) in the same way as in the first embodiment, so as to prepare base substrate 10 and SiC substrate 20 .
  • a metal film forming step is performed as a step (S 12 ).
  • the metal film is formed by, for example, depositing the metal on one main surface of base substrate 10 prepared in step (S 10 ).
  • This metal film contains a metal which forms silicide by, for example, heating.
  • the metal film contains at least one or more of nickel, molybdenum, titanium, aluminum, and tungsten.
  • step (S 30 ) SiC substrate 20 prepared in step (S 10 ) is placed on the metal film formed in step (S 12 ). In this way, a stacked substrate is obtained in which SiC substrate 20 is provided over base substrate 10 with the metal film interposed therebetween.
  • a heating step is performed.
  • the stacked substrate fabricated in step (S 30 ) is heated to approximately 1000° C. in an inert gas atmosphere such as argon, for example. Accordingly, at least part of the metal film (its region in contact with base substrate 10 and its region in contact with the SiC substrate) is silicided, thereby forming ohmic contact layer 50 making ohmic contact with base layer 10 and SiC layer 20 . Accordingly, silicon carbide substrate 1 of the fifth embodiment can be readily manufactured in which base layer 10 and SiC layer 20 different in impurity concentration are connected to each other by ohmic contact layer 50 .
  • a MOSFET 100 (semiconductor device) in the sixth embodiment has basically the same structure and provides basically the same effects as those of MOSFET 100 in the first embodiment.
  • MOSFET 100 in the sixth embodiment is different from that of the first embodiment in terms of structure of silicon carbide substrate 1 .
  • silicon carbide substrate 1 of the sixth embodiment is different from that of the first embodiment in that a carbon layer 60 is formed between base layer 10 and SiC layer 20 as an intermediate layer. Then, base layer 10 and SiC layer 20 are connected to each other by this carbon layer 60 .
  • Carbon layer 60 thus existing facilitates fabrication of silicon carbide substrate 1 in which base layer 10 and SiC layer 20 different in impurity concentration are stacked on each other.
  • step (S 10 ) is performed in the same way as in the first embodiment, and then step (S 20 ) is performed as required in the same way as in the first embodiment.
  • an adhesive agent applying step is performed.
  • a carbon adhesive agent is applied to the main surface of base substrate 10 , thereby forming a precursor layer 61 .
  • the carbon adhesive agent can be formed of, for example, a resin, graphite particles, and a solvent.
  • an exemplary resin usable is a resin formed into non-graphitizable carbon by heating, such as a phenol resin.
  • An exemplary solvent usable is phenol, formaldehyde, ethanol, or the like.
  • the carbon adhesive agent is preferably applied at an amount of not less than 10 mg/cm 2 and not more than 40 mg/cm 2 , more preferably, not less than 20 mg/cm 2 and not more than 30 mg/cm 2 . Further, the carbon adhesive agent applied preferably has a thickness of not more than 100 ⁇ m, more preferably, not more than 50 ⁇ m.
  • step (S 30 ) a stacking step is performed as step (S 30 ).
  • SiC substrate 20 is placed on and in contact with precursor layer 61 formed on and in contact with the main surface of base substrate 10 , thereby fabricating a stacked substrate.
  • a prebake step is performed.
  • the stacked substrate is heated, thereby removing the solvent component from the carbon adhesive agent constituting precursor layer 61 .
  • the stacked substrate is gradually heated to fall within a range of temperature exceeding the boiling point of the solvent component.
  • this heating is performed with base substrate 10 and SiC substrate 20 being pressed against each other using a clamp or the like.
  • the adhesive agent is degassed to improve strength in adhesion.
  • a firing step is performed.
  • the stacked substrate with precursor layer 61 heated and accordingly prebaked in step (S 80 ) are heated to a high temperature, preferably, not less than 900° C. and not more than 1100° C., for example, 1000° C. for preferably not less than 10 minutes and not more than 10 hours, for example, for 1 hour, thereby firing precursor layer 61 .
  • Atmosphere employed upon the firing can be an inert gas atmosphere such as argon.
  • the pressure of the atmosphere can be, for example, atmospheric pressure.
  • precursor layer 61 is formed into a carbon layer 60 made of carbon.
  • silicon carbide substrate 1 of the sixth embodiment is obtained in which base substrate (base layer) 10 and SiC substrate (SiC layer) 20 are connected to each other by carbon layer 60 .
  • the vertical type MOSFET has been illustrated as one exemplary semiconductor device of the present invention, but the semiconductor device of the present invention is not limited to this and is widely applicable to vertical type semiconductor devices in each of which a current flows in the thickness direction of the silicon carbide substrate.
  • the crystal structure of silicon carbide constituting SiC layer 20 is preferably of hexagonal system, more preferably, 4H—SiC.
  • base layer 10 and SiC layer 20 are preferably made of silicon carbide single-crystal having the same crystal structure.
  • the silicon carbide single-crystals respectively constituting SiC layer 20 and base layer 10 preferably have c axes forming an angle of less than 1°, more preferably, less than 0.1°. Further, it is preferable that the c planes of the respective silicon carbide single-crystals thereof are not displaced from each other in the plane.
  • base layer (base substrate) 10 of silicon carbide substrate 1 used to manufacture the semiconductor device such as MOSFET 100 preferably has a diameter of 2 inches or greater, more preferably, 6 inches or greater.
  • silicon carbide substrate 1 preferably has a thickness of not less than 200 ⁇ m and not more than 1000 ⁇ m, more preferably, not less than 300 ⁇ m and not more than 700 ⁇ m.
  • SiC layer 20 preferably has a resistivity of 50 m ⁇ cm or smaller, more preferably, 20 m ⁇ cm or smaller.
  • MOSFET 100 of the first embodiment employs silicon carbide substrate 1 including: base layer 10 having a thickness of 200 ⁇ m and having an n type impurity density of 1 ⁇ 10 20 cm ⁇ 3 ; and SiC layer 20 having a thickness of 200 ⁇ m and having an n type impurity density of 1 ⁇ 10 19 cm ⁇ 3 , wherein SiC layer 20 has a main surface facing active layer 7 and corresponding to the ⁇ 03-38 ⁇ plane (example A).
  • on-resistance of a conventional MOSFET was also determined (comparative example A).
  • the conventional MOSFET employs a silicon carbide substrate having a thickness of 400 ⁇ m, having an n type impurity density of 1 ⁇ 10 19 cm ⁇ 3 , and having a main surface facing its active layer and corresponding to the ⁇ 0001 ⁇ plane.
  • the channel length was set at 1.0 ⁇ m
  • the drift layer was set to have a thickness of 10 ⁇ m and was set to have an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 .
  • the substrate resistance and the drift resistance of the drift layer i.e., series resistance, were determined as follows. That is, first, the following relation is established, assuming that electron density is represented by n n0 , positive hole density is represented by p p0 , effective density of states of electrons is represented by N c , and effective density of states of positive holes is represented by N v .
  • resistance R of the substrate can be determined by the following formula:
  • contact resistance R c exponentially depends on ⁇ bn /(N d 1/2 ). By increasing impurity concentration (impurity density) N d , contact resistance R c can be reduced.
  • a contact resistance was determined between an electrode and a substrate (base layer) having an impurity concentration of 1 ⁇ 10 20 cm ⁇ 3 (example B).
  • a contact resistance was determined between an electrode and a substrate having an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 (comparative example B).
  • an exemplary, usable metal constituting the electrode includes Ni (nickel) having a work function ⁇ of 5.5 eV or Al (aluminum) having a work function ⁇ of 4.1 eV.
  • Ni nickel
  • Al aluminum
  • the contact resistance in example C for the semiconductor device of the present invention is reduced by approximately 40% as compared with the contact resistance in comparative example C for the conventional semiconductor device.
  • the contact resistance can be significantly reduced between the substrate and the electrode (backside electrode).
  • heat treatment is usually performed after formation of the electrode in order to reduce the contact resistance, but according to the semiconductor device of the present invention, the heat treatment may not be performed.
  • the semiconductor device of the present invention is not limited to this and may be, for example, a JFET (Junction Field Effect Transistor), a MESFET (Metal Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a diode or the like.
  • JFET Joint Field Effect Transistor
  • MESFET Metal Semiconductor Field Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • a semiconductor device of the present invention is advantageously applicable to a vertical type semiconductor device required to allow for reduced on-resistance.

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US20130175538A1 (en) * 2012-01-11 2013-07-11 Samsung Electronics Co., Ltd. Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device
US8921890B2 (en) * 2012-01-11 2014-12-30 Samsung Electronics Co., Ltd. Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device
US9048093B2 (en) 2012-03-21 2015-06-02 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device
US9583346B2 (en) 2013-11-08 2017-02-28 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor device
US20150236098A1 (en) * 2014-02-17 2015-08-20 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9793354B2 (en) * 2014-02-17 2017-10-17 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9601581B2 (en) * 2014-03-20 2017-03-21 Kabushiki Kaisha Toshiba Semiconductor device and method for producing the same
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US11004941B2 (en) * 2015-11-24 2021-05-11 Sumitomo Electric Industries, Ltd. Silicon carbide epitaxial substrate having grooves extending along main surface and method of manufacturing silicon carbide semiconductor device
US20180277636A1 (en) * 2017-03-24 2018-09-27 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for manufacturing the same
US10211293B2 (en) * 2017-03-24 2019-02-19 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for manufacturing the same
US10355091B2 (en) 2017-03-24 2019-07-16 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for manufacturing the same

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CN102422424A (zh) 2012-04-18
KR20120014017A (ko) 2012-02-15
EP2432020A1 (fr) 2012-03-21
CA2735975A1 (fr) 2010-11-18
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JPWO2010131573A1 (ja) 2012-11-01
US20120056201A1 (en) 2012-03-08
EP2432002A1 (fr) 2012-03-21
US20120061686A1 (en) 2012-03-15
US20120061687A1 (en) 2012-03-15
CN102422425A (zh) 2012-04-18
EP2432000A1 (fr) 2012-03-21
KR20120023710A (ko) 2012-03-13
WO2010131573A1 (fr) 2010-11-18
EP2432002A4 (fr) 2012-11-21
CN102422388A (zh) 2012-04-18
TW201120939A (en) 2011-06-16
TW201101484A (en) 2011-01-01
CA2761430A1 (fr) 2010-11-18
CN102160143A (zh) 2011-08-17
JPWO2010131569A1 (ja) 2012-11-01
CA2761246A1 (fr) 2010-11-18
KR20120014024A (ko) 2012-02-15
EP2432001A4 (fr) 2012-11-21
CN102422387A (zh) 2012-04-18
WO2010131570A1 (fr) 2010-11-18
JP5477380B2 (ja) 2014-04-23
KR20120024526A (ko) 2012-03-14
CA2761245A1 (fr) 2010-11-18
CA2761428A1 (fr) 2010-11-18
WO2010131569A1 (fr) 2010-11-18
CN102160143B (zh) 2013-05-29
TW201104861A (en) 2011-02-01
JPWO2010131568A1 (ja) 2012-11-01
JPWO2010131572A1 (ja) 2012-11-01
EP2432020A4 (fr) 2013-06-26
KR20120011059A (ko) 2012-02-06
JPWO2010131570A1 (ja) 2012-11-01
TW201101482A (en) 2011-01-01
US20110165764A1 (en) 2011-07-07
US8168515B2 (en) 2012-05-01
TW201104865A (en) 2011-02-01
JP5344037B2 (ja) 2013-11-20
WO2010131568A1 (fr) 2010-11-18
WO2010131572A1 (fr) 2010-11-18
EP2432000A4 (fr) 2012-11-21
EP2432022A1 (fr) 2012-03-21

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