TWI476815B - 於半導體結構中形成分離主動區域、渠溝及導線之方法以及包含其之半導體結構 - Google Patents

於半導體結構中形成分離主動區域、渠溝及導線之方法以及包含其之半導體結構 Download PDF

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TWI476815B
TWI476815B TW098113229A TW98113229A TWI476815B TW I476815 B TWI476815 B TW I476815B TW 098113229 A TW098113229 A TW 098113229A TW 98113229 A TW98113229 A TW 98113229A TW I476815 B TWI476815 B TW I476815B
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forming
consumable material
substrate
consumable
trenches
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TW200952041A (en
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Kunal R Parekh
John K Zahurak
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Micron Technology Inc
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Description

於半導體結構中形成分離主動區域、渠溝及導線之方法以及包含其之半導體結構
本發明之實施例係關於積體電路製造，且更具體言之，係關於在半導體結構上形成不對稱特徵之方法及包含不對稱特徵之半導體結構。
由於許多因素(包含針對現代電子儀器中之增加攜帶性、計算能力、記憶體容量及能量效率的需求)，積體電路之大小正持續地減小。為了促進此大小減小，形成積體電路之組成特徵(諸如，電力裝置及互連線寬度)之大小亦正不斷地減小。
特徵大小之持續減小對用以形成特徵之技術寄予愈來愈大的需求。舉例而言，光微影為在基板上圖案化特徵(諸如，導線)之習知方法。可使用間距概念來描述此等特徵之大小。可將間距界定為兩個相鄰特徵中之相同點之間的距離。此等特徵通常係由鄰近特徵之間的間隔界定，間隔可由諸如絕緣體之材料填充。結果，可將間距視為特徵之寬度與將彼特徵與相鄰特徵隔離之空間之寬度的總和，或特徵之一邊緣與下一鄰近特徵之對應相同邊緣之間的距離。然而，歸因於諸如光學儀器及光或輻射波長之因素，光微影技術具有一最小間距，在低於該最小間距時，特定光微影技術不能可靠地形成特徵。因此，光微影技術之最小間距可限制特徵大小減小。
已提議間距加倍或間距倍增技術以用於延伸光微影技術之能力。間距倍增方法之一實例係說明於本文中之圖1A至圖1F中且描述於頒予Lowrey等人之美國專利第5,328,810號中，該專利之全部揭示係以引用之方式併入本文中。參看圖1A，可首先使用光微影以在上覆於消耗性材料層20及基板30之光阻材料中形成線10之圖案。如圖1B所示，可接著藉由蝕刻步驟(較佳地為各向異性)而將圖案轉印至層20，從而形成替代符號(placeholder)或心軸40。如圖1C所示，可剝離線10且可各向同性地蝕刻心軸40以增加相鄰心軸40之間的距離。如圖1D所示，可隨後將材料層50沈積於心軸40上。如圖1E所示，可接著藉由以指向間隔物蝕刻來優先自水平表面70及80蝕刻間隔物材料而在心軸40之側壁上形成間隔物60，亦即，自另一材料之側壁延伸或原先自另一材料之側壁延伸而形成的材料。如圖1F所示，可接著移除剩餘心軸40，從而留下獨立間隔物60。如圖1F所示，間隔物60充當用於圖案化下伏層之蝕刻遮罩。因此，在給定間距先前包含界定一個特徵及一個空間之圖案的情況下，相同寬度現包含兩個特徵及兩個空間。結果，在光微影技術下為可能的最小特徵大小有效地減小。
然而，習知間距加倍過程係受限制的，此在於：其不能可靠地用以將(例如)對稱性係由於場區域上之通過字線之移除而破壞之DRAM陣列中的不對稱特徵進行間距加倍。在陣列閘極圖案化級下出現問題，因為需要在一間距上界定三個特徵：場上之兩個字線及一接地閘極。場上之接地閘極平衡圖案密度以及確保可執行線性自對準接觸蝕刻以形成用於將插塞傳導至儲存及位元接觸主動區域之空腔。習知間距加倍在此情況下不有效，因為關於所有其他經圖案化形式之經間距加倍特徵不會界定用於字線相對於字線及接地閘極之正確間隙。因此，在此項技術中存在針對將不對稱特徵進行間距加倍之方法及包含此等次微影特徵之半導體結構的持續需要。
以下描述參看圖式而提供本發明之裝置及方法之實施例的說明性實例。此描述僅係出於說明性目的且並非限制本發明之範疇。本文中所呈現之圖式未必按比例繪製且不為特定半導體結構或其製造過程之實際視圖，而僅為用以描述本發明之實施例的理想化表示。一般熟習此項技術者應理解，可根據本發明而實施裝置及方法之其他實施例。
本發明揭示包含至少一不對稱次微影特徵之半導體結構，同時揭示形成此等半導體結構之方法。間距加倍過程可用以在基板上形成分離主動區域。不對稱特徵可破壞基板上之線與空間之間的對稱性。如本文中詳細地所描述且如圖3至圖10B所說明，可在基板上形成遮罩材料且在基板上於第一方向上將遮罩材料圖案化以形成主動區域圖案。可形成主動區域遮罩且在基板上於大體上垂直方向上將主動區域遮罩圖案化且在鄰近於其而形成間隔物之後將其移除。間隔物可在後續蝕刻期間充當遮罩，使得在間隔物之間形成第一渠溝以分離基板上之主動區域。
隨後，可在基板上形成凹入存取裝置(RAD)渠溝。如本文中詳細地所描述且如圖11A至圖15所說明，可在分離主動區域上形成多種遮罩材料且將其圖案化。可鄰近於遮罩材料而形成間隔物，且在移除間隔物之後，遮罩材料可在後續蝕刻期間充當遮罩以形成次微影渠溝。藉由非限制性實例，渠溝可為記憶體陣列之RAD渠溝、FIN渠溝、雙FIN渠溝或字線。
接著，可在基板上形成記憶體陣列之導線及接地閘極。如本文中詳細地所描述且如圖16A至圖20所說明，可在渠溝上方形成交替遮罩材料及間隔物且將其圖案化。可移除遮罩材料，且間隔物可在後續蝕刻期間充當遮罩以形成與渠溝之連接。
以下描述提供特定細節(諸如，材料類型、蝕刻化學物及處理條件)，以便提供本發明之實施例的詳盡描述。然而，一般熟習此項技術者應理解且瞭解，可在不使用此等特定細節之情況下實踐本發明之此等及其他實施例。實際上，可結合工業中所使用之習知製造技術及蝕刻技術來實踐本發明之實施例，因此，未在本文中對其加以詳細地描述。此外，下文中所提供之描述不形成用於製造半導體裝置之完整過程流程。本文中所描述之半導體結構不形成完整半導體裝置。下文僅詳細地描述為理解本發明之實施例所必要的彼等過程動作及半導體結構。用以自半導體結構形成完整半導體裝置之額外動作可藉由習知製造技術而執行，因此，未在本文中對其加以描述。
本文中所描述之方法可用以形成記憶體裝置(諸如，動態隨機存取記憶體(DRAM))之半導體結構，包含RAD特徵、FinFET、鞍形FET、奈米線、三維電晶體，以及其他三維半導體裝置特徵。併有此等結構之記憶體裝置或其他半導體裝置可用於(無限制)無線裝置、個人電腦或其他電子裝置中。藉由非限制性實例，本文中之方法描述製造記憶體裝置(諸如，DRAM記憶體裝置或RAD記憶體裝置)之半導體結構。雖然本文中之方法描述製造記憶體裝置之半導體結構，但該等方法亦可在需要不對稱特徵之間距加倍的其他情形下使用。此外，雖然參考6F2 DRAM裝置組態或布局而說明本文中所描述之方法，但該等方法可用以形成具有其他布局(諸如(例如)，4F2 或8F2 布局)之DRAM裝置或其他半導體裝置，只要分離區域係大體上平行於最終將形成電晶體閘極之位置即可。
本發明之實施例可包含將特徵進行間距加倍，以形成主動區域、在6F2 記憶體陣列之閘極中形成渠溝及/或形成與閘極之連接。圖2展示6F2 記憶體陣列之電路布局之一部分的簡化圖，該記憶體陣列在本文中被稱為包含基板110之記憶體陣列100。可相對於基板110而形成複數個連續主動區域112。為了清楚起見，已將每一所說明連續主動區域112展示成在基板110之邊界外部延伸。連續主動區域112通常為非線性的，其在大體上水平方向上遵循跨越記憶體陣列100之蜿蜒蛇形路徑。將複數個內埋式位元線118展示為大致水平地跨越記憶體陣列100而延伸之陰影區域。每一位元線118亦遵循跨越記憶體陣列100之蜿蜒蛇形路徑，其中位元線118之蜿蜒蛇形迂迴穿行(weave)相對於連續主動區域112之迂迴穿行係在相反方向上。
可在基板110上相對於主動區域112而形成複數個導線120、134。在圖2中，將導線中之六者表示為120，而將導線中之兩者表示為134。可在導線134之任一側上形成一對導線120。導線120、134相對於主動區域112而大體上垂直地延行。
藉由經表示為數字125之虛線輪廓來說明由根據所描繪記憶體陣列之單一記憶體單元所佔用的個別區域。此區域可被認為或描述為關於尺寸「F」，其為最小特徵大小。在所說明實例中，F等於記憶體陣列之「最小間距」的一半。本文中所使用之術語「間距」意欲用於其習知用法中，且(如先前所提及)可被界定為裝置或特徵之一邊緣與下一鄰近裝置或特徵之對應相同邊緣之間的距離。因此，關於記憶體單元125，術語「最小間距」約等於線寬(諸如，導線120、134)加在導線120之於導線120與下一鄰近導線120(在記憶體單元125內之重複圖案中)之間的一側上緊鄰於導線120之空間之寬度的最小距離。如所展示，單一記憶體單元125為約3F寬乘約2F深，因此向單一記憶體單元125提供約6F2 之佔用面積。
在記憶體陣列100(諸如，圖2所描繪之記憶體陣列)之實施之實例中，選定個別導線可相對於鄰近記憶體單元125而提供電分離。舉例而言，如所描繪，導線120相對於個別記憶體單元125而用作字線。鄰近對之記憶體單元125之間的電分離係由插入導線134提供，導線134在操作中可與接地或合適負電壓連接。或者，可利用場氧化物分離技術。
圖2所描繪之記憶體陣列100可另外包含電容器容器136及位元線觸點138。電容器通常可形成於電容器容器136內且可經由儲存節點觸點140而耦接至主動區域。在特定態樣中，儲存節點觸點140可包含延伸至主動區域之節點部分的導電材料。
參看圖2應注意，所描繪之電容器容器136具有大體上等於記憶體單元125之間距的間距。換言之，每一電容器容器136之寬度(在頁面上之垂直方向上)加緊鄰之電容器容器之間的空間之寬度(在頁面上之垂直方向上)大體上等於圖案間距「P」，其中P為線寬「W」加緊鄰於該線之空間「S」之寬度的總和，如圖2所描繪。
為了形成圖2所描繪之記憶體陣列100，結合上覆於基板110之材料的大體上垂直蝕刻而使用遮罩材料以在基板110中或在基板110上形成自對準特徵。如本文中所使用，「自對準」意謂及包含使用單一光罩來形成其他特徵所基於之初始圖案。因而，形成於基板110上之特徵係在未利用額外遮罩及光微影動作之情況下對準。基板可為包括半導電材料層之習知矽基板或另一塊體基板。如本文中所使用，術語「塊體基板」不僅意謂及包含矽晶圓，而且意謂及包含絕緣體上矽(「SOI」)基板(諸如，藍寶石上矽(「SOS」)基板及玻璃上矽(「SOG」)基板)、基底半導體座上之矽磊晶層及其他半導體或光電子材料(諸如，矽-鍺、鍺、砷化鎵、氮化鎵及磷化銦)。
圖3至圖10B描繪處於使用間距加倍以在基板110上形成分離主動區域之各種製造階段之半導體結構200的實施例。圖3描繪具有各種材料之半導體結構200，該等材料可包含在基板110上之絕緣材料250、可選蝕刻終止材料260、第一消耗性材料212及可選擇性界定材料210。絕緣材料250、可選蝕刻終止材料260、消耗性材料212及可選擇性界定材料210可共同被稱為「遮罩材料」。雖然在基板110上以層之形式而說明該等材料，但該等材料亦可以其他組態而形成。本文中所描述之遮罩材料可藉由任何合適沈積技術而形成，該技術包含(但不限於)旋轉塗佈、毯覆式塗佈、化學氣相沈積(「CVD」)、原子層沈積(「ALD」)、電漿增強ALD或物理氣相沈積(「PVD」)。視待使用之特定材料而定，一般熟習此項技術者可選擇用於形成遮罩材料之技術。
藉由非限制性實例，基板110係由矽形成，諸如，矽半導體基板。絕緣材料250可沈積於基板110上。絕緣材料250可為氧化矽，諸如，正矽酸四乙酯(「TEOS」)、二氧化矽(「SiO2 」)或高密度電漿(「HDP」)氧化物。絕緣材料250可熱生長於基板110上。藉由非限制性實例，絕緣材料250可具有在大約25至大約75之範圍內的厚度。在一實施例中，絕緣材料250為SiO2 且熱生長於基板110上。
蝕刻終止材料260(若存在)可沈積於絕緣材料250上。蝕刻終止材料260可在上覆材料之化學機械平面化(「CMP」)期間充當有效蝕刻終止。蝕刻終止材料260可為氮化物材料。在一實施例中，蝕刻終止材料260為包含(但不限於)氮化矽(「Si3 N4 」)之氮化物。
消耗性材料212可由可圖案化材料形成，可圖案化材料相對於基板110及半導體結構200之其他曝露下伏材料而為可選擇性蝕刻的。消耗性材料212之材料可為含碳材料、介電抗反射塗層(「DARC」)或底部抗反射塗層(「BARC」)材料。藉由非限制性實例，消耗性材料212可為非晶形碳、透明碳、正矽酸四乙酯(「TEOS」)、氮化矽(「Si3 N4 」)、碳化矽(「SiC」)、矽或介電抗反射塗層(DARC)(諸如，富矽氮氧化物(「SiO3 N4 」))、氧化矽(SiO2 )或其組合。藉由非限制性實例，可以在大約800至大約2500之範圍內的厚度(諸如，以大約2000)而沈積消耗性材料212。可基於對用於本文中所論述之各種圖案形成及圖案轉印步驟之化學物及處理條件的考慮而選擇上覆於基板110之材料。因為消耗性材料212與基板110之間的材料用以將自消耗性材料212所得到之圖案轉印至基板110，所以此等材料經選擇成使得其可相對於其他曝露材料而被選擇性蝕刻。如本文中所使用，當材料展現比曝露至相同蝕刻化學物之其他材料之蝕刻速率大至少大約兩倍的蝕刻速率時，該材料為「可選擇性蝕刻的」。理想地，此材料具有比曝露至相同蝕刻化學物之另一材料之蝕刻速率大至少大約十倍的蝕刻速率。因而，應理解，消耗性材料212、絕緣材料250及蝕刻終止材料260可為使能夠進行如本文中所描述之選擇性移除的材料之任何組合。
可選擇性界定材料210可藉由微影過程而界定，例如，由光阻材料(包含此項技術中已知之任何光阻材料)形成。因為光阻材料及光微影技術在此項技術中為熟知的，所以選擇、沈積、圖案化及顯影光阻材料以產生所要圖案未在本文中加以詳細地論述。
圖4展示在上方具有經圖案化可選擇性界定材料210之半導體結構200的實施例。可選擇性界定材料210中之圖案可包含具有大體上相等寬度之空間及線。空間可對應於可選擇性界定材料210之已移除部分，而線對應於可選擇性界定材料210之剩餘部分。線之寬度可為可由用以形成圖案之光微影技術列印的最小特徵大小(「F」)。或者，可以大於F之特徵大小而列印空間及線。藉由非限制性實例，F可處於大約40nm至大約70nm之範圍內，諸如，大約44nm。雖然圖4說明1F迂迴穿行圖案，但應瞭解，可使用其他布局。
圖4中鄰近線之間的間距等於可選擇性界定材料210之線之寬度與相鄰空間之寬度的總和。為了最小化使用線及空間之此圖案而形成之特徵的臨界尺寸，間距可處於或接近於用以圖案化可選擇性界定材料210之光微影技術的極限。舉例而言，線之間距可在約80nm與約140nm之間。因此，間距可處於光微影技術之最小間距，且下文所論述之間隔物圖案可有利地具有低於光微影技術之最小間距的間距。或者，因為當接近光微影技術之極限時位置及特徵大小之誤差裕度通常增加，所以線可經形成為具有較大特徵大小以最小化線之位置及大小上的誤差且其隨後可經修整至較小大小。
參看圖5A，可將可選擇性界定材料210中之圖案轉印至消耗性材料212中，從而在蝕刻終止材料260(若存在)上形成消耗性結構264。在將圖案轉印至消耗性材料212之後，可藉由習知技術來移除可選擇性界定材料210。在一實施例中，消耗性結構264可為消耗性線。可使用習知蝕刻過程(諸如，習知乾式蝕刻過程、習知濕式蝕刻過程或其組合)而將形成於可選擇性界定材料210中之圖案蝕刻至消耗性材料212中。藉由非限制性實例，可使用乾式蝕刻化學物來蝕刻消耗性材料212，從而產生具有大體上垂直側壁265之消耗性結構264。如本文中所使用，術語「大體上垂直側壁」意謂及包含具有與垂直線成小於大約5°之傾斜角的側壁。在一實施例中，消耗性結構264之寬度可為F。
在移除可選擇性界定材料210之後，可修整消耗性結構264。在本發明之一實施例中，可將消耗性結構264自F修整至1/2F。如圖5B及圖5C所示，可藉由蝕刻消耗性結構264來加寬每一消耗性結構264之間的空間266，以形成經修改空間266a及經修改結構264a(圖5C)。可使用各向同性蝕刻來蝕刻消耗性結構264以「收縮」彼等特徵。合適蝕刻包含使用含氧電漿(例如，SO2 /O2 /N2 /Ar電漿、Cl2 /O2 /He電漿或HBr/O2 /N2 電漿)之蝕刻。蝕刻之程度可經選擇成使得經修改結構264a之寬度大體上等於稍後形成之間隔物268之間的所要間隔，此將自本文中之論述得以瞭解。舉例而言，消耗性結構264之寬度可自約70nm減小至約35nm。有利地，寬度減小蝕刻使經修改結構264a能夠窄於原本使用用以圖案化可選擇性界定材料210之光微影技術可能達到的寬度。此外，蝕刻可使經修改結構264a之邊緣平滑，因此改良彼等線之均一性。
間隔物材料214可形成於半導體結構200之曝露表面上，如圖6A及圖6B所示。可藉由習知技術(諸如，藉由ALD)而將間隔物材料214等形地沈積於經修改結構264a上。藉由等形地沈積間隔物材料214，間隔物材料214之厚度可保持大體上均一，而不管下伏特徵(諸如，經修改結構264a)之幾何形狀及構形。經修改結構264a可相對於間隔物材料214而為可選擇性蝕刻的。僅作為一實例，間隔物材料214可由多晶矽、氮化矽Si3 N4 或氧化矽(「SiOx 」)形成。
參看圖6C，可各向異性地蝕刻間隔物材料214，從而自大體上水平表面移除間隔物材料214，而在大體上垂直表面上留下間隔物材料214。因而，可曝露經修改結構264a之大體上水平表面及半導體結構200之下伏部分的大體上水平表面。若間隔物材料214係由SiOx 形成，則各向異性蝕刻可為電漿蝕刻，諸如，含CF4 電漿、含C2 F6 電漿、含C4 F8 電漿、含CHF3 電漿、含CH2 F2 電漿或其混合物。若間隔物材料214係由氮化矽形成，則各向異性蝕刻可為CHF3 /O2 /He電漿或C4 F8 /CO/Ar電漿。藉由蝕刻而產生之間隔物268可存在於經修改結構264a之經蝕刻部分的大體上垂直側壁上。間隔物268之寬度可對應於最終待形成於半導體結構200上之特徵(諸如，渠溝)的所要寬度。在一實施例中，間隔物268之寬度可為1/2F。如本文中進一步詳細地所論述，具有次微影寬度之第一渠溝222(展示於圖10A及圖10B中)可在基板110中形成於由間隔物268所界定之區域之間。如本文中所使用，「次微影」意謂小於約70nm，諸如，約44nm。在一實施例中，第一渠溝222(展示於圖10A及圖10B中)具有大約1/2F之寬度。
接著，可藉由習知方法而移除經修改結構264a，從而留下間隔物268，如圖7A及圖7B所示。舉例而言，若非晶形碳用作消耗性材料212(經修改結構264a係由其形成)，則可使用氧基電漿(諸如，O2 /Cl2 電漿、O2 /HBr電漿或O2 /SO2 /N2 電漿)而移除非晶形碳。
緊接著，可使用乾式蝕刻化學物以將間隔物268之圖案轉印至下伏於經修改結構264a之材料中。或者，可使用多種乾式蝕刻化學物以單獨地蝕刻下伏於經修改結構264a之材料中的每一者。舉例而言，第一蝕刻可將間隔物268之圖案轉印至下伏蝕刻終止材料260(若存在)中，且第二蝕刻可將間隔物268之圖案轉印至基板110中(如圖8所示)，從而在其中形成渠溝。適於蝕刻此等材料之蝕刻化學物在此項技術中為已知的，且因此，未在本文中對其加以詳細地描述。
如圖9所示，可以包含開口221以分離具有隨意間距及特徵大小之主動區域230的主動區域遮罩來圖案化半導體結構200之主動區域230。將主動區域230說明為跨越基板110而在大體上水平方向上延伸，而將主動區域遮罩220之開口221說明為大體上垂直於主動區域230而延伸。包含開口221之主動區域遮罩可被認為係跨越基板110而在大體上垂直方向上延伸。主動區域遮罩220可由碳(諸如，非晶形碳或透明碳)形成。為了減小主動區域遮罩中之開口221的尺寸，可視情況將犧牲間隔物材料(未圖示)沈積於開口221之側壁上且將其修整成曝露主動區域遮罩220，使得主動區域遮罩220之開口221由間隔物側接。可將開口221之圖案轉印至基板110以分離主動區域230。可藉由習知蝕刻方法或藉由本文中所描述之方法而轉印主動區域遮罩220中之開口221的圖案。在本發明之一實施例中，可在半導體結構200上形成70nm間距之主動區域230。
如圖10A及圖10B所示，可移除主動區域遮罩220，且可將基板110蝕刻於先前由主動區域遮罩220所遮罩之位置中。若主動區域遮罩220係由間隔物側接，則可移除主動區域遮罩220且可將剩餘間隔物用作遮罩以蝕刻基板110。可藉由離子研磨、反應性離子蝕刻或化學蝕刻而蝕刻基板110。舉例而言，若基板110係由矽形成，則可使用HBr/Cl2 或碳氟化合物電漿蝕刻而各向異性地蝕刻基板110。為了將所要深度蝕刻至由矽形成之基板110中，可控制蝕刻時間。舉例而言，可將矽曝露至適當蝕刻化學物歷經足以在矽中達成所要深度之時間量。
在蝕刻之後，可藉由習知方法(諸如，濕式或乾式蝕刻)而移除間隔物。藉由非限制性實例，若間隔物係由多晶矽形成，則可使用四甲基銨氫氧化物(TMAH)之溶液而蝕刻間隔物。或者，若間隔物係由氮化物形成，則可使用乾式蝕刻化學物而移除間隔物。
參看圖10A，在可為(例如)主動矽之主動區域230之間形成第一渠溝222。如圖10B所示，可將第一填充材料226毯覆式沈積於半導體結構200上且將其密化，如此項技術中已知。第一填充材料226可為二氧化矽基材料，諸如，旋塗式介電質(「SOD」)、二氧化矽、TEOS或高密度電漿(「HDP」)氧化物。可(諸如)藉由化學機械拋光(「CMP」)而平面化第一填充材料226，以移除第一填充材料226之在基板110之矽柱狀物232上方延伸之部分。
主動區域230中之矽柱狀物232及第一渠溝222(展示於圖10A及圖10B中)已在兩個方向上進行間距加倍。應瞭解，雖然間距在上文之實例中實際上減半，但間距之此減小通常被稱為間距「加倍」。應進一步理解，本發明之實施例包含僅在一個方向上進行間距加倍，例如，將矽柱狀物232之寬度或第一渠溝222之寬度進行間距加倍。在本發明之一實施例中，矽柱狀物232之寬度及/或第一渠溝222之寬度可為次微影的。
圖10A及圖10B之半導體結構200'可經受進一步處理。藉由非限制性實例，半導體結構200'可經受額外間距加倍過程以在記憶體陣列之閘極中形成渠溝，如圖11A至圖15所示。參看圖11A，可將第二消耗性材料312沈積於主動區域230上且將其圖案化，如本文中所描述。可相對於第一渠溝222而在大體上平行定向上圖案化第二消耗性材料312。可以F而沈積第二消耗性材料312且將其修整至1/2F。在一實施例中，第二消耗性材料312可為非晶形碳且可使用各向異性蝕刻(諸如，使用碳氟化合物電漿之蝕刻)而進行圖案化，但濕式(各向同性)蝕刻在第二消耗性材料312薄之情況下亦可為合適的。電漿蝕刻化學物可包含(無限制)CF4 、CFH3 、CF2 H2 、CF3 H。
可藉由習知方法而將間隔物材料314沈積於經圖案化第二消耗性材料312上且對其加以修整。可以1/2F而沈積間隔物材料314，使得第二消耗性材料312與間隔物材料314具有為F之組合寬度。可藉由化學氣相沈積或原子層沈積而沈積間隔物材料314。間隔物材料314可為能夠相對於第二消耗性材料312及稍後形成之犧牲材料313而被選擇性移除的任何材料。藉由非限制性實例，間隔物材料314可包含氮化矽及氧化矽。在一實施例中，間隔物材料314與第二消耗性材料312可為相同材料。可各向異性地蝕刻間隔物材料314以自第二消耗性材料312及下伏基板110之水平表面移除間隔物材料314，如圖11B所示。可使用碳氟化合物電漿而執行此蝕刻(亦被稱為間隔物蝕刻)。
緊接著，可將犧牲材料313沈積於第二消耗性材料312及間隔物材料314上。可平面化犧牲材料313以曝露第二消耗性材料312及間隔物材料314，如圖12A、圖12B所示。犧牲材料313可包含與第二消耗性材料312相同之材料，或可為與間隔物材料314相比被選擇性蝕刻之任何材料。
如圖13所示，可相對於第二消耗性材料312及犧牲材料313而選擇性蝕刻間隔物材料314以產生間隙334。剩餘消耗性材料312及犧牲材料313可在蝕刻下伏基板110期間充當遮罩以在間隙334之位置中形成第二渠溝322，如圖14A所示。第二渠溝322可具有為1/2F之寬度。歸因於第二消耗性材料312與犧牲材料313之間隔，第二渠溝322可不對稱地定位於基板110上。可藉由離子研磨、反應性離子蝕刻或化學蝕刻而蝕刻基板110。舉例而言，若基板係由矽形成，則可使用HBr/Cl2 或碳氟化合物電漿蝕刻而各向異性地蝕刻基板。為了將所要深度蝕刻至由矽形成之基板中，可控制蝕刻時間。舉例而言，可將矽曝露至適當蝕刻化學物歷經足以在矽中達成所要深度之時間量。
在本發明之實施例中，第二渠溝322可為凹入存取裝置或「RAD」渠溝。如本文中所使用，「RAD渠溝」意謂及包含基板中之最終形成有RAD電晶體之開口。RAD電晶體之一實例包含部分地形成於半導體基板中之渠溝內的電晶體閘極(字線)。
在蝕刻之後，可藉由習知方法而移除第二消耗性材料312及犧牲材料313。在移除第二消耗性材料312及犧牲材料313之後剩餘之圖案可包含具有陣列主動區域圖案的主動區域230之矽柱狀物332(亦被稱為「基座」或「鰭狀物」)及第二渠溝322(閘極渠溝)，如圖14B所示。因此，對於閘極中之第二渠溝322而言，已發生間距加倍。在本發明之一實施例中，第二渠溝322具有次微影寬度。
應理解，第二消耗性材料312、間隔物材料314及犧牲材料313可經選擇成使得間隔物材料314可相對於第二消耗性材料312及犧牲材料313而為可選擇性移除的。因此，在一實施例中，第二消耗性材料312與犧牲材料313可為相同材料。第二消耗性材料312、犧牲材料313及間隔物材料314中之每一者可選自非晶形碳或透明碳、多晶矽、二氧化矽及氮化矽，使得間隔物材料314可相對於第二消耗性材料312及犧牲材料313而為可選擇性移除的。用於第二消耗性材料312及犧牲材料313之材料可經選擇成耐受後續渠溝蝕刻化學物。
參看圖15，在形成第二渠溝322之後，可藉由習知方法而生長閘極氧化物材料370。緊接著，可藉由習知方法而形成各種毯覆式電晶體閘極材料以形成圖15之半導體結構200"。毯覆式電晶體閘極材料可由具有合適功函數之材料(諸如，摻雜多晶矽372或金屬(亦即，TiN)、導體374(例如，鎢)及氮覆蓋材料376)形成。半導體結構200"可經受進一步習知處理以在第二渠溝322中產生電晶體。
圖15之半導體結構200"可經受進一步處理，如圖16所示。藉由非限制性實例，半導體結構200"可經受間距加倍以形成經由字線(亦即，導線)而與電晶體閘極之連接。第一消耗性材料412可沈積於半導體結構200"上。可藉由習知方法或本文中所描述之方法而圖案化第一消耗性材料412以曝露下伏第二渠溝322。
參看圖17，第一間隔物材料414可沈積於半導體結構200"上。可藉由習知方法而平面化及修整第一間隔物材料414。第一間隔物材料414之厚度可界定電晶體閘極之臨界尺寸。參看圖18，可將第二消耗性材料402沈積於半導體結構200"上且將其平面化以曝露第一間隔物材料414及第一消耗性材料412。可將第二消耗性材料402修整至所要寬度，該所要寬度經選擇以留下具有與第一間隔物材料414類似之寬度的開口。緊接著，可將第二間隔物材料404沈積於半導體結構200"上且將其平面化以曝露第一間隔物材料414、第一消耗性材料412及第二消耗性材料402，如圖18所示。第二間隔物材料404之厚度可界定接地閘極之臨界尺寸。第一間隔物材料414及第二間隔物材料404可具有次微影寬度。
如圖19所示，可藉由習知技術而選擇性移除第一消耗性材料412及第二消耗性材料402。在本發明之一實施例中，第一消耗性材料412及第二消耗性材料402為非晶形碳且係藉由習知方法(例如，藉由使用含SO2 電漿)而進行移除。接著，第一間隔物材料414及第二間隔物材料404可在習知蝕刻期間充當遮罩以形成導線425，如圖20所示。導線425可充當字線425'及接地閘極425"。與下伏主動區域之間的間隙相比，相鄰字線425'之間的間隙為不對稱的。在本發明之一實施例中，導線425具有次微影寬度。
藉由利用本發明之實施例的用以形成半導體結構200'、200"、200'"之方法而達成許多優勢。本文中所描述之方法適應在陣列閘極圖案化時6F2 架構之間距加倍。本文中所描述之方法適應待於未按比例調整所需微影之情況下顯著地按比例調整的6F2 架構。因而，可獨立於光微影及蝕刻修整能力而形成次微影特徵。另外，本發明之實施例之方法提供在非相等線空間上之不對稱特徵之間距加倍。應理解，亦可在其他製造過程期間使用本文中所描述之方法，(例如)以界定線性自對準接觸特徵(諸如，電容器、數位線或其他次微影特徵)。半導體結構200'、200"、200'"可經受習知處理動作以產生圖2所示之記憶體陣列100。因為用以形成記憶體陣列100之額外處理動作為習知的，所以此等動作未在本文中加以詳細地描述。
除了在圖式中藉由實例而展示且在本文中加以詳細地描述之特定實施例以外，本發明亦可容許各種修改及替代形式。因此，本發明不限於所揭示之特定形式。更確切而言，本發明之範疇涵蓋落入以下隨附申請專利範圍及其合法等效物內之所有修改及替代。
1/1/2F‧‧‧間隔物268之寬度
2F‧‧‧記憶體單元125之深度
3F‧‧‧記憶體單元125之寬度
10‧‧‧線
20‧‧‧消耗性材料層
30‧‧‧基板
40．．．心軸
50．．．材料層
60．．．間隔物
70．．．水平表面
80．．．水平表面
100．．．記憶體陣列
110．．．基板
112．．．連續主動區域
118．．．內埋式位元線
120．．．導線
125．．．記憶體單元
134．．．導線
136．．．電容器容器
138．．．位元線觸點
140．．．儲存節點觸點
200．．．半導體結構
200'．．．半導體結構
200"．．．半導體結構
200'"．．．半導體結構
210．．．可選擇性界定材料
212．．．第一消耗性材料
214．．．間隔物材料
220．．．主動區域遮罩
221．．．開口
222．．．第一渠溝
226．．．第一填充材料
230．．．主動區域
232．．．矽柱狀物
250．．．絕緣材料
260．．．可選蝕刻終止材料
264．．．消耗性結構
264a．．．經修改結構
265．．．大體上垂直側壁
266．．．空間
266a．．．經修改空間
268．．．間隔物
312．．．第二消耗性材料
313．．．犧牲材料
314．．．間隔物材料
322．．．第二渠溝
332．．．矽柱狀物
334．．．間隙
370．．．閘極氧化物材料
372．．．摻雜多晶矽
374．．．導體
376．．．氮覆蓋材料
402．．．第二消耗性材料
404．．．第二間隔物材料
412．．．第一消耗性材料
414．．．第一間隔物材料
425．．．導線
425'．．．字線
425"．．．接地閘極
F．．．最小特徵大小
P．．．圖案間距
S．．．空間
W．．．線寬
圖1A至圖1F為根據習知間距加倍方法而形成之遮罩線的示意性橫截面圖；圖2為用於6F2 記憶體陣列之一組態之電路布局的簡化平面圖；圖3為處於處理中之初步階段之工件之實施例的橫截面圖；圖4為處於處理步驟中在圖3所說明之階段之後的階段之工件之實施例的平面圖；圖5A為半導體結構之實施例的俯視圖，且圖5B為一中間半導體裝置的橫截面圖；圖5C為處於處理中在圖5B所說明之階段之後的階段之半導體結構之實施例的橫截面圖；圖6A為半導體結構之實施例的俯視圖，且圖6B為圖6A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；圖6C為處於處理步驟中在圖6B所說明之階段之後的階段之半導體結構之實施例的橫截面圖；圖7A為半導體結構之實施例的俯視圖，且圖7B為圖7A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；圖8為處於處理步驟中在圖7B所說明之階段之後的階段之半導體結構之實施例的橫截面圖；圖9為處於處理中在圖8所說明之階段之後的階段之半導體結構之實施例的俯視圖；圖10A為半導體結構之實施例的俯視圖，且圖10B為圖10A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；圖11A為半導體結構之實施例的俯視圖，且圖11B為圖11A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；圖12A為處於處理中在圖11B所說明之階段之後的階段 之半導體結構之實施例的俯視圖，且圖12B為圖12A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；圖13為處於處理中在圖12B所說明之階段之後的階段之半導體結構之實施例的俯視圖；圖14A為半導體結構之實施例的俯視圖，且圖14B為圖14A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；圖15為處於處理中在圖14B所說明之階段之後的階段之半導體結構之實施例的橫截面圖；圖16為處於處理中在圖15所說明之階段之後的階段之半導體結構之實施例的俯視圖；圖17及圖18A為在各種製造階段期間半導體結構之實施例的俯視圖；圖18B為圖18A中沿著標記為A之虛線所截取之半導體結構的橫截面圖；且圖19及圖20為在各種製造階段期間半導體結構之實施例的俯視圖。
200'"．．．半導體結構
230．．．主動區域
425．．．導線
425'．．．字線
425"．．．接地閘極

Claims (19)

  1. 一種形成半導體結構之方法，該方法包括：在一基板上形成一第一消耗性材料；在該基板上於一第一方向上圖案化該第一消耗性材料；修整該第一消耗性材料；在修整該第一消耗性材料之後，在該第一消耗性材料之側壁上形成第一間隔物之一圖案；移除該第一消耗性材料；將第一間隔物之該圖案轉印至該基板中；在該基板上於一第二方向上圖案化一第二消耗性材料；在該第二消耗性材料之側壁上形成第二間隔物之一圖案；移除該第二消耗性材料；及將第二間隔物之該圖案轉印至該基板中以在該等第二間隔物之間形成渠溝。
  2. 如請求項1之方法，其進一步包括：將該第一消耗性材料修整至一次微影寬度。
  3. 如請求項1之方法，其進一步包括：利用一絕緣材料而填充該等渠溝。
  4. 如請求項1之方法，其中該等渠溝具有一次微影寬度。
  5. 一種在一半導體結構中形成次微影渠溝之方法，該方法包括： 在一基板上形成一消耗性材料，在其上形成該消耗性材料之該基板包括在其上形成該消耗性材料之前之分離主動區域；圖案化該消耗性材料；在該消耗性材料之側壁上形成間隔物；鄰近於該等間隔物而形成一犧牲材料；移除該等間隔物以在該犧牲材料與該消耗性材料之間形成複數個間隙；及經由該複數個間隙而蝕刻該基板以在其中形成複數個渠溝，該等溝渠個別地延伸橫越多個該分離主動區域。
  6. 如請求項5之方法，其進一步包括：選擇該消耗性材料及該犧牲材料以包括相同材料。
  7. 如請求項6之方法，其中選擇該消耗性材料及該犧牲材料包括：自由非晶形碳、透明碳、多晶矽、二氧化矽及氮化矽組成之群組選擇該消耗性材料及該犧牲材料。
  8. 如請求項5之方法，其中經由該複數個間隙而蝕刻該基板以在其中形成複數個渠溝包括：在該基板中形成複數個矽鰭狀物。
  9. 如請求項5之方法，其進一步包括：在該複數個渠溝內形成複數個電晶體閘極。
  10. 如請求項5之方法，其進一步包括：將該等間隔物形成為具有小於一最小特徵大小之一寬度。
  11. 如請求項5之方法，其中在該基板中形成複數個渠溝包括：形成複數個凹入主動裝置渠溝。
  12. 如請求項5之方法，其中經由該複數個間隙而蝕刻該基板以在其中形成複數個渠溝包括：形成相對於該等分離主動區域而不對稱地定位之該複數個渠溝。
  13. 一種在一半導體結構上形成導線之方法，該方法包括：在包括分離主動區域及次微影閘極渠溝之一基板上形成一第一消耗性材料；圖案化該第一消耗性材料；在該第一消耗性材料之側壁上形成間隔物；鄰近於該等間隔物而形成一第二消耗性材料，該第二消耗性材料及該第一消耗性材料在該基板上界定開口；在形成該第二消耗性材料之後且在界定該等開口之後，在該等開口內形成一犧牲材料；移除該第一消耗性材料及該第二消耗性材料；在該基板中於該等間隔物與該犧牲材料之間形成渠溝；及利用一導電材料而填充該等渠溝。
  14. 如請求項13之方法，其中在該等開口內形成一犧牲材料包括：在鄰近於該基板上之主動區域之分離區域上形成該犧牲材料。
  15. 如請求項13之方法，其中在該第一消耗性材料之側壁上形成間隔物包括：形成與該基板中之下伏閘極渠溝大體上垂直對準的該等間隔物。
  16. 如請求項13之方法，其中鄰近於該等間隔物而形成一第二消耗性材料包括：將該第二消耗性材料沈積於該等間 隔物上，且將該第二消耗性材料修整成界定具有大體上類似於該等間隔物之一寬度之一寬度的該等開口。
  17. 如請求項13之方法，其進一步包括：在該基板上形成一第一消耗性材料之前在該基板上形成該等分離主動區域，且利用具有一次微影寬度之分離區域而隔離該等分離主動區域。
  18. 一種在一半導體結構上形成導線之方法，該方法包括：在包括分離主動區域及次微影閘極渠溝之一基板上形成一第一消耗性材料；圖案化該第一消耗性材料；在該第一消耗性材料之側壁上形成間隔物；鄰近於該等間隔物而形成一第二消耗性材料，該第二消耗性材料及該第一消耗性材料在該基板上界定開口；在該等開口內形成一犧牲材料；移除該第一消耗性材料及該第二消耗性材料；在該基板中於該等間隔物與該犧牲材料之間形成渠溝；利用一導電材料而填充該等渠溝；及進一步包括在該基板上形成一第一消耗性材料之前在該基板中形成該等次微影閘極渠溝。
  19. 一種半導體結構，其包括：由分離區域隔離之複數個主動區域，該複數個主動區域包含凹入存取裝置渠溝，該等凹入存取裝置渠溝個別地在其中具有小於一最小特徵大小之一寬度及在該等凹 入存取裝置渠溝中之導電閘極材料；及在高度上向該複數個主動區域及凹入存取裝置渠溝外之複數個導線，該複數個導線之某些與在該凹入存取裝置渠溝中之導電閘極材料連接，該複數個導線之該某些包括字線，且進一步包括該複數個導線之另一某些，其包括接地閘極線，該等字線之二者係容納於該等接地閘極線之緊鄰二者之間。
TW098113229A 2008-05-05 2009-04-21 於半導體結構中形成分離主動區域、渠溝及導線之方法以及包含其之半導體結構 TWI476815B (zh)

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