JP6272949B2 - パターン形成方法 - Google Patents
パターン形成方法 Download PDFInfo
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- JP6272949B2 JP6272949B2 JP2016112744A JP2016112744A JP6272949B2 JP 6272949 B2 JP6272949 B2 JP 6272949B2 JP 2016112744 A JP2016112744 A JP 2016112744A JP 2016112744 A JP2016112744 A JP 2016112744A JP 6272949 B2 JP6272949 B2 JP 6272949B2
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- 238000000034 method Methods 0.000 title claims description 86
- 230000007261 regionalization Effects 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims description 60
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000003252 repetitive effect Effects 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 description 172
- 239000011162 core material Substances 0.000 description 38
- 125000006850 spacer group Chemical group 0.000 description 33
- 239000010410 layer Substances 0.000 description 25
- 238000000206 photolithography Methods 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 8
- 239000000460 chlorine Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Description
下地膜の上に、繰り返しのラインパターン形状の第1の膜を形成する工程と、
前記第1の膜の側面に、前記第1の膜とはエッチング選択性の異なる第2の膜を形成する工程と、
前記第1の膜を除去することなく、前記第2の膜の上面及び側面に、前記第1の膜及び前記第2の膜とはエッチング選択性の異なる第3の膜を形成する工程と、
前記第3の膜の上に、開口部を有するレジストパターンを形成する工程と、
前記レジストパターンをエッチングマスクとして前記第3の膜をエッチングすることにより、前記第1の膜の上面、前記第2の膜の上面及び前記第3の膜の上面が露出した凹部を形成する工程と、
前記凹部において上面が露出した前記第2の膜が残存するように、前記凹部において上面が露出した前記第1の膜及び前記第3の膜をエッチングすることにより、前記下地膜の上面を露出させる工程と、
上面が露出した前記下地膜をエッチングすることにより、前記下地膜を貫通する貫通孔を形成する工程と、
を有する。
11 金属膜
12 絶縁膜
20 第2の層
21 絶縁膜
22 芯材
23 スペーサ
24 犠牲膜
25 レジスト膜
26 ビア
27 導電膜
30 第3の層
31 金属膜
32 絶縁膜
Claims (5)
- 下地膜の上に、繰り返しのラインパターン形状の第1の膜を形成する工程と、
前記第1の膜の側面に、前記第1の膜とはエッチング選択性の異なる第2の膜を形成する工程と、
前記第1の膜を除去することなく、前記第2の膜の上面及び側面に、前記第1の膜及び前記第2の膜とはエッチング選択性の異なる第3の膜を形成する工程と、
前記第3の膜の上に、開口部を有するレジストパターンを形成する工程と、
前記レジストパターンをエッチングマスクとして前記第3の膜をエッチングすることにより、前記第1の膜の上面、前記第2の膜の上面及び前記第3の膜の上面が露出した凹部を形成する工程と、
前記凹部において上面が露出した前記第2の膜が残存するように、前記凹部において上面が露出した前記第1の膜及び前記第3の膜をエッチングすることにより、前記下地膜の上面を露出させる工程と、
上面が露出した前記下地膜をエッチングすることにより、前記下地膜を貫通する貫通孔を形成する工程と、
を有する、パターン形成方法。 - 前記下地膜を貫通する貫通孔を形成する工程の後、前記第2の膜が残存するように、前記第1の膜及び前記第3の膜を除去する工程と、
前記貫通孔及び前記第2の膜の側面に導電膜を形成する工程と、
を更に有する、請求項1に記載のパターン形成方法。 - 前記下地膜は、配線層の上に形成される絶縁膜であり、
前記導電膜は、前記配線層と電気的に接続される、
請求項2に記載のパターン形成方法。 - 前記第1の膜は、ポリシリコンにより形成される膜であり、
前記第2の膜は、酸化シリコンにより形成される膜であり、
前記第3の膜は、金属酸化物により形成される膜である、
請求項1乃至3のいずれか一項に記載のパターン形成方法。 - 前記第3の膜は、金属酸化物を含む溶液をスピン塗布することにより形成される、
請求項4に記載のパターン形成方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016112744A JP6272949B2 (ja) | 2016-06-06 | 2016-06-06 | パターン形成方法 |
TW106116982A TWI718303B (zh) | 2016-06-06 | 2017-05-23 | 圖案形成方法 |
US15/602,307 US10074557B2 (en) | 2016-06-06 | 2017-05-23 | Pattern forming method |
KR1020170069055A KR102332384B1 (ko) | 2016-06-06 | 2017-06-02 | 패턴 형성 방법 |
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Application Number | Priority Date | Filing Date | Title |
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JP2016112744A JP6272949B2 (ja) | 2016-06-06 | 2016-06-06 | パターン形成方法 |
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JP2017219617A JP2017219617A (ja) | 2017-12-14 |
JP6272949B2 true JP6272949B2 (ja) | 2018-01-31 |
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US (1) | US10074557B2 (ja) |
JP (1) | JP6272949B2 (ja) |
KR (1) | KR102332384B1 (ja) |
TW (1) | TWI718303B (ja) |
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US10504775B1 (en) * | 2018-05-31 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming metal layer structures in semiconductor devices |
US11037821B2 (en) * | 2019-05-01 | 2021-06-15 | Globalfoundries U.S. Inc. | Multiple patterning with self-alignment provided by spacers |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2910713B2 (ja) * | 1996-12-25 | 1999-06-23 | 日本電気株式会社 | 半導体装置の製造方法 |
US6590265B2 (en) * | 1998-02-12 | 2003-07-08 | National Semiconductor Corporation | Semiconductor device with sidewall spacers having minimized area contacts |
US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
JP2004327616A (ja) * | 2003-04-23 | 2004-11-18 | Sumitomo Electric Ind Ltd | 金属パターンを形成する方法 |
JP4167664B2 (ja) * | 2004-02-23 | 2008-10-15 | 株式会社東芝 | レチクルの補正方法、レチクルの作製方法、パターン形成方法及び半導体装置の製造方法 |
US7981595B2 (en) * | 2005-03-23 | 2011-07-19 | Asml Netherlands B.V. | Reduced pitch multiple exposure process |
US7696101B2 (en) * | 2005-11-01 | 2010-04-13 | Micron Technology, Inc. | Process for increasing feature density during the manufacture of a semiconductor device |
JP5055980B2 (ja) * | 2006-11-29 | 2012-10-24 | 富士通セミコンダクター株式会社 | 電子装置の製造方法および半導体装置の製造方法 |
TWI493598B (zh) * | 2007-10-26 | 2015-07-21 | Applied Materials Inc | 利用光阻模板遮罩的倍頻方法 |
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US9437447B2 (en) * | 2014-02-23 | 2016-09-06 | Tokyo Electron Limited | Method for patterning a substrate for planarization |
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