JP4815519B2 - マスクパターンの形成方法及び半導体装置の製造方法 - Google Patents
マスクパターンの形成方法及び半導体装置の製造方法 Download PDFInfo
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- JP4815519B2 JP4815519B2 JP2009211819A JP2009211819A JP4815519B2 JP 4815519 B2 JP4815519 B2 JP 4815519B2 JP 2009211819 A JP2009211819 A JP 2009211819A JP 2009211819 A JP2009211819 A JP 2009211819A JP 4815519 B2 JP4815519 B2 JP 4815519B2
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- 238000000034 method Methods 0.000 title claims description 175
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- 229910052799 carbon Inorganic materials 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 41
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- 238000000206 photolithography Methods 0.000 claims description 14
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- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- -1 CH 3 F Chemical compound 0.000 description 1
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 description 1
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BIVNKSDKIFWKFA-UHFFFAOYSA-N N-propan-2-yl-N-silylpropan-2-amine Chemical compound CC(C)N([SiH3])C(C)C BIVNKSDKIFWKFA-UHFFFAOYSA-N 0.000 description 1
- UOERHRIFSQUTET-UHFFFAOYSA-N N-propyl-N-silylpropan-1-amine Chemical compound CCCN([SiH3])CCC UOERHRIFSQUTET-UHFFFAOYSA-N 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
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- 238000011156 evaluation Methods 0.000 description 1
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- 239000001257 hydrogen Substances 0.000 description 1
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- 239000010410 layer Substances 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
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Classifications
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- G—PHYSICS
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Description
(第1の実施の形態)
図1から図6を参照し、本発明の第1の実施の形態に係るマスクパターンの形成方法及び半導体装置の製造方法について説明する。
また、比較例1では、レジスト膜に対する選択比が高い反射防止膜、例えばレジスト膜よりも柔らかい反射防止膜を選択しなくてはならず、反射防止膜の材料が制限され、製造コストを増大させる要因となる。本実施の形態では、材料の選択の制限がなく一般的な反射防止膜を用いることができるため、製造コストを減少させることができる。
(実施例1)
(A)ステップS15(第2のステップ)
処理ガス(ガス流量):CH3F(50sccm)/CF4(250sccm)
基板温度 :加熱なし
成膜装置内圧力 :20mTorr
処理時間 :60秒
高周波電源パワー(上部電極/下部電極):600/600W
(B)ステップS16(第3のステップ)
処理ガス(ガス流量):CF4(170sccm)/O2(30sccm)
基板温度 :加熱なし
成膜装置内圧力 :100mTorr
処理時間 :25秒
高周波電源パワー(上部電極/下部電極):600/100W
(C)ステップS17(第4のステップ)
処理ガス(ガス流量):C4H8(40sccm)/O2(10sccm)
基板温度 :加熱なし
成膜装置内圧力 :40mTorr
処理時間 :40秒
高周波電源パワー(上部電極/下部電極):600/600W
(D)ステップS18(第1のマスクパターン列形成ステップ)
処理ガス(ガス流量):O2(100sccm)
基板温度 :加熱なし
成膜装置内圧力 :20mTorr
処理時間 :20秒
高周波電源パワー(上部電極/下部電極):600/30W
(E)ステップS19(第6のステップ)
処理ガス(ガス流量):C4H8(30sccm)/CF4(170sccm)
基板温度 :加熱なし
成膜装置内圧力 :20mTorr
処理時間 :20秒
高周波電源パワー(上部電極/下部電極):600/100W
(F)ステップS20(第3のマスクパターン列形成ステップ)
処理ガス(ガス流量):CH3F(50sccm)/CF4(100sccm)
基板温度 :加熱なし
成膜装置内圧力 :20mTorr
処理時間 :10秒
高周波電源パワー(上部電極/下部電極):600/100W
(G)ステップS21(第7のステップ)
処理ガス(ガス流量):CHF3(90sccm)/CF4(240sccm)/O2(8sccm)
基板温度 :加熱なし
成膜装置内圧力 :90mTorr
処理時間 :45秒
高周波電源パワー(上部電極/下部電極):300/200W
図7に、実施例で(D)ステップS18を行った後の第1のマスクパターン列15cを、走査型電子顕微鏡SEM(Scanning Electron Microscope)を用いて撮影した写真を示す。図7(a)及び図7(b)は、第1のマスクパターン列15cの断面を、それぞれ正面及び斜め上方から撮影した写真(左側)と、写真を模式的に説明する図(右側)とを示す図である。
(第2の実施の形態)
次に、図9から図10Eを参照し、本発明の第2の実施の形態に係るマスクパターンの形成方法及び半導体装置の製造方法を説明する。
(第2の実施の形態の変形例)
次に、図11から図12Bを参照し、本発明の第2の実施の形態の変形例に係るマスクパターンの形成方法及び半導体装置の製造方法を説明する。
11 被エッチング膜(第1の被エッチング膜)
12 第2の被エッチング膜
13 反射防止膜(第1の反射防止膜)
14 レジスト膜(第1のレジスト膜)
15、25 酸化シリコン膜
16、26 カーボン膜
23 第2の反射防止膜
24 第2のレジスト膜
Claims (23)
- 反射防止膜上に形成され、トリミングされた所定のライン幅を有するレジストパターン列の表面を、隣り合う該レジストパターン列の間隔が所定の寸法となるまで等方的に酸化シリコン膜で被覆する第1のステップと、
前記酸化シリコン膜で被覆した前記レジストパターン列の隣り合う列の間をカーボン膜で埋め込むと共に、前記酸化シリコン膜で被覆した前記レジストパターン列の上部を前記カーボン膜で被覆する第2のステップと、
前記カーボン膜を、前記酸化シリコン膜で被覆した前記レジストパターン列の上部から除去すると共に、前記酸化シリコン膜で被覆した前記レジストパターン列の隣り合う列の間に残存するように前記カーボン膜をエッチバック処理する第3のステップと、
残存する前記カーボン膜を除去すると共に、前記レジストパターン列の上部を被覆する前記酸化シリコン膜を所定の膜厚寸法となるようにエッチバック処理する第4のステップと、
前記酸化シリコン膜が除去された前記レジストパターン列をアッシング処理し、前記反射防止膜上に、トリミングされた前記レジストパターン列の前記所定のライン幅と略等しいスペース幅で配列し、所定の幅寸法を有する中央部と、該中央部を両側から挟み前記所定の膜厚寸法を有する膜側壁部とを有する、酸化シリコン膜よりなる第1のマスクパターン列を形成するステップと
を有するマスクパターンの形成方法。 - 前記第2のステップと、前記第3のステップとを、前記カーボン膜をエッチバック処理する処理装置内で連続して行うことを特徴とする請求項1に記載のマスクパターンの形成方法。
- 前記カーボン膜は、アモルファスカーボンを含むことを特徴とする請求項2に記載のマスクパターンの形成方法。
- 前記第2のステップにおいて、CF系ガス、CHF系ガス、又はCH系ガスのいずれかを含む第1の処理ガスを供給し、前記カーボン膜で被覆することを特徴とする請求項3に記載のマスクパターンの形成方法。
- 前記第1の処理ガスは、CH3F又はCF4を含むことを特徴とする請求項4に記載のマスクパターンの形成方法。
- 前記反射防止膜上に形成し、レジスト膜よりなるパターンの形状をトリミングして前記レジストパターン列を形成する第5のステップを有し、
前記第5のステップと、前記第1のステップとを、前記酸化シリコン膜を成膜する成膜装置内で連続して行うことを特徴とする請求項1から請求項5のいずれかに記載のマスクパターンの形成方法。 - 前記第1のステップにおいて、シリコンを含む原料ガスと酸素を含むガスとを交互に供給し、前記レジストパターン列の表面を酸化シリコン膜で被覆することを特徴とする請求項1から請求項5のいずれかに記載のマスクパターンの形成方法。
- 前記第3のステップにおいて、CF系ガス、CHF系ガス、CH系ガス、又は酸素ガスを含む第2の処理ガスを供給し、前記カーボン膜をエッチバック処理することを特徴とする請求項1から請求項5のいずれかに記載のマスクパターンの形成方法。
- 前記第2の処理ガスは、CF4又は酸素ガスを含むことを特徴とする請求項8に記載のマスクパターンの形成方法。
- 前記第4のステップにおいて、CF系ガス、CHF系ガス、CH系ガス、又は酸素ガスを含む第3の処理ガスを供給し、エッチバック処理することを特徴とする請求項1から請求項5のいずれかに記載のマスクパターンの形成方法。
- 前記第3の処理ガスは、C4F8又は酸素ガスを含むことを特徴とする請求項10に記載のマスクパターンの形成方法。
- 前記第1のマスクパターン列から前記中央部を除去すると共に、該中央部の両側の前記膜側壁部が残存するように前記酸化シリコン膜をエッチバック処理し、前記反射防止膜上に、残存する前記膜側壁部よりなる第2のマスクパターン列を形成する第6のステップを有する請求項1から請求項5のいずれかに記載のマスクパターンの形成方法。
- 前記第6のステップにおいて、CF系ガス、CHF系ガス、又はCH系ガスのいずれかを含む第4の処理ガスを供給し、前記酸化シリコン膜をエッチバック処理することを特徴とする請求項12に記載のマスクパターンの形成方法。
- 前記第4の処理ガスは、C4F8又はCF4を含むことを特徴とする請求項13に記載のマスクパターンの形成方法。
- 前記第2のマスクパターン列を用いて前記反射防止膜をエッチングし、少なくとも前記反射防止膜よりなり、一の方向に延びる第3のマスクパターン列を形成するステップを有する請求項12に記載のマスクパターンの形成方法。
- 基板の上に、被エッチング膜、反射防止膜及びレジスト膜を積層するステップと、
フォトリソグラフィ技術を用いて前記レジスト膜よりなるパターンを形成するステップと、
請求項15に記載のマスクパターンの形成方法を行って、前記第3のマスクパターン列を形成するステップと、
前記第3のマスクパターン列を用いて前記被エッチング膜を加工して、第4のマスクパターン列を形成する第7のステップと
を有する半導体装置の製造方法。 - 前記被エッチング膜は、窒化シリコン、酸化シリコン、酸窒化シリコン、アモルファスシリコン、又はポリシリコンを含むことを特徴とする請求項16に記載の半導体装置の製造方法。
- 前記第7のステップにおいて、CF系ガス、CHF系ガス、CH系ガス、又は酸素ガスを含む第5の処理ガスを供給し、前記被エッチング膜を加工することを特徴とする請求項16に記載の半導体装置の製造方法。
- 前記第5の処理ガスは、CHF3、CF4又は酸素ガスを含むことを特徴とする請求項18に記載の半導体装置の製造方法。
- 基板の上に、第1の被エッチング膜、第2の被エッチング膜、及び第1の反射防止膜を積層するステップと、
前記反射防止膜が前記第1の反射防止膜である請求項15に記載のマスクパターンの形成方法を行って、前記第3のマスクパターン列である第1の方向に延びる第4のマスクパターン列を形成するステップと、
前記第4のマスクパターン列を用いて前記第2の被エッチング膜を加工して、第5のマスクパターン列を形成するステップと、
前記第5のマスクパターン列を埋めるように第2の反射防止膜を積層するステップと、
前記反射防止膜が前記第2の反射防止膜である請求項15に記載のマスクパターンの形成方法を行って、前記第3のマスクパターン列である前記第1の方向と交差する第2の方向に延びる第6のマスクパターン列を形成するステップと、
前記第5のマスクパターン列及び前記第6のマスクパターン列を用いて前記第1の被エッチング膜を加工して、前記第1の方向及び前記第2の方向に配列するホールを有する第7のマスクパターン列を形成するステップと
を有する半導体装置の製造方法。 - 前記第1の方向と前記第2の方向とのなす角度が90°である請求項20に記載の半導体装置の製造方法。
- 基板の上に、第1の被エッチング膜、第2の被エッチング膜、及び第1の反射防止膜を積層するステップと、
前記反射防止膜が前記第1の反射防止膜である請求項15に記載のマスクパターンの形成方法を行って、前記第3のマスクパターン列である第1の方向に延びる第4のマスクパターン列を形成するステップと、
前記第4のマスクパターン列を用いて前記第2の被エッチング膜を加工して、第5のマスクパターン列を形成するステップと、
前記第5のマスクパターン列を埋めるように第2の反射防止膜を積層するステップと、
前記反射防止膜が前記第2の反射防止膜である請求項15に記載のマスクパターンの形成方法を行って、前記第3のマスクパターン列である前記第1の方向と交差する第2の方向に延びる第6のマスクパターン列を形成するステップと、
前記第6のマスクパターン列を用いて前記第5のマスクパターン列を加工して、前記第1の方向と前記第2の方向とに沿って配列するドットを有する第7のマスクパターン列を形成するステップと、
前記第7のマスクパターン列を用いて前記第1の被エッチング膜を加工して、第8のマスクパターン列を形成するステップと
を有する半導体装置の製造方法。 - 前記第1の方向と前記第2の方向とのなす角度が90°である請求項22に記載の半導体装置の製造方法。
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CN108878286B (zh) * | 2017-05-10 | 2021-06-08 | 北京北方华创微电子装备有限公司 | 一种刻蚀工艺 |
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US10566194B2 (en) | 2018-05-07 | 2020-02-18 | Lam Research Corporation | Selective deposition of etch-stop layer for enhanced patterning |
JP2019204815A (ja) * | 2018-05-21 | 2019-11-28 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
JP7292014B2 (ja) * | 2018-06-21 | 2023-06-16 | 東京エレクトロン株式会社 | マイクロレンズの製造方法およびプラズマ処理装置 |
EP3953073A1 (en) * | 2019-04-11 | 2022-02-16 | Corning Incorporated | Anti-reflective transparent oleophobic surfaces and methods of manufacturing thereof |
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JP2001308076A (ja) | 2000-04-27 | 2001-11-02 | Nec Corp | 半導体装置の製造方法 |
JP2005203672A (ja) * | 2004-01-19 | 2005-07-28 | Sony Corp | 半導体装置の製造方法 |
US20090087990A1 (en) * | 2007-09-28 | 2009-04-02 | Tokyo Electron Limited | Manufacturing method, manufacturing apparatus, control program and program recording medium of semiconductor device |
JP5236983B2 (ja) * | 2007-09-28 | 2013-07-17 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びプログラム記憶媒体 |
KR100942078B1 (ko) * | 2007-12-27 | 2010-02-12 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
JP5226296B2 (ja) * | 2007-12-27 | 2013-07-03 | 東京エレクトロン株式会社 | プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体 |
KR100948464B1 (ko) * | 2007-12-28 | 2010-03-17 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
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US20110065049A1 (en) | 2011-03-17 |
JP2011059579A (ja) | 2011-03-24 |
US20130122429A1 (en) | 2013-05-16 |
US8815495B2 (en) | 2014-08-26 |
TW201118945A (en) | 2011-06-01 |
KR101164897B1 (ko) | 2012-07-19 |
KR20110029064A (ko) | 2011-03-22 |
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