TWI225277B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI225277B
TWI225277B TW092102880A TW92102880A TWI225277B TW I225277 B TWI225277 B TW I225277B TW 092102880 A TW092102880 A TW 092102880A TW 92102880 A TW92102880 A TW 92102880A TW I225277 B TWI225277 B TW I225277B
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Taiwan
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copper
wiring
film
etching
barrier metal
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TW092102880A
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TW200300989A (en
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Yoshihiro Uozumi
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C22/00—Chemical surface treatment of metallic material by reaction of the surface with a reactive liquid, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C22/05—Chemical surface treatment of metallic material by reaction of the surface with a reactive liquid, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using aqueous solutions
    • C23C22/60—Chemical surface treatment of metallic material by reaction of the surface with a reactive liquid, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using aqueous solutions using alkaline aqueous solutions with pH greater than 8
    • C23C22/63—Treatment of copper or alloys based thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/02087—Cleaning of wafer edges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/0209—Cleaning of wafer backside
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

1225277 ⑴ ' 广、'r^/r- x \. w/… „ f , / "* ~ , - 玖Λ發權愈乳 (發明茲明^曰瓦广|^月所屬Hi領域、先前茲術/内容、實施+¾及圖式簡單姣明) 【發明之技術領域】 本發明是半導體積體電路之半導體裝置及有關半導體 裝置配線用之銅膜加工及其配線構造之製造方法、。 【先前技術】 現在半導體積體電路之半導體裝置用銅或以銅為主要 成分之材料配線。銅原子擴散至絕緣膜甚至半導體基板 上，為了防止因此產生之錯誤動作，通常是用氮化鈥、氮 化妲、氮化鎢等障壁金屬包住銅膜以隔絕絕緣層。 如圖13(a)所示，在半導體基板上形成之配線通常是埋 在絕緣膜上之配線溝裡。圖1 3是半導體基板之側面圖。積 體電路等之半導體元件是在以矽做成的半導體基板100上 形成矽氧化膜之層間絕緣膜1 〇 1，在其表面形成配線溝。 在此配線溝之側壁形成TiN或TaN等障壁金屬102，銅膜 103或以銅為主要成分之合金膜埋入其中。 如此以往配線部分的銅會經由沒有障壁金屬之上方擴 散至層間絕緣膜，對在半導體基板100上形成之半導體元 件有不良影響。又因為在層間絕緣膜1 〇 1及埋入其中之銅 膜103表面以CMP法平坦化.所以在刻版印刷時會產生圖形 蝕刻無法辨識之圖形。 針對此問題以蝕刻的方法將配線部分即銅膜1 〇 3上方除 去，使其如圖1 3 (b)所示較層間絕緣膜1 0 1表面低。如此可 使圖形對合。 又如圖13(c)所示在其上方覆蓋一層障壁金屬104或其 (2) 他覆蓋層，如此可 材料則上層之配線：其：從上部擴散。若覆蓋層用導電 丁合吉技昱咖 、穿孔配線（接觸配線）形成時因銅 不a罝接暴路在蝕刻之 衣兄中’故可降低發生腐蝕或因蝕 刻而斷線之危險。 【發明所欲解決之課題】 如前所述以往形成配線、^ ^ $ /再構造的方法有溼式蝕刻法和 乾式姓刻法。乾式法又分成、 成非寺万向蝕刻之RIE (Reactive
Ion Etching)法及等方向 刀门触刻之CDE (Chemical Dry
Etching)法。用此方法雖可 μ j以進行銅蝕刻但對地球的環境 有不良影響。如在乾式法φ你 八古千使用CF系的氣體。溼式法要 除去在蝕刻後堆積的副產品，如μ L ^ ^ 4座相對的溼式處理在工程上及 成本上有較多的問題。 在此將重點放在澄式1虫刻。銅幾乎不溶於鹽酸、氟跋、 稀硫酸、酷酸、氫氰酸等氧化力較弱的酸但會被具氧化力 之酸蝕刻。如熱濃硫酸、硝酸、亞硝酸、磷酸等。又可溶 解於如鹽酸+過氧化氫水、鹽酸+臭氧水、氟酸+過氧化氫 水之類的過氧化氫、臭氧或氧等具氧化力之混合液。也會 被可以和銅錯合成可溶性錯合體的物質如氨、帶有胺基的 物免（乙一胺等）、吼化物（KCN)等姓刻。將這物質和過氧 化氫水等混合強化氧化力通常可以加速蝕刻。 通常氨水和過氧化氫水及鹽酸和過氧化氫水的混合液 是當做洗淨用的藥液’分別稱為SCI、SC2。一般市售的 氨水、鹽酸、或過氧化氫水的濃度約為2 0〜3 5 %，和純水 以1:1:5〜1:1 :7的比例混合調製SCI、SC2。將鋼浸泡在此 (3) (3)1225277 條件下的混合溶液進行蝕刻。 但是前述條件下用SCI、SC2蝕刻銅，將使銅表面白、、尋 化失去原有的光澤。若用硝酸或熱硫酸等前述之各種藥& 姓刻時也會使銅表面白濁，而且溫度愈高愈顯著。因钱刻 使銅表面粗糙造成膜厚度不一。用在配線時產生實質電户且 上升、和丰層之配線接觸不良等問題。因此儘量使表面保 持平滑是蝕刻的必要條件。 提出將銅膜氧化再以酸等除去氧化物之銅蝕刻方 /ΪΓ。如 特開平2-3 0663 1號公報提出在銅膜注入氧離子後回火戈 用氧電漿處理方法等生成氧化物再用稀硫酸或醋酸之餘 刻方法。又如特開平10-23 3 3 97號公報提出在擴散爐、RTA 爐或烤箱内將銅膜曝曬在室溫以上之氧或臭氧形成鋼氧 化膜再翎稀鹽酸或稀硫酸以溼蝕刻、乾蝕刻、或CMp等除 去万法。但是用這些方法蝕刻後的銅表面多半粗糙。特别 疋在為使氧化膜加厚提高溫度時問題更嚴重。 f發明是為了減少這些問題。以酸或鹼除去銅膜氧化後 勺氧化物蝕刻銅膜方法可減少銅膜表面粗糙，工時減少且 、度良好。提供銅氧化膜之形成方法、銅膜蝕刻方法、半 導缸裝置之製造方法、及半導體裝置。 【課題之解決手段】 本發明《特徵為在鋼配線時將銅暴露於PH = 8〜10之氨 水及過氧化氫水之混合液（SC1),表面形成含有氨錯合體 《虱化膜，然後以稀鹽酸等氧化力較弱的酸或稀氨水等鹼 將銅氧化膜選擇性钱刻。在PH = 8〜1〇溶液中浸泡氧化膜形 (4) 成後本應該將銅進行蝕刻，為了加速蝕刻再浸入 pH= 10〜11之SCI使含有氨錯合體之氧化膜成長加厚然後 再以稀鹽酸等氧化力較弱的酸或稀氨水等鹼將銅氧化膜 選擇性蝕刻。或用甘氨酸或丙氨酸等中性胺基酸水溶液將 和銅形成之錯合體溶解，雖然在中性溶液中仍可將銅氧化 膜進行選擇性错刻。 像這樣以形成氧化膜及蝕刻之處理方法使從來銅蝕刻 後不會造成表面粗糙是困難的方法變成可行。以安全且廉 價之藥液在短時間内氧化及蝕刻銅，結果在配線構造的表 面形成一安定障壁金屬。 換言之本發明之特徵為將銅膜表面和pH = 8〜10或 pH = 9〜10之氨水及過氧化氫水之混合液接觸，形成含有氨 錯合體之氧化膜之步驟。或將銅膜表面和pH = 8〜10或 pH = 9〜10之氨水及過氧化氫水之混合液接觸，形成含有氨 錯合體之氧化膜之步驟。以及前述形成氧化膜之銅膜暴露 在pH= 10〜1 1之氨水及過氧化氫水之混合液之步驟。又發 明之銅氧化膜之形成方法是以過氧化氫水在銅膜表面形 成氧化膜之步驟。前述形成氧化膜後的銅膜再暴露於 pH= 10〜1 1之氨水及過氧化氫水之混合，形成含有氨錯合 體之氧化膜之步驟。 - 前述銅氧化膜之形成方法是首先使銅膜和pH==8〜10或 pH = 9〜10之氨水及過氧化氫水之混合液接觸，在前述表面 形成銅氧化膜，最後再暴露在pH=10〜1 1之氨水及過氧化 氫水之混合液，其間可多階段斷續調整pH或連續調整pH。 (5)1225277 —種銅 體的銅 銅之氧 埋入在 線或接 成方法 及將前 在除去 孔側璧 形成金
本發明銅膜之蝕刻方、、表 & ’其特徵在備有以上述任 氧化膜之形成方法在鋼勝士 辑表面形成含銅之氨錯合 氧化膜之步騾，以及自1、+ 二岐鋼膜選擇性地除去上述 化膜之步驟。上述鋼之羞 乳化膜可以酸或鹼除去。 本發明之半導體裝置之制4 〈製造方法，其特徵為具有 半導體基板之絕緣膜上米&、 &成 < 配線溝或接觸孔配 觸配線之銅膜之步騾，以箭、> 則述任一種銅氧化膜之形 在前述銅冑上形纟含氨錯合體之銅氧化膜之步驟， 述銅氧化膜從前述銅膜上選擇性除去之步驟。可以 珂述銅氧化膜後（銅膜表面蝕刻如配線溝或接觸 附近區域相同深度，也可在前述配線溝或接觸孔上 屬膜表面做為障壁金屬，也可以在除去前述銅氧化
銅膜表面前述銅膜上形成再加上一層障壁金屬，也可以在 前述配線溝或接觸孔或配線溝及接觸孔和前述埋入之銅 膜之間介有之前述障壁金屬和前述銅膜上形成之前述障 壁金屬不同材質所構成，也可以將除去前述銅氧化膜後之 銅膜表面暴露於氨水’也可將前述半導體基板以1〇〇〇rpm 以上1600 rpm以下之條件下將銅膜表面暴露在氨水中。 又本發明之半導體裝置之製造方法，其特徵為具有在半 導體基板之絕緣膜上形成之配線溝或接觸孔上堆積金屬 以充填配線溝或接觸孔之步.驟，及研磨前述配線金屬以露 出前述絕緣膜之步驟，及前述半擎體基板之洗淨之击 前述凹蝕之步驟，埋入在前述配線溝或接觸孔之前逑配線 金屬表面凹蝕之步驟，前述研磨步騾、前述洗淨步騾、及 -9-
山5277 則述再蝕刻步驟中至少兩種步騾所用的藥液主要成分相‘ 同。 ' « 又本發明之半導體裝置之製造方法，其特徵為具有在半 · 導to基板上堆積金屬或金屬化合物之步騾，及蝕刻前述 〜 金屬或金屬化合物不要部分之步驟，及前述金屬或金屬化 η物堆積之步騾中包含之鐘敷步驟，前述鍍敷步騾使用之 鍍敷液如鍍敷對像成分及鹼或形成錯合體的成分和前述 蝕刻除去（步驟所用的藥液之主要成分相同，在前述藥液 _ 中添加之氧化劑可以用過氧化氫水或臭氧水，在前述藥液 中之主要酸成分以用硫酸或氫氰酸，前述不要部分蝕刻除 去之步驟後之前述藥液中之氧化劑除去之步驟，及前述藥 液中之金屬離子濃度和前述鍍敷液中之金屬離子滚度幾 乎相同之步驟’更可以將前述氧化劑除去之藥液當做鐘敷 又本發明之半導體之製造裝置是以前述半導體裝置之 製造方法，其特徵為除去包含在前述藥液之氧化劑之手 鲁 段’將前述藥液中之金屬離子濃度調成和前述鍍敷液中之 金屬離子濃度大致相同之手段，將除去前述氧化劑之藥液 當成鍍敷液使用之手段。 本發明之半導體裝置，其.特徵為在半導體基板及埋在前 述半導體基板上之絕緣膜形成之配線溝或接觸孔之金屬 膜’在^述配線溝或接觸孔上形成金屬膜表面做為障壁金 · 屬’ ϋ述金屬膜表面姓刻如配線溝或接觸孔側璧附近區域 、 相同深度。前述金屬膜也可介有之前述障壁金屬埋入在前 -10- 1225277
⑼
方法。在銅膜表面形成一含氨錯合之氧化膜，然後用蝕刻 法將其除去。具體而言，不是先蝕刻銅而是先調整 pH = 8〜10或pH = 9〜10之氨水及過氧化氫水之混合液使銅膜 表面形成比較厚的氧化膜，然後用稀鹽酸等沒有氧化力的 酸或稀氨水等鹼將此氧化膜蝕刻除去之方法。如前所述， 通常用氨水和過氧化氫水的混合液（sC 1)蝕刻銅時將pH 調至10.5〜1 1。依本發明之實驗得知pH在10以下表面會形 成氧化膜，超過1 〇銅將被蝕刻等特性。 在此浸泡在調整pH後的S C 1 1分鐘使其表面形成氧化
膜，用稀鹽酸選擇性蝕刻此氧化膜時銅之蝕刻量如圖6所 示。圖6之縱軸表示姓刻量（nm)，橫軸表示pH。如圖6所 示銅表面浸泡在約1 8%之過氧化氫水形成氧化膜，此時之 I虫刻量約4 n m。然而加入氨水中和ρ Η = 7時幾乎沒有氧 化，再加入更多的氨水，當ρ Η超過8時蚀刻量增加，ρ Η = 1 0 約11〜12 nm。pH超過10產生深藍色的氨錯離子溶解。圖 7(a)是處理前之銅表面’（b)是在ρΗ==9·5之氨水及過氧化 氫水混合液氧化1分鐘後用鹽酸蝕刻後之銅表面。圖8(a) 是在ρΗ= 10.2之氨水及過氧化氫水混合液蝕刻後之銅表 面。對照參考圖8(b)是鹽酸及過氧化氫水混合液（80 °C )蝕 刻後銅表面之SEM像。從圖得知用調整pH後的氨水及過 氧化氫水可得到表面不會粗·縫之姓刻方法。 為了在微影蝕刻時位置可以確實對合期望有30〜50 nm 的蝕刻，同時也期望蝕刻時間儘量縮短。只用過氧化氫水 處理可以得到較厚的氧化膜，蝕刻5 0 n m須要1 2〜1 3分鐘 -15- 1225277
(13) 氧〜μ ， 一 丄V ·」·丄w 7丄刀理攸丹斤j ζ υ y〇盟酸稀 釋50倍之稀鹽酸將表面之氧化膜除去，如此反復三次將銅 蝕刻約3 5〜4 0 nm的〇 · 2 5 // m線和空間配線之剖面圖如圖 在圖9中半導體基板5〇上形成層間絕緣膜51。在層 層配線為對像姓刻實際的銅配線。浸泡在ρ Η = 1 〇之S C 1 (過 化氫水··氨水：純水=1 〇 : 3 ·· 1 Ο Ο) 1分鐘後再用2 ο %鹽酸稀 5 0倍之稀鹽酸將矣而 > 备於睹仏l 一 & y ι 9所示 ----------_//^耳内，吧啄肤u。杜層 間絕緣膜51上形成障壁金屬52，在其侧壁上堆積配線溝 54,銅膜53埋入此配線溝54。對這種構造的銅配線用上述 方法形成氧化膜再姓刻處理彤士、 ~ !形成不粗糙的表面，然後在這 不粗糙的表面用濺鍍法或CVn^、丄 ' L VD寺万法將TaN或WN等堆積 第2障壁金屬，CMP等方法形# * 床形成障壁金屬5 5。 如圖9所示蝕刻銅鍈5 3形决π 成不粗糙的表面，愈靠近配線 溝54蚀刻量愈多，變成所謂 巧配線眉滑落斷面形狀。因此在 其上形成之障壁金屬55愈靠 近配線溝54膜的厚度愈大。對 於這種形狀用本發明之實施 有很多好處。即圖1〇是說明這 好處的杈式剖面圖。圖1〇( 疋如圖9所示謂配線肩滑落之 銅配線’如圖10(b)所示將 表面到底端部幾乎平坦之將::：被覆：障壁金屬’形成 下層配線之接觸孔配線必須-广為形成將上層配線接在 ^ ^ 貝、在下層配線上堆積層間絕緣 膜上7成接觸孔（穿孔）。如圖一 圖所不為形成接觸配線將接觸 孔在荆配線上面形成之查 斜列區姑㈤ '金屬上形成，而形成接觸孔之 蝕刻區域因對合偏差有— ^ 鉍刻被霜nr 刀進入層間絕緣膜。在此狀態 钱刻被覆下層配線之障壁 屬孓層間絕緣膜，層間絕緣膜 ( 膜"）之钱刻速率比鋼脸、 膜 < 蝕刻速率大則層間絕緣 膜部刀餘刻較多，如圖1 〇 )、圖10(b)虛線所示開口。 · •17- 1225277
(14)
如圖10(a)深的部分a其深度為b。圖10(b)深的部分a，其 深度為b’。因材質決定蝕刻速率b’ = b。在圖1 〇(a)中配線肩 滑落，深的部分之直徑較圖10(b)表面平坦時之直徑為大 (a>a’）。換言之在圖i〇(b)深的部分形成一袋狀空間，這地 方的方位比（b’/a，）明顯地較圖l〇(a)深的部分之方位比 (b/a)為大，因此在圖1〇(1))之接觸孔堆積障壁金屬時若用 鏡敷的方法將銅埋入接觸孔不易形成片狀銅膜。而在圖 i〇(a)之接觸孔堆積障壁金屬形成片狀銅膜就容易多了。 當然這不限於銅，所有半導體之配線或接觸的金屬膜均 可適用。不只在金屬膜上埋入障壁金屬，全面性形成障壁 層或直接堆積層間絕緣膜也可適用。 以下說明第4實施例。 將銅配線浸泡在ρΗ=ι〇之SC1 (過氧化氫水：氨水：純水 1 0.3.1 00)30秒再鐘後再浸泡在pH=1〇 5(混合比ΐ ι
SC1 1分3〇秒使其表面氧，然後用35%過氧化氫水以3/1 之比例用純水稀釋溶液除去表面之氧化膜，可以蝕刻約5 :、之後和罘3實施例相同的方法在上層用濺鍍法或 等方法將TaN或WN菩i金接哲。Λ 寺堆積乐2障壁金屬。然後再用CMPi; 研磨形成如圖3所示配線溝。 以下參照圖11說明第5實施例。 在本實施例說明適用於本如月之銅配 是說明銅配線^ # n 驟圖1 下舌杰π ★私 如圖所不銅配線形成程序^ 層間絕緣膜上形成配線溝。其次②在配線， ό’底邵及側面用漱鍍法或CVD等方法將^或難等堆; -18- 1225277 (15) 障壁金屬。然後③用賤鍍法或C V D等方法將銅埋入配綠 溝。然後④用CMP法只研磨銅或研磨銅及障壁金屬形成埵 入層間絕緣膜之鋼配線。然後⑤將CMP後之晶圓洗淨，若 有必要⑥銅姓刻晶圓的斜切部及裏面然後洗淨。最後⑦進 行本發明之銅凹蝕處理。 本發明之藥液可在銅表面形成氧化膜研磨時可保護内 部構造’可當成銅CMP之研漿。又通常在CMP後在同一裳 置或移至其他裝置用滾筒海綿或懸掛海綿等物理方法洗 淨，此時若用鹼性藥液，粒子洗淨效果顯著。本發明之藥 液其pH屬鹼性，對除去CMP後之研磨殘留粒子（鋁或矽等） 很有效。 用濺鍍法或CVD等方法將銅堆積在晶圓的斜切部及裏 面。將用濺鍍法或CVD等方法堆積的銅當成底層用鍍敷法 堆積時晶圓的斜切部及裏面堆積的銅被當成電極，然而錢 敷後就不要斜切部的銅。晶圓的斜切部及裏面是和其他在 半導體製造時因搬運或核對裝置接觸的部分。這種部分若 被銅污染’因製造裝置之媒介有可能污染其他晶圓。因此 有必要在銅CMP後將沾在晶圓的斜切部及裏面的銅蚀刻 洗淨。也可以在CMP之前洗淨。因為有可能在CMP時再度 被銅污染因此在CMP之後洗淨比較適宜。為了同時洗淨斜 切部及裏面’以迴轉葉片裝置轉動晶圓，從裏面噴出鹽酸 和過氧化氫水之混合液、硝酸、熱濃硫酸、$粦酸等氧化力 強的酸以溶解銅。然而此方法蝕刻處理後會產生表面裝置 部分的銅只在晶圓邊緣附近氧化的問題。這可能是從藥液 -19- 1225277
(16) 中氣化或蝕刻中發生的HCl、NOx、SOx等氣體殘留在銅 表面促使局部氧化。 為了要除去這種氧化膜以鹽酸或稀硫酸等氧化力弱的 酸處理’如此會產生只有在晶圓邊緣附近銅膜變薄的問 題。 為了避免這問題可採用將晶圓旋轉從正面用純水沖 洗’只有在斜切部裝設喷出藥液的噴嘴處理斜切部，同時 在裏面也噴出藥液處理裏面的方法。但是這又有必須裝設 從硬面專用的噴嘴這使製造裝置複雜提高裝置價格的問 、/兄且從程序面看若從表面沖洗純水往後就不能回收藥 液 '再使用循環蝕刻液因而增加藥液的使用量。 但若用本發明的方法CMP處理後的銅表面預先形成一 層厚厚的氧化膜，縱使只從裏面藥液處理也不會發生上述 的問題。因此在形成銅配線時如圖1 1所示銅CMP步驟從 (④）到銅凹餘（⑦）全部步驟可用同一藥液，且所有程序可 在同一裝置内進行。 可用同一藥液就表示製造半導體裝置時有簡略構造的 好處。在同一製置内連續處理就不必在每一步驟進行乾燥 可提南流程順暢的優點。例如圖1 4是上述同一室内進行半 導體_举 $ 、 衣置 < 概略圖，以圖1 1所示程序說明銅配線形成步 ° ^ a, 一 先①在層間絕緣膜上形成配線溝。其次②在配線溝 的底部及側面堆積障壁金屬。然後③用鍍敷將銅埋入配線 溝。此步驟在銅鍍敷槽6 1進行，然後④用CMP法只研磨銅 或研磨銅及障壁金屬形成埋入層間絕緣膜之銅配線。此步 •20- 1225277
(17) 騾在銅鍍敷槽62進行，然後⑤將CMP後之晶圓洗淨，此步 驟在銅鍍敷槽6 3進行。而後，進行⑥斜切部·裏面銅蝕刻 及洗淨。此一步驟係在姓刻槽6 4進行。最後⑦銅凹姓處理 在蝕刻槽64進行。這些銅鍍敷槽61、CMP裝置62、CMP 洗淨裝置6 3、蝕刻槽6 4、及處理槽6 5全部配置在室6 0内在 此可實施銅配線之形成之步驟。
在此室6 0各内部裝置裡從銅鍍敷槽6 1及蝕刻槽6 4排出 的藥液集中到處理槽6 5，監視銅濃度排除臭氧等氧化劑， 調整硫酸濃度再送回鍍敷槽6 1。如此本發明半導體製造裝 置可以做到資源回收。
圖15是半導體製造裝置之概略圖。如圖14所示半導體製 造裝置具有鍍敷槽61、蝕刻槽64、及處理槽65。處理槽65 是由濃度調整部及調整鍍敷液之鍍敷部所組成，供應且調 整將純水加入從蝕刻槽64排出的藥液、或調整形成鹽·錯 合體成分濃度的藥液，調整後的藥液供入鍍敷液部當做鍍 敷液。然後將此供入鍍敷槽（鍍敷室）61。從蝕刻室64排放 的藥液相較於在鍍敷室6 1使用過的鍍敷液量少時只須整 從蝕刻室64排放的藥液，而使用過的鍍敷液直接回收到鍍 敷部即可。 將鍍敷處理納入同一裝置内時所使用的鍍敷液若是硫 酸銅水溶液選用硫酸、若是氰化銅水溶選用氫氰酸，如此 蝕刻銅或氧化銅後的溶液和鍍敷液成分相同對程序有 利。因為蝕刻藥液和使用過的鍍敷液成分相同可以同時排 放處理。用蝕刻後藥液再進行鍍敷可得銅的利用效率極高 -21 - 1225277 广 4 i v o 1 (18) 的製程。 . 但是若只用稀硫酸或氫氰酸等氧化力弱的酸不容易姓 刻金屬銅。須加入賦予氧化力之氧化劑，使用反應後或分 解後變成水或氧之過氧化氫或臭氧較好。例如在鍍敷液加 - 入10%之硫酸鋼水溶液，以10%之硫酸（+過氧化氫水或臭 氧）蝕刻銅或鋼氧化物，蝕刻液中用離子濃度或重量、吸 光度等線内監视銅濃度，超過10 0/。時則回收再使用。當然 也可以用和鍍敷液不同濃度的硫酸，也可以不循環使用。 籲 又因不容易只增加銅濃度，最好使銅濃度高到硫酸濃度以 上。最後用活性碳過濾器或UV燈照射將蝕刻液中的過氧 化氫或臭氧分解，監祝銅濃度或硫酸濃度加入硫酸或純 水，加熱處理或以逆溱透用半透膜處理濃縮作成10%之硫 酸銅水溶液。然後加入鍍敷必須的添加劑鍍敷時使用。此 時也可同時調整使用過的鍍敷液濃度。可將濃度調整過的 藥液一點一點加入鍍敷液内。當然濃度監視或氧化劑除去 機構、藥液濃縮機構不限於以上所提及之物。 隹 此種姓刻後的溶液當成鍍敷液再利用之程序及裝置不 限於銅，如Au、Ag、Ti等所有可鍍敷的金屬都可適用。 以下參照圖12說明第6實施例。 圖1 2是說明銅凹蝕時氨處理晶圓配線電阻和晶圓迴轉 數依存性之特性圖。在此實施例以迴轉式葉片裝置進行銅 凹蝕步驟，（1) · NHi〇 H :H2_〇2_:DIW (30:100:1000)，60 秒， - 1 0 00 rpm，（2) · NH 生OH: H2J32JDIW (100:100:100)，60 秒， 1000 rpm，（3)· HC1 (30:1000)，5秒，1000 rpm處理可凹 -22- (19)1225277 蝕”力5”0 nm的銅。但以鹽酸處理後的銅表面氧化加速。銅 表面氧化造成配線實際有效的銅減少，配線截面積降低配 ’泉私阻上升等問題。又銅表面和上部障壁金屬之間形成銅 氧化膜，裝置上上部的穿孔的接觸電阻上升，可能因產生 電容造成延遲的原因。在程序上上部障壁金屬形成時控制 凹蚀處後的時間必須迅速在上部堆積障壁金屬或CMp處 理時可能發生剥落等問題。 然而在鹽酸處理後進行氨水處理，可以抑制氧化。但氨 水a蝕刻銅過度處理造成表面粗糙的原因。使用迴轉式 葉片裝置以氨水蝕刻銅知蝕刻特性依迴轉數改變。以下的 圖形疋8吋矽阳圓上〇 · 3 5 # m之銅配線（配線電阻約3 4 2 m Ω )在晶圓面内19薄片形成後將銅用3·5%之氨水蝕刻約1〇 分鐘後其配線電阻（q )以晶圓迴轉數為參數作圖。配線的 銅被#刻截面積減少電阻上升。3 X 1 〇4 m Ω表示銅完全被 蝕刻。此時晶圓面内蝕刻之均一性不良電阻上升分布不
均，均一性好則分布不均小。超過1 〇 〇 〇 rp m以上分布不均 變小，1 475 rpm附近有極小值，在1 600 rpm和接近1 000 rpm 有相同的分布不均。 又在2000rpm下也可進行蝕刻，但400nm的銅完全被蝕 刻。因為只希望在表面處理.所以這種高速蝕刻條件不是很 適宜。迴轉數超過1600rpm以上可預知触刻速率會上升’ 因此處理條件以1 6 0 0 r p m以下為宜。是以’為抑制氧化之 氨處理，以1000 rpm以上1600 rpm以下為宜。 在此上述凹钱程序後實際進行氨處理’在清潔室環境下 -23- 1225277
(22) 8 間隔物膜 9 穿孔配線（接觸配線） 10、20、40、50、100 半導體基板 60 室 61 62 63 64 65 銅鍍敷槽 CMP室 CMP後洗淨裝置
蝕刻槽 處理槽
-26-

Claims (1)

12 降 77 正替換 屬1)920)如8〇號專利申請案 中文申請專利範圍替換本(93年7月） 拾、申請專利範圍 1. 一種半導體裝置，其特徵為具有：半導體基板、埋在 前述半導體基板上之絕緣膜中所形成的配線溝或接 觸孔内之金屬膜，及在前述配線溝或接觸孔内以覆蓋 金屬膜表面之方式形成之障壁金屬；前述金屬膜表面 係以前述配線溝或接觸孔之中央部最高，並朝前述配 線溝或接觸孔之周邊變低。 2. 如申請專利範圍第1項之半導體裝置，其中前述金屬 膜係介以障壁金屬埋入前述配線溝或接觸孔。 3. 如申請專利範圍第1項或第2項之半導體裝置，其中具 有將以覆蓋在前述金屬膜表面的方式形成之障壁金 屬埋入前述配線溝或接觸孔之構造。
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