JP5076482B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5076482B2 JP5076482B2 JP2006340102A JP2006340102A JP5076482B2 JP 5076482 B2 JP5076482 B2 JP 5076482B2 JP 2006340102 A JP2006340102 A JP 2006340102A JP 2006340102 A JP2006340102 A JP 2006340102A JP 5076482 B2 JP5076482 B2 JP 5076482B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Description
図4(A),(B)は、本発明の第1の実施形態による、自己形成バリア膜の形成工程を説明する図である。
[第2の実施形態]
図7(A)〜(C)は、本発明の第2の実施形態による自己形成バリア膜の形成工程を説明する図である。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
[第3の実施形態]
図9(A)〜11(I)は、本発明の第3の実施形態によるCu配線構造を有する半導体装置の製造工程を示す。
HCOOH+Mn→Mn(HCOO)2+H2 (1)
により、気相反応生成物Mn(HCOO)2およびH2を形成し、その結果、Mnは前記Cu層27から系外へと、連続的に除去される。
4HCOOH+2MnO2→Mn(HCOO)2+H2O+O2 (2)
により、気相反応生成物Mn(HCOO)2、H2OおよびO2を形成し、その結果、Mnは前記Cu層27から系外へと、連続的に除去される。
[第4の実施形態]
次に本発明の第4の実施形態によるCu配線構造の作製工程を、図12(A)〜(C)を参照しながら説明する。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
[第5の実施形態]
次に本発明の第5の実施形態によるCu配線構造の作製工程を、図13(A)〜図14(D)を参照しながら説明する。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
[第6の実施形態]
図15は、本発明の方法により作製されたCu多層配線構造を有する本発明の第6の実施形態による半導体装置40の構成を示す。
前記開口部中にCu−Mn合金層を形成する工程と、
前記Cu−Mn合金層上にCu層を堆積し、前記開口部を充填する工程と、
前記Cu−Mn合金層中のMn原子と前記絶縁膜との反応により、バリア層を形成する工程と、
を含む半導体装置の製造方法であって、
前記バリア層を形成する工程は、前記Cu層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露しながら実行されることを特徴とする半導体装置の製造方法。
前記開口部内にCu−Mn合金層を形成する工程と、
前記内壁面上に、前記Cu−Mn合金層中のMn原子と前記絶縁膜との反応により、バリア層を形成する工程と、
前記Cu−Mn合金層上にCu層を堆積し、前記開口部を充填する工程と、
を含むことを特徴とする半導体装置の製造方法であって、
前記Cu層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露することを特徴とする半導体装置の製造方法。
前記開口部内にCu−Mn合金層を形成する工程と、
前記内壁面上に、前記Cu−Mn合金層中のMn原子と前記絶縁膜との反応により、バリア層を形成する工程と、
前記Cu−Mn合金層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露する工程と、
前記Cu−Mn合金層を前記雰囲気に曝露する工程の後、前記Cu−Mn合金層上にCu層を堆積し、前記開口部を充填する工程を含むことを特徴とする半導体装置の製造方法。
12,14,22,24 エッチングストッパ膜
13A,23A ビアホール
15A,25A 配線溝
16,26 Cu−Mn合金膜
17,27 Cu層
18M,28M 拡散バリア膜
18,28 酸化マンガン膜
40 半導体装置
41 シリコン基板
41A 素子領域
41B 素子分離領域
41a,41b,41c,41d 拡散領域
42 ゲート絶縁膜
43 ゲート電極
43a,43b 側壁絶縁膜
44〜47 層間絶縁膜
44P,44Q,46P,46W,47P,47Q コンタクトプラグ
45A,45B,46A〜46C,47A,47B Cu配線パターン
45a,45b,46a〜46c,47a,47b 拡散バリア膜
61 シリコン基板
62 シリコン酸化膜
63 Cu−Mn合金層
63M 自己形成バリア膜
64 Cu層
Claims (7)
- 絶縁膜中に、内壁面で画成された開口部を形成する工程と、
前記開口部中にCu−Mn合金層を形成する工程と、
前記Cu−Mn合金層上にCu層を堆積し、前記開口部を充填する工程と、
前記Cu−Mn合金層中のMn原子と前記絶縁膜との反応により、バリア層を形成する工程と、
を含む半導体装置の製造方法であって、
前記バリア層を形成する工程は、前記Cu層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露しながら実行され、
前記雰囲気は、蟻酸(HCOOH)を含むことを特徴とする半導体装置の製造方法。 - 絶縁膜中に、内壁面で画成された開口部を形成する工程と、
前記開口部内にCu−Mn合金層を形成する工程と、
前記内壁面上に、前記Cu−Mn合金層中のMn原子と前記絶縁膜との反応により、バリア層を形成する工程と、
前記Cu−Mn合金層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露する工程と、
前記Cu−Mn合金層を前記雰囲気に曝露する工程の後、前記Cu−Mn合金層上にCu層を堆積し、前記開口部を充填する工程を含み、
前記雰囲気は、蟻酸(HCOOH)を含む半導体装置の製造方法。 - バリア層を形成する工程と、前記Cu−Mn合金層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露する工程とは、同時に実行されることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記Cu−Mn合金層を、Mnと反応して気相反応生成物を形成する雰囲気に曝露する工程は、前記バリア層を形成する工程の後で実行されることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記雰囲気は、さらにMnを酸化し、さらにMn酸化物と反応して気相反応生成物を形成することを特徴とする請求項1〜4のうち、いずれか一項記載の半導体装置の製造方法。
- 前記曝露工程は、350℃以上で400℃を超えない加熱下において実行されることを特徴とする請求項1〜5のうち、いずれか一項記載の半導体装置の製造方法。
- 前記曝露工程は、200〜1000Paのプロセス圧において実行されることを特徴とする請求項1〜6のうち、いずれか一項記載の半導体装置の製造方法。
Priority Applications (2)
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JP2006340102A JP5076482B2 (ja) | 2006-01-20 | 2006-12-18 | 半導体装置の製造方法 |
US11/654,688 US7935624B2 (en) | 2006-01-20 | 2007-01-18 | Fabrication method of semiconductor device having a barrier layer containing Mn |
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JP2006013155 | 2006-01-20 | ||
JP2006013155 | 2006-01-20 | ||
JP2006340102A JP5076482B2 (ja) | 2006-01-20 | 2006-12-18 | 半導体装置の製造方法 |
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JP2007221103A JP2007221103A (ja) | 2007-08-30 |
JP5076482B2 true JP5076482B2 (ja) | 2012-11-21 |
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Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008091645A (ja) | 2006-10-02 | 2008-04-17 | Tokyo Electron Ltd | 半導体製造装置、半導体装置の製造方法及び記憶媒体 |
JP5010265B2 (ja) * | 2006-12-18 | 2012-08-29 | 株式会社東芝 | 半導体装置の製造方法 |
JP2008218659A (ja) * | 2007-03-02 | 2008-09-18 | Tokyo Electron Ltd | 半導体装置の製造方法、半導体製造装置及びプログラム |
JP5196467B2 (ja) * | 2007-05-30 | 2013-05-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
JP2009004518A (ja) * | 2007-06-20 | 2009-01-08 | Kobe Steel Ltd | 薄膜トランジスタ基板、および表示デバイス |
WO2009001780A1 (ja) * | 2007-06-22 | 2008-12-31 | Rohm Co., Ltd. | 半導体装置およびその製造方法 |
KR20090038624A (ko) * | 2007-10-16 | 2009-04-21 | 주식회사 동부하이텍 | 배리어 금속막 형성 방법 |
JP5264187B2 (ja) * | 2008-01-08 | 2013-08-14 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP5366235B2 (ja) | 2008-01-28 | 2013-12-11 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
JP5343369B2 (ja) | 2008-03-03 | 2013-11-13 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
JP5441345B2 (ja) * | 2008-03-27 | 2014-03-12 | 富士フイルム株式会社 | 研磨液、及び研磨方法 |
JP2010040771A (ja) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2010040772A (ja) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | 半導体装置の製造方法 |
JP5353109B2 (ja) | 2008-08-15 | 2013-11-27 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2010171063A (ja) * | 2009-01-20 | 2010-08-05 | Kobe Steel Ltd | 半導体配線の製造方法 |
US8168528B2 (en) * | 2009-06-18 | 2012-05-01 | Kabushiki Kaisha Toshiba | Restoration method using metal for better CD controllability and Cu filing |
US8749028B2 (en) | 2009-07-01 | 2014-06-10 | Hitachi, Ltd. | Semiconductor device with silicon through electrode and moisture barrier |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
JP2014062312A (ja) * | 2012-09-24 | 2014-04-10 | Tokyo Electron Ltd | マンガンシリケート膜の形成方法、処理システム、半導体デバイスの製造方法および半導体デバイス |
US9184093B2 (en) | 2013-03-15 | 2015-11-10 | Applied Materials, Inc. | Integrated cluster to enable next generation interconnect |
US9997457B2 (en) | 2013-12-20 | 2018-06-12 | Intel Corporation | Cobalt based interconnects and methods of fabrication thereof |
KR102190654B1 (ko) * | 2014-04-07 | 2020-12-15 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
JP6181006B2 (ja) * | 2014-07-09 | 2017-08-16 | 東京エレクトロン株式会社 | めっき前処理方法、めっき処理システムおよび記憶媒体 |
FR3055166B1 (fr) * | 2016-08-18 | 2020-12-25 | Commissariat Energie Atomique | Procede de connection intercomposants a densite optimisee |
US10256191B2 (en) | 2017-01-23 | 2019-04-09 | International Business Machines Corporation | Hybrid dielectric scheme for varying liner thickness and manganese concentration |
Family Cites Families (10)
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JPH0262035A (ja) | 1988-08-29 | 1990-03-01 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置 |
US5130274A (en) | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
US6387805B2 (en) | 1997-05-08 | 2002-05-14 | Applied Materials, Inc. | Copper alloy seed layer for copper metallization |
JP3907151B2 (ja) * | 2000-01-25 | 2007-04-18 | 株式会社東芝 | 半導体装置の製造方法 |
JP2001326192A (ja) | 2000-05-16 | 2001-11-22 | Applied Materials Inc | 成膜方法及び装置 |
JP3734447B2 (ja) | 2002-01-18 | 2006-01-11 | 富士通株式会社 | 半導体装置の製造方法および半導体装置の製造装置 |
JP4478038B2 (ja) * | 2004-02-27 | 2010-06-09 | 株式会社半導体理工学研究センター | 半導体装置及びその製造方法 |
JP4503356B2 (ja) * | 2004-06-02 | 2010-07-14 | 東京エレクトロン株式会社 | 基板処理方法および半導体装置の製造方法 |
JP2007109687A (ja) * | 2005-10-11 | 2007-04-26 | Sony Corp | 半導体装置の製造方法 |
JP2007149813A (ja) * | 2005-11-25 | 2007-06-14 | Sony Corp | 半導体装置の製造方法 |
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US20070173055A1 (en) | 2007-07-26 |
JP2007221103A (ja) | 2007-08-30 |
US7935624B2 (en) | 2011-05-03 |
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