TW201119007A - Electrical interconnect for die stacked in zig-zag configuration - Google Patents
Electrical interconnect for die stacked in zig-zag configuration Download PDFInfo
- Publication number
- TW201119007A TW201119007A TW099120462A TW99120462A TW201119007A TW 201119007 A TW201119007 A TW 201119007A TW 099120462 A TW099120462 A TW 099120462A TW 99120462 A TW99120462 A TW 99120462A TW 201119007 A TW201119007 A TW 201119007A
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- Prior art keywords
- die
- conductive material
- assembly
- layer
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- H01L2924/14—Integrated circuits
Description
201119007 六、發明說明: 本申請案根據R.公司等於2〇09年6月26日所提出名稱 爲“用於以鋸齒組態堆疊之晶粒之電連接”之美國暫時申請 案61/220,986,且倂提於此以供參考。 【發明所屬之技術領域】 本發明係有關積體電路晶片之電連接,特別是堆疊晶 粒之電互連。 【先前技術】 典型的半導體晶粒具有形成積體電路之前(主動)側 、背側及側壁。側壁與前側相接於前緣,並與後側相接於 後緣。半導體晶粒通常設有互連墊(晶粒墊),其位於晶 粒上電路之電互連前側,裝置中另一電路佈設晶粒。通常 ,晶粒墊包含諸如銅或鋁之導電或金屬化之金屬。 所提供某些晶粒在沿一或更多晶粒邊緣之前側具有晶 粒墊,且此等均稱爲周緣墊晶粒。所提供其他晶粒墊在接 近晶粒中央之前側上配置成一行或兩行,且此等均稱爲中 央墊晶粒。某些晶粒具有配置成區域陣列之墊。然而,晶 粒墊可如所提供,配置於晶粒中,該晶粒可“重選路”以提 供適當的互連墊配置於晶粒之一或更多邊緣。 曾提議多種方法來增加積體電路晶片封裝中之主動半 導體電路之密度,惟將封裝尺寸(封裝映罩表面、封裝厚 度)減至最小。於製造具有較小映罩表面之高密度封裝之 -5- 201119007 方法中,互疊及安裝相同或不同功能之二或更多半導體晶 粒於封裝基板上。 S. McElrea等人於2 0 0 8年五月2 0曰提出申請,名稱 爲“電連接堆疊總成”之美國申請案1 2/1 24,077說明一種堆 疊晶粒組態,其中晶粒上之互連墊藉導電互連材料之引線 電連接。於某些組態中,堆疊中之相鄰晶粒設有沿晶粒邊 緣配置於前側之互連墊,且上方晶粒之邊緣之緣相對於其 下方之晶粒之邊緣錯位。該錯位顯示下晶粒上互連墊區域 之至少一部分,俾下晶粒上之墊可用來與位於上方之晶粒 之墊電連接。導電互連材料係就像例如可固化導電環氧樹 脂之導電聚合物。較大堆疊總成可藉由於模組設計中建構 錯位堆疊晶粒單元及接著堆疊此等單元製造。一個此種模 組單元可藉對齊及連接之個別模組單元之互連端反轉及互 疊安裝;所形成兩層總成提供鋸齒組態。 T. Caskey等人於2008年五月20日提出申請,名稱爲 “藉由脈衝調配形成之電互連”之美國申請案12/124,097說 明一種堆疊中晶粒電互連方法,及藉由於一系列脈衝中原 位沉積電互連材料以形成連續電互連之具有基板之堆疊晶 粒。互連材料可爲可固化材料,其可在未固化或局部固化 狀態下沉積;且該材料可於調配後之中間步驟局部或額外 固化;且可在完成調配時,完全固化。適當互連材料包含 充塡粒子形式之導電材料之聚合物,就像例如充塡金屬聚 合物’其例如包含金屬充塡環氧樹脂、金屬充塡熱固聚合 物、金屬充塡熱塑聚合物或導電油墨。 -6- 201119007 【發明內容】 於本發明之一般態樣中,特點在於安裝並隆起於支撐 上方’以及電連接於支撐中之電路之晶粒(或晶粒堆疊) 。導電材料柱形成於支撐之安裝側之一組接合墊上,且隆 起晶粒(隆起晶粒堆疊之至少一晶粒)藉使晶粒上互連墊 接觸柱之導電材料之引線電連接於支撐,並透過此等柱電 連接於該支撐。 於某些實施例中,下晶粒或下晶粒堆疊或半導體封裝 位於支撐與隆起晶粒間;且於某些實施例中,下晶粒或下 晶粒堆疊或半導體封裝電連接於支撐。於某些實施例中, 下晶粒堆疊係下成層錯位堆疊晶粒總成,且第一層中之晶 粒以晶粒對晶粒方式電連接,又,下層藉使晶粒上互連墊 接觸柱之導電材料之引線以及一組支撐上之接合墊,電連 接於支撐。 於某些實施例中,隆起晶粒堆疊係成層錯位堆疊晶粒 總成,其中晶粒層之互連緣面對第一方向,且互連晶粒墊 緣對準柱。 於本發明各個實施例中,特點在於以鋸齒組態成層錯 位堆疊晶粒總成,其中第一(下)層之互連緣面對第一方 向,且堆疊於第一層之第二(上)層之互連緣面對異於第 一方向之第二方向。第二層互連緣方向可正對或正交第一 層互連緣方向。第一層中之晶粒以晶粒對晶粒方式電連接 ,又,該層藉使晶粒上互連墊接觸之導電材料之引線以及 201119007 一組支撐上之接合墊,電連接於支撐。導電材料柱形成於 第二組接合墊上,且第二層之晶粒以晶粒對晶粒方式電互 連,又該層藉使晶粒上互連墊接觸柱之導電材料之引線電 連接於支撐,並透過多數柱電連接於基板。 導電材料包含於聚合物基質中的金屬粒子。適當材料 包含能以可流動形式沉積且之後硬化或容許硬化以形成導 體之材料。互連材料可爲可固化材料,且可沉積成未固化 或局部固化狀態;且該材料可於沉積後之中間階段局部或 額外固化,並可在沉積完成時完全固化。適當的互連材料 包含充塡粒子形式之導電材料之聚合物,例如金屬充塡聚 合物,其例如包含金屬充塡環氧樹脂、金屬充塡熱固化聚 合物、金屬充塡熱塑聚合物以及導電油墨。 互連材料可藉適於特定材料之任何技術沉積。於某些 實施例中,材料可使用噴嘴或針調配或噴灑成霧,或網版 印刷或噴墨印刷;材料可透過噴射或噴嘴連續調配或脈動 調配例如成滴狀。 於本發明之另——般態樣中,特點在於一種藉由以下 步驟將安裝並隆起於支撐上方之晶粒(或一疊晶粒)電連 接於支撐中之電路之方法:於支撐之安裝側之一組接合墊 上形成多數導電材料柱;以及形成導電材料之引線,各該 引線與隆起晶粒(或在隆起疊之晶粒的至少一晶粒)上之 互連晶粒墊及柱接觸。於某些實施例中,引線跨柱與互連 晶粒墊間之間隙。於某些實施例中,形成柱包括沉積可固 化導電柱材料於接合墊上及固化沉積之引線材料。於某些 201119007 實施例中,形成引線包括沉積與柱接觸之可固化導電引線 材料,以及固化沉積之引線材料。 於本發明之一般態樣中,特點在於一種藉由以下步驟 製造以鋸齒組態成層錯位堆疊之晶粒總成之方法:堆疊或 安裝第一(下)層於支撐上’配置成第一(下)層之互連 緣面對第一方向,俾第一層中至少最下方晶粒上之互連墊 與該支撐上之第一組接合墊對齊;晶粒對晶粒電互連該第 ~層中之晶粒’並藉由形成第一層導電材料引線,電連接 該層於該支撐’該第一層導電材料引線之每一者與該晶粒 上之至少一互連墊以及該等第一組接合墊接觸;堆疊或安 裝第二(上)層於該第一層上方,配置成第二(上)層之 互連緣面對第二方向;形成導電材料柱於該支撑上之第二 組接合墊上;以及形成導電材料之第二(上)層引線,各 該引線與該第二(上)層中至少一晶粒上之互連晶粒墊及 該柱接觸。於某些實施例中,形成第一層導電材料引線包 括沉積可固化導電引線材料,該導電引線材料與至少一下 層晶粒上之晶粒墊接觸’以及固化沉積之引線材料。於某 些實施例中,形成第二層引線包括跨該柱與該互連晶粒墊 間之間隙形成引線。於某些實施例中,形成柱包括沉積可 固化導電柱材料於接合墊及固化沉積之引線材料。於某些 實施例中,形成第二層導電材料引線包括沉積可固化導電 引線材料,該導電引線材料與至少一上層晶粒上之晶粒墊 接觸及固化沉積之引線材料。柱、第一層引線及第二層引 線可由相同或不同材料形成。
S -9 - 201119007 於某些實施例中,製造成層錯位堆疊之晶 法包括於堆疊或安裝第一層之後及形成第一層 以保形介電塗層塗布該總成,並形成多數開口 第一層引線接觸之至少經選擇之晶粒墊及接合 實施例中,製造成層錯位堆疊之晶粒總成之方 疊或安裝第二層之後及形成該等柱之前,以保 塗布該總成,並形成多數開口於待與該等柱接 選擇之第二層晶粒墊及接合墊。 【實施方式】 現在參考說明本發明之選擇性實施例之圖 說明本發明。此等圖式顯示本發明之特點及其 和構造間之關係,惟其未按比例繪製。爲改進 度,於圖式中顯示本發明之實施例,對應於其 件的元件並未全部特別另標元件符號,雖則其 中均可馬上辨識。亦爲顯示之清晰度,於圖式 些特點,畢竟其等對本發明瞭解不必要。於說 點,可參考圖式中諸視點之位向,使用“上方’ “上”、“下”、“頂部”、“底部”等,此等用辭不 中裝置之位向。 第1A圖以俯視圖顯示安裝於支撐上之錯位 之配置之圖式,各晶粒具有互連墊,其配置在 緣之一邊緣;且第1B圖如第1A圖中1B-1B所示 安裝於支撐上之堆疊。於此例子中,堆疊包 粒總成之方 引線之前, 於待與該等 墊。於某些 法包括於堆 形介電塗層 觸之至少經 式,進一步 與其他特點 顯示之清晰 他圖式之元 在所有圖式 中未顯示某 明中的某些 ’、“下方”、 擬限制使用 堆疊晶粒1 〇 鄰接前晶粒 ,俯視顯示 含七個晶粒 -10- 201119007 141,142,143,1 44, 1 45,146,147,各安裝成晶粒之 側背離支撐1 7。參考堆疊中之最上方晶粒1 47,例如 連墊1 4 8位在沿前晶粒緣1 4 9之一行1 4 2中。此例子中 粒147藉電絕緣保形塗層144覆蓋於所有表面(背表面 表面及側壁)上,該電絕緣保形塗層144設有露出互 148之開口 145。如於此等例子中,堆疊中之連續塗佈 靠在另一個上,俾上晶粒之背側上之塗層可接觸下晶 前側上之塗層。於其他例子中,保形塗層可覆蓋較所 粒表面小,或者其可僅覆蓋一或更多晶粒表面之一部 —般而言,電絕緣保形塗層可至少形成於須要與其他 或表面電絕緣之表面或特點,此等其他特點或表面可 成之總成接觸。任選地或額外地,晶粒附接膜可層疊 或更多晶粒之背側。 於第1 A及1 B圖所示例子中,各晶粒具有位於沿一 粒緣(“互連”緣)之邊緣之互連墊,且堆疊中之連續 配置成其個別互連緣面朝堆疊之相同面。堆疊中之連 粒沿正交晶粒緣之方向位移(錯位),多數墊沿晶粒 且於在此所示之例子中,此錯位使諸墊在各下晶粒中 露出。該組態提供梯狀晶粒堆疊,且電連接形成於此 級上方。 堆疊安裝在支撐17(例如封裝基板)上,該支撐 有一行露出於晶粒安裝表面171之接合位置1:72之行1 接合位置連接於(或構成一部分)支撐中之電路(未 )。該晶粒附著於基板之晶粒安裝表面1 7 1,並配置 主動 ,互 之晶 、前 連墊 直接 粒之 有晶 分; 特點 與完 於一 前晶 晶粒 續晶 緣, 完全 等梯 17具 73 » 圖示 成第 3 -11 - 201119007 —(最下方)晶粒1 4 1之前側壁沿接合位置1 72之ί 齊。於在此所示例子中,最下方晶粒之前側壁重疊 置至很小程度;於其他例子中,最下方晶粒之前側 接合位置之行後退,或可重疊接合位置至較大程度 此等例子中,第一晶粒之塗佈背側可直接接觸晶粒 面171,並可用來附著該堆疊於支撐。任選地,晶 膜可層疊於第一晶粒之背側,以附著該堆疊於支撐 如第1 C圖所示,於堆疊中,晶粒電連接(晶粒 ),且堆疊藉配設成與例如墊148及接合墊172接觸 材料之引線174,電連接於支撐。互連材料可爲導 物,就像包含導電材料之粒子之聚合物基質。該材 諸如可固化聚合物之可固化材料,例如就像是導電 脂(例如充塡銀之環氧樹脂):且互連可藉由將未 材料形成爲預定圖案,且此後固化材料以獲得與接 接合位置之電接觸,並確保其間引線之完整性來形 材料可爲導電油墨,其可於載體中包含導電粒子, 或不可包含聚合物基質。 如於美國申請案1 2/124,097中所說明,可藉由 計中建構錯位晶粒堆疊單元,並接著堆疊這些單 成較大堆疊晶粒總成。可藉對齊及連接之個別模組 反轉及互疊安裝一個此種模組單元;例如依第2Α, 示,形成之二層總成提供鋸齒組態。第一錯位晶粒 成第一模組單元(第一層)210,其可安裝於及電 支撐217上之接合墊272;且可藉對齊及連接之互 Ϊ 173 對 接合位 壁可從 。如於 安裝表 粒附接 〇 對晶粒 之互連 電聚合 料可爲 環氧樹 固化之 合墊及 成。該 且其可 於模組 元,製 單元, 2 Β圖所 堆疊構 連接於 連 214, -12- 201119007 224之端部’反轉及安裝第二模組單元(第二層)212於第 一層210上方。於第2A圖中舉例顯示形成之總成。一隔件 (於第2A圖中未圖示)可設在第一與第二層間。如可理解 ’在第一與第二模組單元相同情況下,當第二單元反轉時 ’互接端之個別墊行反平行;亦即,現在,第一單元上之 第一互連對齊第二晶粒上之最後互連。於此種組態中,可 能需要重選路電路來將適當的個別特點連接於晶粒上。重 選路電路可設在第一單元上之頂部晶粒之主動層;或者, 在包含隔件情況下,該隔件可構成一插入件(於第2A圖中 未圖示)’其包含一或更多介電層及一或更多導電重選路 層。第2B圖顯示第二層安裝於第一層上方惟未翻轉之組態 。在此,第二層220之互連224之端部接近第一層210中頂 部晶粒之相對緣。包含至少一介電層2 1 6 (就像例如玻璃 )及至少一圖型化導電層244之插入件位於諸模組單元間 ,以提供從第一層210之一緣上之互連214之端部至第二層 220之一(相對)緣上之互連224之端部之重選路。 可利用特定互連材料之流變性質(就像例如黏度或觸 變性)來提供具有控制形狀之沉積。特別是,對某些材料 而言,在調配脈衝完成後的一段時間內,沉積團塊之一部 分可保持與沉積工具接觸,且可在分離完成前移動該工具 。在未固化狀態下,具有較高黏度及觸變性之導電聚合物 材料可在沉積期間,藉由於調配脈衝完成後不久移動沉積 工具,予以成形,以沿選擇方向拉出材料之“尾部” ’形成 具有選擇形狀之互連。結果’可藉工具之方向及移動速率
S -13- 201119007 及材料之流變性質判定沉積團塊之形狀。 如以上所述’第1A,1B,1C, 2A及2B圖所示例子中之 錯位晶粒堆疊如圖示具有七個晶粒。考慮具有其他數目之 晶粒之錯位堆疊,且通常較常見的是偶數晶粒(例如每— 錯位堆疊有四個晶粒或八個晶粒)。 參考第3A圖,例如依圖示附接液滴304於支撐320 (諸 如晶粒上之墊,或基板上之接合墊)上之電接觸328。於 圖示例子中,在液滴形成期間,使工具梢朝向電接觸328 ,並調配材料團塊於接觸。接著,當材料團塊仍與工具梢 接觸時,垂直移動離開目標以向上拉出材料“尾巴”。最後 ,液滴團塊與工具梢分離,且形成之液滴304具有大致錐 形。適於形成成形液滴之材料包含導電環氧樹脂(充塡金 屬之環氧樹脂),其在未固化狀態下,具有約3 000 〇Cps或 更大的黏度及/或約6.5或更大的觸變指數。如可瞭解,黏 度及/或觸變度不得太高,否則,材料沒有用,否則其無 法與互接端子良好接觸。 以上參考及倂提於此供參考之美國申請案12/124,097 說明形成一系列此種大致錐形之自由立起液滴,此等液滴 於晶粒堆疊面上相互鄰接’提供接觸互連端子之材料柱。 此種柱組態可在垂直相鄰之晶粒間有很大空隙,以致互連 引線須在無側面支撐下垂直越過該間時特別有用。如以上 參考及倂提於此供參考之美國申請案12/124,097所說明, 這可提供於具有相互安裝及藉隔件分隔之多數晶粒堆疊中 ;或藉晶粒之交錯配置(亦即’在待連接晶粒間之間隙大 -14 - 201119007 約等於(或略微超過)夾裝之錯位晶粒之厚度情況下)提 供:或於具有長形堆疊晶粒之晶粒堆疊中,各晶粒在位向 上相對於下方之晶粒成90°。 如於美國申請案1 2/1 24,097中進一步說明,工具可在 異於垂直遠離目標之其他方向中移動,且可形成各種有用 液滴。例如參考第3B圖,如圖所示,晶粒錯位堆疊341, 342,343, 344安裝於基板317上,該基板317在堆疊安裝側 具有電連接位置(諸如接合墊)3 72。此例中的所有晶粒 具有例如周緣墊348,其沿晶粒之邊緣,配置於互接緣。 堆疊中的每一晶粒可相對於下方之晶粒位移,露出墊區域 之至少一部分(於圖示例子中露出墊的全部)。如圖示, 第一互接液滴314將第一晶粒341上之晶粒墊348連接至基 板317中的接合墊372。爲形成液滴,使工具朝向第一目標 接合墊,並將材料團塊調配於接合墊。接著,當材料團塊 仍與工具梢部接觸時,該工具移動,首先向上,側面離開 第一目標,接著向下,側面朝晶粒墊3 48 (如斷箭所示) ,以成弧形朝第二墊拉出材料“尾部”。可同樣形成第二及 後續液滴以連接連續晶粒上之墊,形成晶粒對晶粒互連。 根據第4A、4B及4C圖所示發明實施例,以鋸齒組態 成層錯位堆疊之晶粒總成安裝及電連接於支撐。於此例子 中,包含各具有四個錯位堆疊晶粒之二層之堆疊晶粒總成 428安裝於支撐(諸如封裝基板)447。於本例子中,下層 包含晶粒441,442, 443,444;且上層包含晶粒445,446, 4 4 7,4 4 8。且各晶粒之後側層疊晶粒附接膜(分別爲4 3 1,
S -15- 201119007 43 2,43 3,43 4,43 5,43 6,43 7,43 8 )。互接晶粒墊(例如 548 ; 6M )配置於接近各晶粒之互接緣之晶粒緣。互接材 料之引線404形成於第一層之互接面,其接觸互接晶粒墊 (例如5 48 )以形成晶粒對晶粒互連,並接觸支撐上第一 行之接合墊472,以形成層對支撐電連接。互連材料之柱 502形成接觸支撐上第二行之接合墊474;且互連材料之引 線5 04形成於第二層之互連面上方,接觸互接晶粒墊(例 如648 )以形成晶粒對晶粒互連,並接觸柱5 02,以形成層 對支撐電連接。 基板47 7於面對堆疊安裝面之表面包含焊墊4 76,其用 來將總成二級電連接(例如作爲焊墊格柵陣列或球形格柵 陣列或標記陣列)於裝置中的下層電路(未顯示於此等圖 中),其中佈置總成供使用。接合墊472,47 4及焊墊47 6連 接於圖案化之導電層,並於基板中爲一或更多介電層所分 隔,且基板中之圖案化導電層藉貫穿單一或多數介電層之 通孔連接。 如第4 A、4B及4C圖所示,用來建構以鋸齒組態成層 錯位堆疊之晶粒總成安裝及電連接於支撐之程序例子之步 驟顯示於第5A、5B及5C圖;第6A、6B及6C圖;第7A、7B 及7C圖:第8A、8B及8C圖;以及第9A、9B及9C圖。以下 係此種程序之說明。 用於晶粒陣列之習知半導體電路形成於半導體晶圓之 主動側(前側)。通常藉由背部硏磨薄化,且晶粒附接膜 安裝於薄化晶圓之背側。接著,晶粒藉由沿陣列中之晶粒 -16- 201119007 間之切割道切割(鋸割)單一化。 使用諸如拾取及安置工具,將單一化的晶粒堆疊於錯 位配置中。於在此顯示之例子中,將構成第一層420之第 一錯位晶粒堆疊(於此例子中爲四個)安裝於基板477之 堆疊安裝表面。第一層定位成最下方晶粒441之晶粒附接 側璧對齊(鄰接或局部重疊於)基板上第一接合墊行中的 接合墊472。此後,該總成塗以介電塗層544。介電塗層之 材料可爲多種材料的任一種,並可使用適於特定材料之多 種技術之任一種形成。適當的材料包含有機聚合物,且特 別適當之材料包含聚對二甲苯,其藉由蒸汽形式之先驅分 子之原位聚合物化形成。塗層覆蓋在塗佈期間暴露於材料 之所有表面,包含待形成電連接之區域。因此,開口例如 藉由選擇性雷射磨滅形成於選擇區域上方。例如,開口 545透過塗層形成以露出基板上第一行之互連晶粒墊(例 如548 )及接合墊(例如472 )。完成之架構顯示於第5A圖 中,並局部放大於第5B,5C圖。 此後,藉由形成與互連晶粒墊以及與接合墊472接觸 之引線404,形成於第一層420中晶粒之互連以及第一層與 基板之連接。於第6A圖中顯示並於第6B,6C圖中局部放大 顯示完成之建構。介電塗層用來將可藉導電引線接觸,惟 不欲電接觸之特點絕緣,此等特點像是邊緣’晶粒墊沿其 安置,以及相鄰晶粒緣和側壁。如以上所述,導電材料包 含可以流動形式沉積且此後硬化或容許硬化以形成導體之 材料。導電材料可爲可固化材料,且可沉積成未固化或局 -17- 201119007 部固化狀態;且該材料可於沉積後之中間階段局部或額外 固化,並可在沉積完成時完全固化。適當的互連材料包含 充塡粒子形式之導電材料之聚合物,就像例如金屬充塡聚 合物,其例如包含金屬充塡環氧樹脂、金屬充塡熱固化聚 合物、金屬充塡熱塑聚合物以及導電油墨。 互接材料可藉由適於特定材料之任何技術沉積。於某 些實施例中,材料可使用噴嘴或針調配或噴灑成霧,或網 版印刷或噴墨印刷;材料可透過噴射或噴嘴連續調配或脈 動調配例如成滴狀。在調配後,固化材料以完成互連。 此後,將構成第二層422之第二錯位晶粒堆疊(於本 例子中爲四個)安裝於第一層420之上表面。於此例子中 ,第二層定位成最下方晶粒445之晶粒附接側壁懸於第一 層上,且相對於基板上第二接合墊行中之接合墊474垂直 對齊。此後,所形成之總成塗以第二介電塗層644。第二 介電塗層之材料可爲多種材料之任一種,且可使用適於特 定材料之多種技術之任一種形成。第二塗層材料可與第一 塗層材料相同或不同。適當材料包含有機聚合物,且特別 是適當材料包含聚對二甲苯,其藉由蒸汽形式之先驅分子 之原位聚合物化形成。塗層覆蓋在塗佈期間暴露於材料之 所有表面,包含待形成電連接之區域。因此,開口例如藉 由選擇性雷射磨滅形成於選擇區域上方。例如,開口 645 透過塗層形成以露出基板上第一行之互連晶粒墊(例如 648 )及接合墊(例如474 )。完成之架構顯示於第7A圖中 ’並局部放大於第7B,7C圖。 -18- 201119007 此後,導電材料之柱502形成與基板上第二行中之接 合墊474接觸。完成之架構顯示於第8A圖中,並局部放大 於第8B,8C圖。如以上所述,導電材料包含可以可流動方 式沉積,且此後硬化或容許硬化以形成導體之材料。導電 材料可爲可固化材料,且可沉積成未固化或局部固化狀態 ;且該材料可於沉積後之中間階段局部或額外固化,並可 在沉積完成時完全固化。適當的導電材料包含充塡粒子形 式之導電材料之聚合物,就像例如金屬充塡聚合物,其例 如包含金屬充塡環氧樹脂、金屬充塡熱固化聚合物、金屬 充塡熱塑聚合物以及導電油墨。在調配時及最後固化以前 ,選擇具有適於維持柱高度及一般形狀之適當材料。於特 定實施例中,柱具有大致錐形,範圍約在190-3 ΙΟμιη間之 高度,且基底半徑範圍例如約在160-1 80 μιη間。依材料之 性質而定,可製成具有較大的高度對半徑比例。在沉積及 固化程序期間可形成如第8Β圖中512所示,圍繞基底之環 氧樹脂“印流”;惟於某些實施例中,這可能不是理想的特 點。 用於導電柱之適當材料之特定例子包含OrmetCircuits 公司以“800,700, 500,400,200系列油墨”銷售之導電糊。 此等材料包含5-15 wt%之環氧樹脂混合物以及高達5 wt% 之丁基乙甘醇;其餘包含各種Cu,Bi,Sn及Ag粒子之比率 〇 用於導電柱之適當材料之其他特定例子包含Lord公司 以諸如“Thermoset MD-141”“晶粒附接黏著劑”銷售之導電
S -19 - 201119007 糊。此等材料包含約10 Wt%之酚醛清漆樹脂、約5 wt %之 乙醇乙醚、約5 wt%之環氧樹脂以及約80 wt%之銀。 用於柱之互接材料可藉由適於特定材料及柱形狀之任 何技術沉積。於某些實_例中,材料可使用噴嘴或針調配 或噴灑成霧,或網版印刷或噴墨印刷:材料可透過噴射或 噴嘴連續調配或脈動調配例如成滴狀。在調配後,固化柱 材料以完成柱之機械完整性。 此後,藉由形成與互連晶粒墊以及與柱5 02接觸之引 線5 04,形成於第二層422中晶粒之互連以及第二層與基板 之連接(藉柱502) »於第9A圖中顯示並於第9B, 9C圖中 局部放大顯示完成之建構。介電塗層用來將可藉導電引線 接觸,惟不欲電接觸之特點絕緣,此等特點像是邊緣,晶 粒墊沿其安置,以及相鄰晶粒緣和側壁。如以上所述,導 電材料包含可以流動形式沉積且此後硬化或容許硬化以形 成導體之材料。導電材料可爲可固化材料,且可沉積成未 固化或局部固化狀態;且該材料可於沉積後之中間階段局 部或額外固化,並可在沉積完成時完全固化。適當的互連 材料包含充塡粒子形式之導電材料之聚合物,就像例如金 屬充塡聚合物,其例如包含金屬充塡環氧樹脂、金屬充塡 熱固化聚合物、金屬充塡熱塑聚合物以及導電油墨。在調 配之後,最後固化以前,選擇具有適於維持其跨晶粒445 之側壁與柱梢間之間隙之形狀之適當流變性質的適當材料 〇 互接材料可藉由適於特定材料之任何技術沉積。於某 -20- 201119007 些實施例中,材料可使用噴嘴或針調配或 版印刷或噴墨印刷;材料可透過噴射或噴 動調配例如成滴狀。 第10A及10B圖係顯示於第—層420中 互連及第一層420對基板上接合墊472之驾 分視圖。 第11A及11B圖係顯示於第二層422中 互連及第二層422對基板上柱502之連接;^ 部分視圖。 第12A、12B、12C圖係顯示於第二層 對晶粒互連及第一層422對基板上接合墊 導電引線5〇4之形成步驟之部分視圖。 其他實施例在本發明之範圍內。 例如,圖式顯示總成,其中,成層晶 例子中,上錯位晶粒堆疊)隆起於支撐上 用來電連接隆起之錯位晶粒堆疊於支撐上 考慮其他實施例中,佈設柱以用來電連接 粒堆疊(錯位或非錯位)於支撐上之接合 式顯示總成,其中,下錯位晶粒堆疊位於 。特別是,於圖示之例子中,下錯位晶粒 ,且上堆疊安裝於下堆疊,俾上堆疊之隆 度強施於基板表面(或下堆疊之高度)上 他實施例中,上堆疊可安裝在異於下堆疊 ,就像例如下晶粒或下非錯位晶粒堆疊或 噴灑成霧,或網 嘴連續調配或脈 進行晶粒對晶粒 I電引線404之部 進行晶粒對晶粒 =導電引線5 04之 f 422中進行晶粒 474上之柱502之 粒堆疊(於此等 方;且佈設柱以 之接合墊》於所 隆起之晶粒或晶 墊。且例如,圖 上堆疊與支撐間 堆疊安裝於支撐 起藉下堆疊之高 方。於所考慮其 之某些特點上方 封裝上方》 -21 - 201119007 例如,圖示之鋸齒狀成層錯位晶粒堆疊總成亦具有兩 層(下層及上層),且各層如圖示具有四個晶粒。考慮兩 層以上之總成,並考慮具有其他數目之晶粒之層。例如, 一或更多的額外層可被堆疊在第二層上。例如,一或更多 層可具有四個以上或以下之晶粒,且於某些實施例中,一 或更多層可例如具有八個晶粒。 如圖所示,上及下層中之晶粒亦具有相同長度。此種 情況可例如適用於所有晶粒具有相同類型或相同功能情況 下。成層堆疊之每一者例如包含同型之記憶晶粒。考慮其 他晶粒型。例如,具有不同功能之晶粒可包含於一層內; 或者,例如,一層中之晶粒可具有相同功能,而其他層中 之晶粒則具有一或更多不同功能。結果,於所考慮之某些 實施例中,晶粒可大小不同;或一層中之晶粒可大小相同 ,而其他層中之晶粒則具有不同尺寸。 於如圖示例子中,上層中之最下方晶粒之互接緣亦向 外延伸超過下特點之下緣(亦即於圖示之例子中,超過下 層中最上方晶粒之下晶粒緣)。於另一考慮之例子中,上 堆疊中之互連緣可垂直對齊或可從下特點之下緣向內。 於例如圖示例子中,介電塗層亦自堆疊中所有晶粒上 之互連墊移除。這容許所有墊接觸後續形成之引線。可能 較佳係形成僅與墊之選擇者連接之電連接。如於以上參考 且倂提於此供參考之美國申請案12/1 24,077中所圖示及討 論,開口可形成於任何晶粒中所選墊的上方,或對應堆疊 中連續晶粒上之墊選擇,留下爲介電塗層所覆蓋且對電連 -22- 201119007 接無用之墊。且,例如,塗層如說明形成於多數相中,各 相出現在層之每一者建構後。於某些所考慮之實施例中, 塗層應用於形成兩個(或更多)以後之單一相中。在上層 位於下層上方俾下層中之互連晶粒墊可便於用來移除(例 如藉由雷射磨滅)情況下,這可能特別理想》 於例如圖示例子中,說明在二調配操作中進行柱之形 成,及連接隆起(上)晶粒或晶粒堆疊於柱之引線之形成 。於某些實施例中,可於連續操作中,藉由調配及調配工 具之適當控制,形成各柱及對應引線。 【圖式簡單說明】 第1 A及1 B圖係以俯視圖(第1 A圖)及剖視圖(第1 B 圖)顯示安裝於支撐上之錯位晶粒堆疊之圖式。 第1 C圖係如第1 B圖剖視顯示安裝於支撐上之錯位晶片 堆疊之圖式,其中晶粒以晶粒對晶粒方式電連接,且晶粒 堆叠電連接於支撐。 第2 A及2B圖係剖視顯示以鋸齒組態相互安裝之二堆疊 晶粒單元之圖式。 第3A圖係顯示可固化互連材料之自由立起液滴之圖式 ,第3 B圖係顯示於晶粒與支撐間形成電連接之步驟之圖式 〇 第4 A、4B及4C圖係剖視顯示以鋸齒組態成層錯位堆 疊之晶粒總成,其安裝及電連接於支撐。
第5A、5B及5C圖:第6A、6B及6C圖:第7A、7B及7C -23- 201119007 圖;第8A、8B及8C圖;以及第9A、9B及9C圖係如第4A' 4B及4C圖剖視顯示以鋸齒組態建構成層錯位堆疊之晶粒總 成之步驟的圖式,第4B,5B, 6B,7B,8B及9B圖分別係如 於4A,5A,6A,7A, 8A及9A圖中B所不部分剖視之圖式’且 第 4C,5C, 6C, 7C, 8C及 9C圖分別係如於 4A, 5A,6A,7A, 8 A及9 A圖中C所示部分剖視之圖式。 第1 OA圖係安裝於支撐上之成層錯位堆疊之晶粒總成 一部分之正視圖,其顯示下層對支撐之電連接。 第10B圖係安裝於支撐上之成層錯位堆疊之晶粒總成 一部分之俯視圖,其顯示下層對支撐之電連接》 第11A圖係安裝於支撐上之成層錯位堆疊之晶粒總成 一部分之正視圖,其顯示上層對支撐之電連接。 第1 1 B圖係安裝於支撐上之成層錯位堆疊之晶粒總成 一部分之俯視圖,其顯示上層對支撐之電連接。 第1 2 A圖係安裝於支撐上之成層錯位堆疊之晶粒總成 一部分之正視圖,其顯示形成上層對支撐之電連接之步驟 〇 第11B圖係如第12A圖安裝於支撐上之成層錯位堆疊之 晶粒總成一部分之俯視圖,其顯示上層對支撐之電連接。 第12C圖係如第12A圖安裝於支撐上之成層錯位堆疊之 晶粒總成一部分之俯視圖,其顯示形成上層對支撐之電連 接之步驟。 【主要元件符號說明】 • 24 - 201119007 1 〇 :錯位堆疊晶粒 1 4 1 :最下方晶粒 143, 144, 146 :晶粒 142, 173 :行 145 :開口 147:最上方晶粒 148 :互連墊 1 4 9 :目ij晶粒緣 1 7, 2 1 7, 320, 447 :支撐 1 7 1 :晶粒安裝表面 172 :接合位置 174 :引線 210:第一模組單元(第一層) 2 1 2 :第二模組單元(第二層) 214,224:互連 220 :第二層 244 :導電層 272 :接合墊 3 04 :液滴 3 17 :基板 3 2 8 :接觸 34 1 , 3 42, 3 43, 344 :晶粒 3 48 :周緣墊 3 72 :接合墊
S -25- 201119007 404 :弓丨線 420 :第一層 4 2 8 :堆疊晶粒總成 431,432,433, 434,435, 436, 437, 438 :晶粒附接膜 44 1 , 442, 443, 444 :晶粒 445, 446, 447, 448 :晶粒 472,474:接合墊 476 :焊墊 477 :基板 5 02 :柱 504 :引線 544, 644:介電塗層 545, 645 :開口 5 48,648 :互連晶粒墊 -26-
Claims (1)
- 201119007 七、申請專利範圍: 1. 一種半導體總成,其包括安裝並隆起於支撐上方之 晶粒,該晶粒於其前側具有互連墊,該支撐於其安裝側接 合墊上具有一第一導電材料柱,其中,該隆起晶粒藉使該 晶粒上該互連墊接觸該接合墊上之該柱之第二導電材料的 引線電連接於該支撐。 2. 如申請專利範圍第1項之總成,其中,該隆起晶粒 於其前側具有複數個互連墊,且該支撐於其安裝側之該等 複數個接合墊之每一者上具有第一導電材料柱,其中,該 隆起晶粒藉使該等複數個互連墊之至少二者之每一者接觸 至少二對應接合墊之每一者上之該柱之第二導電材料的引 線電連接於該支撐。 3 .如申請專利範圍第1項之總成,其中,該第一導電 材料及該第二導電材料包括相同材料。 4.如申請專利範圍第1項之總成,其中,該第一導電 材料及該第二導電材料之至少一者包括能以可流動形式沉 積及之後硬化或容許硬化以形成導體之材料。 5 ·如申請專利範圍第1項之總成,其中,該第一導電 材料及該第二導電材料之至少一者包括可固化材料。 6. 如申請專利範圍第1項之總成,其中’該第〜導電 材料及該第二導電材料之至少一者包括於聚合基質導電材 料中之粒子形式之導電材料。 7. 如申請專利範圍第1項之總成,其中,該第〜導電 材料及該第二導電材料之至少一者包括充塡金屬之聚合物 -27- 201119007 8. 如申請專利範圍第7項之總成,其中,該充塡金屬 之聚合物包括充塡金屬之環氧樹脂。 9. 如申請專利範圍第7項之總成,其中,該充塡金屬 之聚合物包括充塡金屬之熱固聚合物。 1〇_如申請專利範圍第7項之總成,其中,該充塡金屬 之聚合物包括充塡金屬之熱塑聚合物。 11.如申請專利範圍第1項之總成,其中,該第一導電 材料及該第二導電材料之至少一者包括於載體中之粒子形 式之導電材料。 1 2 .如申請專利範圍第1 1項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括導電墨。 13. —種半導體總成,其包括安裝於支撐上方之晶粒 堆疊之複數個晶粒,至少第一該晶粒隆起於該支撐上,該 第一晶粒於其前側具有互連墊,該支撐於其安裝側接合墊 上具有一第一導電材料柱,其中,該第一晶粒藉使該晶粒 上該互連墊接觸該接合墊上之該柱之第二導電材料之引線 電連接於該支撐。 14. 如申請專利範圍第13項之總成,其中,該第一導 電材料及該第二導電材料包括相同材料。 1 5 .如申請專利範圍第1 3項之總成,其中,至少該第 二晶粒藉使該第一晶粒上之互連墊接觸該第二晶粒上之互 連墊之第三導電材料之引線電連接於該第一晶粒。 16.如申請專利範圍第15項之總成,其中,該第三導 -28 - 201119007 電材料及該第二導電材料包括相同材料。 17·如申請專利範圍第13項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括能以可流動形式 彷:胃及之後硬化或容許硬化以形成導體之材料》 1 8.如申請專利範圍第1 3項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括可固化材料。 1 9.如申請專利範圍第1 3項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括於聚合基質導電 材料中之粒子形式之導電材料。 20.如申請專利範圍第1 3項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括充塡金屬之聚合 物。 2 1.如申請專利範圍第20項之總成,其中,該充塡金 屬之聚合物包括充塡金屬之環氧樹脂。 2 2.如申請專利範圍第20項之總成,其中,該充塡金 屬之聚合物包括充塡金屬之熱固聚合物。 23.如申請專利範圍第20項之總成,其中,該充塡金 屬之聚合物包括充塡金屬之熱塑聚合物。 24·如申請專利範圍第1 3項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括於載體中之粒子 形式之導電材料。 25.如申請專利範圍第24項之總成,其中,該導電材 料包括導電墨。 2 6. —種半導體總成,其包括安裝於並隆起於支撐上 -29- 201119007 方之上晶粒堆疊中之複數個晶粒,該上堆疊中之至少第一 晶粒於其前側具有互連墊,該支撐於其安裝側接合墊上具 有一第一導電材料柱’其中,該上堆疊中之該第一晶粒藉 使該上堆疊中之該第一晶粒上之該互連墊接觸該接合墊上 之該柱的第二導電材料之引線電連接於該支撐。 27·如申請專利範圍第26項之半導體總成,進一步包 括位於該支撐與該上晶粒堆疊間之下晶粒。 28·如申請專利範圍第26項之半導體總成,進一步包 括位於該支撐與該上晶粒堆疊間之下晶粒堆疊。 2 9.如申請專利範圍第26項之半導體總成,進一步包 括位於該支撐與該上晶粒堆疊間之半導體封裝。 3 0 ·如申請專利範圍第2 8項之半導體總成,其中,該 下晶粒堆疊包括成層錯位堆疊的晶粒總成,且其中,下層 中之晶粒以晶粒對晶粒方式電互連,且該下層藉使晶粒上 互連墊及該支撐上之一組接合墊接觸之導電材料之引線電 連接於該支撐。 3 1.如申請專利範圍第26項之半導體總成,其中,該 上晶粒堆疊包括該成層錯位堆疊的晶粒總成,其中,該層 之互連緣面對第一方向,且該互連晶粒墊對準該柱。 3 2.—種晶粒堆疊總成,包括以鋸齒組態堆疊的第一 及第二成層錯位晶粒堆疊。 3 3 .如申請專利範圍第3 2項之晶粒堆疊總成’其中, 該第一層之互連緣面對第—方向,且該第二層之互連緣面 對異於第一方向之第二方向。 -30- 201119007 34.如申請專利範圍第32項之晶粒堆疊總成,其中, 該第一層互連緣方向與該第二層互連緣方向相對。 3 5 ·如申請專利範圍第3 2項之晶粒堆疊總成,其中, 該第一層互連緣方向與該第二層互連緣方向正交。 3 6 .如申請專利範圍第3 2項之晶粒堆疊總成,其中, 該第一層晶粒以晶粒對晶粒方式電互連,且該第一層中的 晶粒藉使該晶粒上該互連墊與該支撐上第一組接合墊接觸 之導電材料之引線電連接於支撐,且其中,該第二層中的 晶粒以晶粒對晶粒方式電互連,且該第一層藉使該晶粒上 該互連墊與形成於該支撐上第二組接合墊上之導電材料柱 接觸之導電材料之引線電連接於該支撐。 37. —種將安裝並隆起於支撐上方之晶粒電連接於支 撐中之電路之方法,包括以下步驟: 於支撐之安裝側之一組接合墊上形成多數導電材料柱 :以及 形成導電材料之引線,各該引線與隆起晶粒上之互連 晶粒墊及柱接觸。 38. 如申請專利範圍第37項之方法,其中,形成引線 包括跨該柱與該互連晶粒墊間之間隙形成引線。 39. 如申請專利範圍第37項之方法,其中,形成柱包 括沉積可固化導電柱材料於接合墊上及固化沉積之柱材料 〇 40. 如申請專利範圍第37項之方法,其中,形成引線 包括沉積與柱接觸之可固化導電引線材料以及固化該沉積 -31 - 201119007 之引線材料。 41.—種用以將安裝並隆起於支撐上方之晶粒堆疊中 之晶粒電連接於支撐中之電路之方法,包括以下步驟: 於支撐之安裝側之一組接合墊上形成多數導電材料柱 ;以及 形成導電材料之引線,各該引線與隆起晶粒堆之至少 一晶粒上之互連晶粒墊及該柱接觸。 42 ·—種製造以鋸齒組態成層錯位堆疊之晶粒總成之 方法,包括以下步驟: 安裝第一層於支撐上,配置成使得第一層之互連緣面 對第一方向,使得第一層中至少最下方晶粒上之互連墊與 該支撐上之第一組接合墊對齊; 晶粒對晶粒電互連該第一層中之晶粒,並藉由形成第 一層導電材料引線,電連接該層於該支撐,該第一層導電 材料引線之每一者與該晶粒上之至少一互連墊以及該等第 -組接合墊之一者接觸; 堆疊或安裝第二層於該第一層上方,配置成第二層之 互連緣面對第二方向; 形成導電材料柱於該支撐上之第二組接合墊上;以& 形成導電材料之第二層引線,各該引線與該第二層中 至少一晶粒上之互連晶粒墊及該柱接觸。 43.如申請專利範圍第42項之方法,其中,形成第〜^ 層引線包括沉積可固化導電引線材料,該導電引線材 至少一下層晶粒上之晶粒墊接觸,及固化沉積之引線材_ -32- 201119007 44·如申請專利範圍第42項之方法,其中,形成第二 層引線包括跨該柱與該互連晶粒墊間之間隙形成引線。 45·如申請專利範圍第42項之方法,其中,形成該等 柱包括沉積可固化導電柱材料於接合墊上及固化沉積之柱 材料。 46.如申請專利範圍第42項之方法,其中,形成第二 層引線包括沉積可固化導電引線材料,該導電引線材料與 至少一上層晶粒上之晶粒墊及柱接觸,及固化沉積之引線 材料。 4 7.如申請專利範圍第42項之方法,進一步包括於堆 疊或安裝第一層之後及形成第一層引線之前,以保形介電 塗層塗布該總成,並形成多數開口於待與該等第一層引線 接觸之至少經選擇之晶粒墊及接合墊。 48.如申請專利範圍第42項之方法,進一步包括於堆 疊或安裝第二層之後及形成該等柱之前,以保形介電塗層 塗布該總成,並形成多數開口於待與該等柱接觸之至少經 選擇之第二層晶粒墊及接合墊。 3 -33-
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- 2010-06-23 CN CN201080035256.6A patent/CN102473697B/zh not_active Expired - Fee Related
- 2010-06-23 WO PCT/US2010/039639 patent/WO2010151578A2/en active Application Filing
- 2010-06-23 JP JP2012517680A patent/JP5963671B2/ja not_active Expired - Fee Related
- 2010-06-23 TW TW099120462A patent/TWI570879B/zh not_active IP Right Cessation
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US9230942B2 (en) | 2013-02-26 | 2016-01-05 | Sandisk Information Technology (Shanghai) Co., Ltd. | Semiconductor device including alternating stepped semiconductor die stacks |
Also Published As
Publication number | Publication date |
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CN102473697B (zh) | 2016-08-10 |
WO2010151578A3 (en) | 2011-03-31 |
JP2012531750A (ja) | 2012-12-10 |
US20100327461A1 (en) | 2010-12-30 |
KR20120055541A (ko) | 2012-05-31 |
CN102473697A (zh) | 2012-05-23 |
US8680687B2 (en) | 2014-03-25 |
WO2010151578A2 (en) | 2010-12-29 |
JP5963671B2 (ja) | 2016-08-03 |
TWI570879B (zh) | 2017-02-11 |
KR101715426B1 (ko) | 2017-03-10 |
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