TWI611485B - 覆晶底部填充 - Google Patents

覆晶底部填充 Download PDF

Info

Publication number
TWI611485B
TWI611485B TW099114942A TW99114942A TWI611485B TW I611485 B TWI611485 B TW I611485B TW 099114942 A TW099114942 A TW 099114942A TW 99114942 A TW99114942 A TW 99114942A TW I611485 B TWI611485 B TW I611485B
Authority
TW
Taiwan
Prior art keywords
die
substrate
film
interconnection
dielectric
Prior art date
Application number
TW099114942A
Other languages
English (en)
Other versions
TW201115662A (en
Inventor
馬柯 卡尼佐
Marcos Karnezos
Original Assignee
英維瑟斯公司
Invensas Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英維瑟斯公司, Invensas Corporation filed Critical 英維瑟斯公司
Publication of TW201115662A publication Critical patent/TW201115662A/zh
Application granted granted Critical
Publication of TWI611485B publication Critical patent/TWI611485B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

一種用於覆晶互連之方法包括施加一介電性薄膜於晶粒之作用側上，或基板之晶粒安裝側上，或晶粒與基板兩者上；接著相關於基板而將晶粒定向與對準，且將晶粒移向基板，使得互連接觸形成；接著處理該組件(例如藉由加熱或藉由熱壓)，以完成電氣連接並使薄膜軟化及黏接。再者，一種用於覆晶組件之方法包括完成一晶粒上之覆晶互連和一基板上之接合墊塊的電氣連接，及隨後將該組件曝露於一化學汽相沈積(CVD)製程，以利用一介電材料填充晶粒與基板之間之頂上空間。再者，一種覆晶組件係藉由該方法製成。再者，一種晶粒或一種基板係藉由施加一介電性薄膜於其一表面上而製備用於覆晶互連。

Description

覆晶底部填充
交互參考相關申請案
本申請案主張由M.Karnezos在2009年5月14日申請之美國臨時申請案第61/178,443號及2010年5月7日申請之美國申請案第12/776,262號二案同為名稱「覆晶底部填充」之優先權，該等申請案係以引用的方式併入本文中。
本發明關於覆晶封裝。
一典型半導體晶粒具有一供積體電路形成於其中之前(作用)側、一背側、及側壁。側壁係在前緣部連接於前側及在後緣部連接於背側。半導體晶粒典型上設有位於前側之互連墊塊(晶粒墊塊)，用於晶粒上之電路與配置有晶粒之裝置中之其他電路的電氣互連。有些晶粒在前側上沿著一或多個晶粒邊緣設有晶粒墊塊，且這些可以視為周邊墊塊晶粒。其他晶粒則在前側且靠近晶粒中央處具有配置成一或二列之墊塊，且這些可以視為中央墊塊晶粒。有些晶粒具有配置成一區域陣列之墊塊。
晶粒可以「重路由」，以提供一適當之互連墊塊配置方式於一或多個晶粒邊緣或附近。
半導體晶粒可以藉由多種方式之任一者而電氣連接於一封裝中之其他電路，例如在一封裝基板上或在一引線框架上者。此z形互連例如可以藉由線接合、或藉由覆晶互連、或藉由捲帶互連構成。封裝基板或引線框架提供用於封裝對下層電路(第二層互連)之電氣連接，例如一將封裝裝設於其中以供使用之裝置中之印刷電路板上之電路。
在一覆晶封裝中，晶粒係定向成以作用側面向基板。晶粒中之電路與基板中之電路的互連係藉由附接於晶粒上之一互連墊塊陣列、及接合於基板上之一相對應(互補型)互連墊塊陣列的導電性圓珠或凸塊而達成。典型上凸塊包括例如焊珠，或例如金凸塊。封裝係藉由將晶粒定向成以作用側面向基板之晶粒接附表面、及將晶粒對準基板(在X-Y平面中)，使得晶粒上之圓珠或凸塊將基板上之相對應接合墊塊定位，將晶粒移向基板(在Z方向中)直到圓珠或黏接劑接觸到接合墊塊，及接著藉由迴焊而完成電氣連接，或者藉由施加力與熱以利於金凸塊與接合墊塊之間產生一固態結合。
在生成之電氣連接之晶粒-基板組件中，圓珠或凸塊具有一有限高度，且晶粒墊塊及接合墊塊分隔(在Z方向中)一相當於互連高度之距離。據此，在電氣連接之組件中，晶粒與基板之面對面表面之間有一有限之「頂上空間」。
頂上空間係經一介電材料填入，以減低晶粒與焊珠上由熱循環所造成之應力或由彎曲所造成之機械性應力，並使晶粒與基板表面避免潮濕及其他可能導致腐蝕與造成失效之化學物質。
此空間一般是以一介電性「底部填充」材料填入，此為二種方式之其中一者。
在一底部填充方式中，晶粒-基板之電氣連接大致上係依上述達成。接著完成電氣連接，一熱可固化液體底部填充前驅物材料沿著一或多個晶粒邊緣施加，且容許在晶粒與基板之間流動(原則上是利用毛細作用)。隨後底部填充材料即固化。
業界冀求增加晶粒上之互連墊塊數量，並減少晶粒之涵蓋範圍。生成之封裝有較高之互連密度，且隨之而來的減小(較細微)墊塊間距。具有較細微墊塊間距之覆晶電氣連接則需要較小圓珠或凸塊，且生成之頂上空間也對應地變小。對於使用一般毛細作用流動式底部填充之努力皆因前驅物材料未能進入頂上空間、或是無法完全進入頂上空間，導致在晶粒與基板之間產生氣隙而受挫。
在另一方式中，一熱可固化可流動性(典型上為液體)底部填充前驅物材料係在基板與晶粒結合前先在基板上方施配一選擇之厚度。接著藉由將晶粒定向與對準於基板，並將晶粒與基板壓合，使晶粒與基板結合。當凸塊或圓珠趨近於接合墊塊時，其將液體之底部填充前驅物移位，使得圓珠或凸塊與接合墊塊之間完成接觸，且晶粒之表面接觸於底部填充之表面。隨後，該組件加熱一段時間，以令焊料圓珠或凸塊迴焊(或施加熱與壓力以形成固態連接)及令底部填充材料固化。
在此移位方式中，成功且穩定電氣連接及確實底部填充固化所需之溫度/時間構型必須微調及謹慎控制。
適用於一般底部填充之材料為易操作性介電質，以提供所想要的良好流動性與黏性特徵，且可以極為價廉。
在多項實施例中，本發明之特徵在於覆晶晶粒組件係藉由施加一介電性薄膜於晶粒之作用側上，或基板之晶粒安裝側上，或晶粒與基板兩者上；接著相關於基板而將晶粒定向與對準，且將晶粒移向基板，使得互連接觸形成；接著處理該組件(例如藉由加熱或藉由熱壓)，以完成電氣連接並使薄膜軟化及黏接，及填入空間內之任一氣隙而形成。
在其他多項實施例中，本發明之特徵在於覆晶晶粒組件係藉由相關於基板而將晶粒定向與對準，且將晶粒移向基板，使得互連接觸形成；接著處理該組件(例如藉由加熱或藉由熱壓)，以完成電氣連接；及隨後使用一化學汽相沈積(CVD)製程，以利用一介電材料填充晶粒與基板之間之頂上空間。
在一大致態樣中，本發明之特徵在一種用於覆晶互連之方法，其藉由施加一介電性薄膜於一晶粒之作用側上，該薄膜具有複數個開孔，其曝露該晶粒上之電氣互連；相關於基板而將晶粒定向與對準，且將晶粒移向基板，使得互連接觸形成；接著處理該組件，以完成電氣連接並使薄膜軟化及黏接。
在另一大致態樣中，本發明之特徵在一種用於覆晶互連之方法，其藉由施加一介電性薄膜於一基板之安裝側上，該薄膜具有複數個開孔，其曝露該基板上之互連位置；相關於基板而將晶粒定向與對準，且將晶粒移向基板，使得互連接觸形成；接著處理該組件，以完成電氣連接並使薄膜軟化及黏接。
在又一大致態樣中，本發明之特徵在一種用於覆晶互連之方法，其藉由施加一第一介電性薄膜於一基板之安裝側上，該第一薄膜具有複數個開孔，其曝露該基板上之互連位置；在一晶粒之作用側上形成一第二介電性薄膜，該第二薄膜具有複數個開孔，其曝露該晶粒上之電氣互連；相關於基板而將晶粒定向與對準，且將晶粒移向基板，使得互連接觸形成；接著處理該組件，以完成電氣連接並使薄膜軟化及黏接。
該互連可以是或可以包括該晶粒上之互連墊塊，及在一些實施例中，該晶粒上之電氣互連包括安裝於該晶粒上之互連墊塊上的互連凸塊或圓珠或球體。該互連之材料可以是或可以包括例如焊珠，或例如「凸塊」(例如，金或金合金凸塊)，或例如一可熔材料之球體(例如，一焊膏)，或例如一可固化導電性材料之球體。當該互連例如包括焊料時，則處理該組件以完成電氣連接之步驟包括一加熱以迴焊之程序。當該互連例如包括金凸塊時，處理該組件以完成電氣連接之步驟包括一加熱且施壓之程序，以在凸塊與基板上之互連位置的界面處形成一固態結合。
當該互連材料係一可固化之材料時，其可在沈積後、或局部或全部固化後呈導電性。一適當之互連材料可以是一導電性聚合物。適當之導電性聚合物包括利用粒子形式導電性材料填充之聚合物，例如，金屬填充之聚合物(例如包括金屬填充之環氧樹脂、金屬填充之熱固性聚合物、金屬填充之熱塑性聚合物、或一導電性墨水)。導電性粒子可以有廣範圍之尺寸及形狀，其例如可為奈米粒子或較大粒子。
用於導電性互連之適當可固化導電性材料係以一可流動形式施加，未固化或部分固化，及隨後固化或容許硬化。互連過程可包括在互連墊塊上形成未固化材料點或球，及處理該組件以完成電氣連接之步驟包括一將材料固化(或容許材料固化或硬化)之程序，以令晶粒墊塊與基板上之互連位置的電氣接觸穩固。對於一些導電性墨水而言，例如，固化使施加之墨水中之粒子燒結，及處理該組件以完成電氣連接之步驟可包括施加及一後續之燒結程序。
當使用一可固化之互連材料時，可以利用一施加工具施加，例如一注射器或一噴嘴或一針；且其可從該工具以一連續流方式擠出；或者，其可逐滴離開該工具。選項性地，複數個沈積工具可以設置為一成組式或陣列式工具，及經操作以在單一次送料時沈積一或多條材料之跡線。另者，可固化之互連材料可以藉由針腳轉移或墊塊轉移而沈積，即其使用一針腳或墊塊或成組式或陣列式針腳或墊塊。一可固化材料之塗佈可以是自動化；亦即，工具或成組式或陣列式工具之移動、及材料之沈積可以由操作人員適當編程而做自動機械式控制。及，另者，一可固化之互連材料可以藉由印刷而施加，例如使用一列印頭(其可具有一適當之噴嘴陣列)，或例如藉由空氣噴霧器，或例如藉由網印或使用一遮罩。多種可固化之互連材料、及用於沈積可固化之電氣互連的方法係揭述於Caskey等人在2008年5月20日申請之美國專利申請案第12/124,097號「Electrical interconnect formed by pulsed dispense」中之形成互連跡線的文章中，及Leal在2009年12月9日申請之美國專利申請案第12/634,598號「semiconductor die interconnect formed by aerosol application of electrically conductive material」中之形成互連端點於晶粒墊塊上的文章中。這些申請案是以引用方式併入本文。
當晶粒上之電氣互連包括安裝於晶粒上之互連墊塊上的互連凸塊或圓珠或球體時，互連凸塊或圓珠或球體可以在施加介電性薄膜至晶粒之作用側上之前或之後，安裝於或沈積於或施加於晶粒上之互連墊塊。當互連是在施加介電性薄膜至晶粒之後才安裝或施加或沈積時，則在安裝或施加或沈積於墊塊上之前必須在介電性薄膜中開孔(例如使用雷射剝蝕)以曝露出晶粒墊塊。
在另一大致態樣中，本發明之特徵在一種用於覆晶互連之方法，其藉由提供一晶片，晶片具有互連凸塊或球體或圓珠且安裝於其一作用側上之互連墊塊上，及提供一基板，其具有互連位置設於其一晶粒安裝表面上之接合墊塊上；相關於該基板而將晶粒定向與對準，且將該晶粒移向該基板，使得互連圓珠或凸塊或球體接觸於互連位置；處理該生成之組件(例如藉由加熱或藉由熱壓)，以完成電氣連接；及隨後使用一化學汽相沈積製程，以一介電材料填充該晶粒與該基板之間之空隙。特別適用之介電材料包括對二甲苯或其衍生物之聚合物，例如一聚二甲苯聚合物(例如一聚對二甲苯)。一聚對二甲苯(例如聚對二甲苯A、或聚對二甲苯C、或聚對二甲苯N)特別適合；一聚對二甲苯填充物之形成可以在習知聚對二甲苯處理設備中實施。
在再一大致態樣中，本發明之特徵在一種製備以用於覆晶互連之晶粒，其具有一形成於其一作用側上之介電性薄膜，該薄膜具有複數個開孔，其曝露該晶粒上之電氣互連。
在另一大致態樣中，本發明之特徵在一種製備以用於覆晶互連之基板，其具有一形成於其一晶粒安裝側上之介電性薄膜，該薄膜具有複數個開孔，其曝露該基板上之互連位置。
在另一大致態樣中，本發明之特徵在一種覆晶組件，其包括一晶粒安裝於且電氣連接於一基板，及一介電性薄膜底部填充具有開孔，藉此以達成電氣連接。
晶粒上或基板上之介電性薄膜實質上為不可流動性，且可以是固態。亦即，對比於液體或可流動性材料，薄膜可以抗變形及體積變化。介電性薄膜之厚度(或第一及第二介電性薄膜之組合厚度)足以在達成電氣連接後完全佔滿晶粒與基板之間之頂上空間。
適用於介電性薄膜之材料包括多種有機聚合物，例如熱固性聚合物、熱塑性聚合物、聚醯亞胺、及對二甲苯或其衍生物之聚合物，例如一聚二甲苯聚合物(例如一聚對二甲苯)。一聚對二甲苯(例如聚對二甲苯A、或聚對二甲苯C、或聚對二甲苯N)特別適合，且一聚對二甲苯薄膜之形成可以在習知聚對二甲苯處理設備中實施。薄膜可以由適用於特殊材料之任意技術形成，且在一些實施例中薄膜係藉由化學汽相沈積形成。
本發明現在即藉由參考圖式而進一步詳細說明，圖中揭示本發明之可替代實施例。圖式係示意圖，揭示本發明之特性及其對其他特性與結構之關係，且未依比例繪示。為了方便說明清楚，在揭示本發明實施例之圖式中，和其他圖式中所示之元件相對應之元件即不特別重編號碼，儘管其在所有圖式中皆可輕易辨識。同樣為了方便說明清楚，某些特性並不在圖中揭示，因其對於本發明之瞭解並非必要者。在說明中之一些地方，相對位置之用詞像是「上方」、「下方」、「上部」、「下部」、「頂部」、「底部」及類似者皆可參考於圖式之方位而採用，這些用詞並非用來限制本裝置使用時之方位。
圖1A係大致上在編號10位置以截面圖揭示一晶粒12，其具有一作用(前)側13及一背側11，以及具有側壁15。前側之晶粒緣部係界定於晶粒之側壁15與作用側13的相交處，且背側之晶粒緣部係界定於晶粒之側壁15與背側11的相交處。電氣互連墊塊(晶粒墊塊)14係以一或多列設置靠近於一或多個前側之晶粒緣部處。晶粒墊塊可以構成晶粒之作用側中之電路的一部分、或者可連接於電路。互連球17安裝於晶粒墊塊上。安裝球之一球高度H係取決於球徑，較小球即有較小之球高度。
圖1B係以平面圖揭示圖1A中之一晶粒。在此例子中，晶粒呈正方形，且其在沿著所有晶粒緣部之晶粒邊界處配置多列之互連墊塊14。眾所週知晶粒不會是正方形；亦即，晶粒之寬度應小於長度。同樣可知的是周邊墊塊之晶粒可在僅靠近於一晶粒緣部處、或沿著二相鄰或相對立之晶粒緣部、或沿著三晶粒緣部、或如圖所示沿著所有四晶粒緣部處具有配置成多列之晶粒墊塊。
圖2A係在編號20位置以截面圖揭示一般之支撐件(在本文內稱之為一「基板」)，其具有一連接側21及一反轉側23，以及具有接合墊塊24上之互連位置，該互連位置可供一晶粒在定向相反於基板、且在X-Y平面中正確對準時，基板上之互連位置即與晶粒上之相對應互連(圓珠或凸塊或球體)對準。亦即，基板接合墊塊組態係與特定晶粒之晶粒墊塊組態相匹配，藉此接合；及例如圖2A、2B中所示之基板即匹配於圖1A、1B中所示之晶粒。圖2B係以平面圖揭示圖2A中之基板。支撐件包括至少一層22之介電材料及至少一層由一或多層介電材料支撐之導電材料(例如金屬或金屬化)。接合墊塊24可以構成一圖案化導電層中之電氣跡線的一部分、或連接於跡線，其至少設置於支撐件之連接側。許多類型支撐件之任一者皆可根據本發明而使用。特別是，支撐件可以是一封裝基板、或一印刷電路板(例如一母板或子板、及類似者)。許多基板組態已屬習知。
圖1C係大致上在編號10’位置以截面圖揭示一晶粒12’，其具有一作用(前)側13’及一背側11’，以及具有側壁15’。前側之晶粒緣部係界定於晶粒之側壁15’與作用側13’的相交處，且背側之晶粒緣部係界定於晶粒之側壁15’與背側11’的相交處。在此範例中之電氣互連墊塊(晶粒墊塊)14’係以一區域陣列實質上設置於整個表面上。晶粒墊塊可以構成晶粒之作用側中之電路的一部分、或者可連接於電路。互連球17’安裝於晶粒墊塊上。安裝球之球高度係取決於球徑，較小球即有較小之球高度。
圖1D係以平面圖揭示圖1C中之一晶粒。在此例子中，晶粒呈正方形且如上所述，其在幾乎全部晶粒表面上皆有配置成一區域陣列之互連墊塊14。如上所述，晶粒不會是正方形；亦即，晶粒之寬度應小於長度。同樣可知的是有些晶粒兼具一區域陣列之墊塊及周邊之墊塊。例如一晶粒可在沿著一或多個緣部處具有配置成一或多列之晶粒墊塊，此外也可以在較為中央處具有一區域陣列。許多墊塊可以和許多電氣功能相關聯，且晶粒上之墊塊尺寸及配置方式可因此而相異。
圖2C係在編號20’位置以截面圖揭示一般之支撐件，其具有一連接側21’及一反轉側23’，以及具有接合墊塊24’上之互連位置，該互連位置可供晶粒在定向相反於基板、且在X-Y平面中正確對準時，基板上之互連位置即與晶粒上之相對應互連(圓珠或凸塊或球體)對準。亦即，基板接合墊塊組態係與特定晶粒之晶粒墊塊組態相匹配，藉此接合；及例如圖2C、2D中所示之基板即匹配於圖1C、1D中所示之晶粒。圖2D係以平面圖揭示圖2C中之基板。支撐件包括至少一層22’之介電材料及至少一層由一或多層介電材料支撐之導電材料(例如金屬或金屬化)。接合墊塊24’可以構成一圖案化導電層中之電氣跡線的一部分、或連接於跡線，其至少設置於支撐件之連接側。許多類型支撐件之任一者皆可根據本發明而使用。特別是，支撐件可以是一封裝基板、或一印刷電路板(例如一母板或子板、及類似者)。許多基板組態已屬習知。
可以瞭解的是，將如圖1A、1B或1C、1D中所示之一晶粒以覆晶方式安裝於如圖2A、2B或2C、2D中所示之一支撐件(例如一基板)上即在晶粒之作用側與基板之晶粒安裝側之間產生一頂上空間。除其他外，在頂上空間之厚度將取決於結合(迴焊或固態壓縮)後之圓珠高度，及取決於接觸墊塊是否高過基板之晶粒安裝表面(如圖2A、2C中所示之範例者)，或者其可以透過一焊料遮罩(圖中未示)中之開孔而曝露。
用於形成一底部填充之二替代性習知方式已在前文中說明。在一方式中晶粒係與基板結合，而形成電氣互連；隨後一液體形式之底部填充前驅物材料沿著一或多個晶粒緣部施加。液體之底部填充前驅物材料藉由面對面之晶粒與基板表面之間的毛細管流動而侵入頂上空間；隨後底部填充材料固化(例如利用熱)。在一替代性方式中，一可流動之底部填充前驅物材料係施加於基板表面上；及隨後晶粒即與基板定向及對準，並且被壓入底部填充前驅物材料內。晶粒上之圓珠或凸塊或球體將位於其與接觸墊塊接觸處之底部填充前驅物移位，及最後晶粒表面接觸於底部填充前驅物表面。隨後，組件被處理至一溫度狀況，以完成電氣連接(藉由回流焊接或固態接合)及將底部填充材料固化。
根據本發明之諸實施例，在晶粒結合於基板之前，一固態介電性薄膜形成於晶粒上或基板上(或晶粒與基板兩者上)。薄膜厚度足以佔滿頂上空間，且當組件結合時在互連位置(即薄膜在晶粒上)或在接合位置(即薄膜在基板上)之開孔可供接觸。接著將組件加熱且晶粒與基板被壓合至一所需之程度，以形成電氣連接(迴焊或固態接合)及令薄膜表面黏接於一面對之表面，並且填注任何空隙。
請即參閱圖3A，如圖2中所示之一支撐件(例如基板22)係藉由在基板22之晶粒安裝表面21上形成一介電材料之薄膜32，以製備用於與如圖1中所示之一晶粒結合。如圖3B中所示，開孔37係在接合墊塊24上之互連位置處形成穿過薄膜。
適用於薄膜之材料包括例如多種有機聚合物之任一者，例如熱固性聚合物、熱塑性聚合物、聚醯亞胺、及對二甲苯或其衍生物之聚合物，例如一聚二甲苯聚合物(例如一聚對二甲苯)。一聚對二甲苯(例如聚對二甲苯A、或聚對二甲苯C、或聚對二甲苯N)特別適合，且一聚對二甲苯薄膜之形成可以在習知聚對二甲苯處理設備中實施。薄膜可以由適用於特殊材料之任意技術形成，且在一些實施例中薄膜係藉由化學汽相沈積形成。
較佳之薄膜材料係在薄膜形式時實質上呈非黏性，但是當進行後續處理時(例如藉由加熱、或例如藉由加熱及壓合)則可呈現有限度之黏性及柔軟度。
開孔可以藉由多種遮蔽及去除技術之任一者製成，例如藉由剝蝕(例如藉由雷射剝蝕)。較佳之薄膜材料係充分不可流動性(固態)，使得成型薄膜中之材料可以抗變形及體積變化，例如，其不流動或蠕動至開孔內，直到電氣互連已與接合墊塊接觸後。
薄膜可以直接形成(沈積及若有需要時可固化)於基板表面上。開孔可以如同薄膜一樣形成於基板上，或者，開孔可以在薄膜形成於基板上之後才製成。或者，替代性地，薄膜可以形成如同一適當厚度之薄片，及隨後疊置於基板表面上。當薄膜形成如同一薄片時，開孔可以在其疊置於基板表面上之前先製成於薄片中，或者，開孔可以在薄膜疊置於基板上之後才製成。
薄膜具有一厚度T，足以在晶粒已安裝時將頂上空間佔滿，據此，除其他因素外，薄膜厚度係與待安裝於基板上之特定晶粒之焊珠高度H相關。
圖4A揭示一將如圖1中所示之晶粒安裝至如圖3B中所示之製備基板上的階段。晶粒係定向成以作用側13面向膜表面31，且在X-Y平面中對準，使得互連17將接合墊塊24上之相對應互連位置定址。晶粒隨後如箭頭方向41所示移動趨近於基板。最後互連圓珠(或凸塊或球體)17接觸到接合墊塊24。此時組件係經處理(例如藉由加熱及壓合)以完成(焊料再熔、或固態接合)電氣連接47。另外或者在同一時間，組件係經加熱使薄膜軟化，以順應於表面，使得任何空隙皆獲填充，及導致薄膜黏接於晶粒表面，如圖4B中之編號44所示。
請參閱圖5，如圖1中所示之一晶粒(例如晶粒12)係藉由形成一介電材料之薄膜54於晶粒12之作用表面13上，以製備用於配合一基板安裝，如圖2中所示。如圖5中所示，開孔係在接合墊塊24上之互連圓珠(或凸塊或球體)17處形成穿過薄膜。
就基板上之薄膜而言，適用於一薄膜之材料包括例如多種有機聚合物之任一者，例如熱固性聚合物、熱塑性聚合物、聚醯亞胺、及對二甲苯或其衍生物之聚合物，例如一聚二甲苯聚合物(例如一聚對二甲苯)。一聚對二甲苯(例如聚對二甲苯A、或聚對二甲苯C、或聚對二甲苯N)特別適合，且一聚對二甲苯薄膜之形成可以在習知聚對二甲苯處理設備中實施。薄膜可以由適用於特殊材料之任意技術形成，且在一些實施例中薄膜係藉由化學汽相沈積形成。
較佳之薄膜材料係在薄膜形式時實質上呈非黏性，但是當進行後續處理時(例如藉由加熱、或例如藉由加熱及壓合)則可呈現有限度之黏性及柔軟度。
開孔可以藉由多種遮蔽及去除技術之任一者製成，例如藉由剝蝕(例如藉由雷射剝蝕)。較佳之薄膜材料係充分不可流動性(固態)，使得材料不致於流動或蠕動至開孔內，直到電氣互連已與接合墊塊接觸後。
薄膜可以直接形成(沈積及若有需要時可固化)於晶粒表面上。開孔可以如同薄膜一樣形成於晶粒上，或者，開孔可以在薄膜形成於晶粒上之後才製成。或者，替代性地，薄膜可以形成如同一適當厚度之薄片，及隨後疊置於晶粒表面上。當薄膜形成如同一薄片時，開孔可以在其疊置於晶粒表面上之前先製成於薄片中，或者，開孔可以在薄膜疊置於晶粒上之後才製成。
薄膜具有一厚度T，足以在晶粒已安裝時將頂上空間佔滿，據此，除其他因素外，薄膜厚度係與待安裝於晶粒上之特定晶粒之焊珠高度H相關。
圖6A揭示一將如圖3B中所示之一製備晶粒安裝至如圖2中所示之一基板上的階段。晶粒係定向成以薄膜表面51面向基板表面21，且在X-Y平面中對準，使得互連17將接合墊塊24上之相對應互連位置定址。晶粒隨後如箭頭方向61所示移動趨近於基板。最後互連圓珠(或凸塊或球體)17接觸到接合墊塊24。此時組件係經處理(例如藉由加熱及壓合)以完成(焊料再熔、或固態接合)電氣連接67。另外或者在同一時間，組件係經加熱使薄膜軟化，以順應於表面，使得任何空隙皆獲填充，及導致薄膜黏接於基板表面，如圖6B中之編號54所示。
薄膜可交替地施加於晶粒及基板兩者上，分別如圖7及8中所示。晶粒上之薄膜74具有一厚度td，且基板上之薄膜具有一厚度ts。這些厚度係經選擇，使得當晶粒安裝於基板上且薄膜表面71、81係經處理而黏接於彼此時，其組合厚度足以將頂上空間佔滿。如圖5之範例中所示，穿過薄膜74之開孔係至少曝露出接合墊塊24上之互連圓珠(或凸塊或球體)17之一表面，及如圖3B之範例中所示，穿過薄膜84之開孔87係曝露出接合墊塊24上之互連位置。
如圖4A及6A之範例中所示，晶粒係定向(圖9A)使得晶粒上之薄膜表面71面向基板上之薄膜表面81，且在X-Y平面中對準，使得互連17將接合墊塊24上之相對應互連位置定址。晶粒隨後如箭頭方向91所示移動趨近於基板。最後互連圓珠(或凸塊或球體)17接觸到接合墊塊24。此時組件係經處理(例如藉由加熱及壓合)以完成(焊料再熔、或固態接合)電氣連接97。另外或者在同一時間，組件係經加熱使薄膜軟化，以令其接觸表面順應於彼此，及導致薄膜黏接於彼此，如圖9B中之編號94所示。
另者，在晶粒互連結合於接合墊塊上之互連位置，且電氣連接完成後，薄膜可以藉由一化學汽相沈積(CVD)製程形成。此方法係利用圖10A、10B及11中之範例說明。圖10A及10B揭示一將覆晶電氣連接於一基板之習知方法。在圖10A中，如圖1中所示之一晶粒及如圖2中所示之一基板係定向使得晶粒之作用側13面向基板之晶粒安裝側21，且其對準使得晶粒上之互連(圓珠或凸塊或球體)17將基板上之接合墊塊24上之相對應互連位置定址。晶粒及基板如箭頭方向101所示移動趨近於彼此。最後互連(圓珠或凸塊或球體)17接觸到接合墊塊24，隨後組件係經加熱且，典型上，晶粒及基板係壓向彼此，以完成電氣連接(迴焊或固態接合)107，如圖10B中所示。晶粒及基板之間之一頂上空間104必須現在填充且，根據本發明之一實施例其係藉由將電氣連接之組件曝露於一CVD製程而完成。在特定實施例中，介電材料係對二甲苯或其衍生物之一聚合物，例如一聚二甲苯聚合物(例如一聚對二甲苯)。一聚對二甲苯(例如聚對二甲苯A、或聚對二甲苯C、或聚對二甲苯N)特別適合，且一聚對二甲苯薄膜之形成可以在習知聚對二甲苯處理設備中實施。CVD製程係在所有曝露於製程之表面上產生一敷形塗層，且除其他因素外，塗層之厚度取決於曝露長度。該過程實施直到晶粒及基板之間之頂上空間已完全由介電材料填充為止，如圖11中之編號114所示。CVD製程係在所有曝露於製程之表面上產生一敷形塗層，且除其他因素外，塗層之厚度取決於曝露長度。吾人想要的是避免塗佈於某些表面且，據此，一遮罩或配件可用於限制這些表面對於CVD環境之曝露。
在圖式說明中，其揭示單一晶粒及單一基板。可以瞭解的是，在晶粒切單之前，較佳為實施某些晶粒處理步驟。例如，當一過程使用製備之晶粒時，薄膜可以形成於在晶圓高度之晶粒上，且互連(圓珠或凸塊或球體)可以安裝於在晶圓高度之晶粒墊塊上。同樣可以瞭解的是，典型上多數個基板是在一長條之基板上呈一列或一陣列，及在從該長條切割或沖切下個別封裝或封裝組件之前，較佳為實施某些封裝處理步驟。例如，所示製程步驟之任一者皆可在多數個未切單之基板上實施。
其他實施例皆在本發明之範疇內。
11、11’．．．背側
12、12’．．．晶粒
13、13’．．．作用(前)側
14、14’．．．互連墊塊
15、15’．．．側壁
17、17’．．．互連球
20、20’．．．基板
21、21’．．．連接側
22、22’．．．介電材料層
23、23’．．．反轉側
24、24’．．．接合墊塊
31、51、71、81．．．薄膜表面
32、54、74、84、94、114．．．介電性薄膜
37、87．．．開孔
41、61、91、101．．．箭頭方向
44．．．晶粒表面
47、67、97、107．．．電氣連接
104．．．頂上空間
圖1A係示意圖，其以截面揭示一半導體晶粒。
圖1B係示意圖，其以平面揭示圖1A中之一半導體晶粒。
圖2A係示意圖，其以截面揭示一基板。
圖2B係示意圖，其以平面揭示圖2A中之一基板。
圖1C係示意圖，其以截面揭示一半導體晶粒。
圖1D係示意圖，其以平面揭示圖1C中之一半導體晶粒。
圖2C係示意圖，其以截面揭示一基板。
圖2D係示意圖，其以平面揭示圖2C中之一基板。
圖3A及3B係示意圖，其以截面揭示根據本發明之一實施例的一基板之製備。
圖4A及4B係示意圖，其以截面揭示根據本發明之一實施例的一製程中之階段，用於將如圖1中所示一晶粒安裝於且電氣連接於如圖3B中所製備之一基板上。
圖5係示意圖，其以截面揭示根據本發明之一實施例而製備的一晶粒。
圖6A及6B係示意圖，其以截面揭示根據本發明之一實施例的一製程中之階段，用於將如圖5中所示一製備晶粒安裝於且電氣連接於如圖2中所示之一基板上。
圖7及8係示意圖，其以截面揭示各根據本發明之另一實施例而製備的一晶粒(圖7)及一基板(圖8)。
圖9A及9B係示意圖，其以截面揭示根據本發明之一實施例的一製程中之階段，用於將如圖7中所示一製備晶粒安裝於且電氣連接於如圖8中所示之一基板上。
圖10A、10B及11係示意圖，其以截面揭示根據本發明之一實施例的一製程中之階段，用於藉由填充材料之化學汽相沈積而形成一介電質填充。
12．．．晶粒
22．．．介電材料層
107．．．電氣連接
114．．．介電性薄膜

Claims (29)

  1. 一種用於製成一晶粒與一基板之一覆晶互連的方法，該晶粒在其一作用側上具有電氣互連及該基板在其一晶粒安裝側的一基板表面上具有互連位置，該方法包含：施加一介電性薄膜於該晶粒之該作用側上，其中該介電性薄膜具有曝露該晶粒上之電氣互連的複數個開孔，且該介電性薄膜具有厚度，該厚度完全佔據該晶粒之該作用側與該基板表面之間的頂上空間；相關於該基板而將該晶粒定向與對準，且將該晶粒移向該基板，使得互連接觸形成於該晶粒上之電氣互連與該基板上之對應互連位置之間；處理該生成之組件，以完成該晶粒上之電氣互連與該基板上之對應互連位置的電氣連接；及加熱該介電性薄膜，使得該介電性薄膜填充全部的該頂上空間，其中，該晶粒上之該電氣互連並未延伸至該薄膜的薄膜表面。
  2. 一種用於製成一晶粒與一基板之一覆晶互連的方法，該晶粒在其一作用側上具有電氣互連及該基板在其一晶粒安裝側上具有互連位置，該方法包含：施加一介電性薄膜於該基板之該晶粒安裝側上，使得該介電性薄膜具有厚度，該厚度完全佔據該晶粒之該作用側與面對該晶粒之該作用側的該基板之一表面之間的頂上空間； 相關於該基板而將該晶粒定向與對準，且將該晶粒移向該基板，使得互連接觸形成於該晶粒上之電氣互連與該基板上之對應互連位置之間；加熱該介電性薄膜，使得該介電性薄膜完全佔據該頂上空間；及處理該生成之組件，以完成該晶粒上之電氣互連與該基板上之對應互連位置的電氣連接，其中，該薄膜具有複數個開孔，其曝露該基板上之電氣互連，其中，該基板上之該電氣互連並未延伸至該薄膜的薄膜表面。
  3. 如申請專利範圍第1或2項之方法，其中該處理包含加熱。
  4. 如申請專利範圍第1或2項之方法，其中該處理包含強制該晶粒趨近於該基板，以將該晶粒上之電氣互連壓在該基板上之對應互連位置。
  5. 如申請專利範圍第1或2項之方法，其中該電氣互連包含圓珠或凸塊或球體。
  6. 如申請專利範圍第1或2項之方法，其中該電氣互連包含焊料，及其中該處理包含加熱以使焊料迴焊。
  7. 如申請專利範圍第1或2項之方法，其中該電氣互連包含金，及其中該處理包含強制該晶粒趨近於該基板，以將該晶粒上之互連壓在該基板上之對應互連位置，及形成一固態電氣連接。
  8. 如申請專利範圍第1或2項之方法，其中該電氣互連包含一可固化之互連材料，及其中該處理包含將該互連材料固化。
  9. 如申請專利範圍第1項之方法，其中該處理包含加熱該組件，以令該薄膜黏接於該基板之晶粒附著側。
  10. 如申請專利範圍第2項之方法，其中該處理包含加熱該組件，以令該薄膜黏接於該晶粒之該作用側。
  11. 如申請專利範圍第1或2項之方法，其中該介電性薄膜之材料包含有機聚合物。
  12. 如申請專利範圍第1或2項之方法，其中該介電性薄膜之材料包含熱固性聚合物。
  13. 如申請專利範圍第1項之方法，其中該介電性薄膜之材料包含熱塑性聚合物。
  14. 如申請專利範圍第1或2項之方法，其中該介電性薄膜之材料包含聚醯亞胺。
  15. 如申請專利範圍第1或2項之方法，其中該介電材料包含對二甲苯或其衍生物之聚合物。
  16. 如申請專利範圍第1或2項之方法，其中該介電材料包含聚二甲苯聚合物。
  17. 如申請專利範圍第1或2項之方法，其中該介電材料包含聚對二甲苯。
  18. 如申請專利範圍第17項之方法，其中該聚對二甲苯包含聚對二甲苯A、或聚對二甲苯C、或聚對二甲苯N。
  19. 一種覆晶封裝，其包含一半導體晶粒，該半導體晶粒具有形成於其一作用側上之一介電性薄膜，該介電性薄膜具有複數個開孔，其曝露該晶粒上之電氣互連，且該介電性薄膜具有厚度，該厚度完全佔據該晶粒之該作用側與面對該晶粒之該作用側的該基板之一表面之間的頂上空間，其中，該晶粒上之該電氣互連並未延伸至該介電性薄膜的薄膜表面，該半導體晶粒安裝且電氣連接於一基板，使得在該晶粒上的該電氣互連並列設置且電氣連接於在該基板的晶粒安裝側之對應的互連位置，且使得該介電性薄膜填充全部的該頂上空間，其中，該介電性薄膜包含對二甲苯或其衍生物之聚合物、聚二甲苯聚合物或聚對二甲苯。
  20. 如申請專利範圍第19項之覆晶封裝，其中，該介電性薄膜係第一介電性膜，其中，該封裝更包含形成在該基板的該晶粒安裝側上的第二介電性膜，該第二介電性膜具有複數個開孔，其曝露該互連位置，其中，該互連位置並未延伸至該第二薄膜的薄膜表面，其中，該第二薄膜包含對二甲苯或其衍生物之聚合物、聚二甲苯聚合物或聚對二甲苯。
  21. 如申請專利範圍第19項之覆晶封裝，其中該薄膜實質上不可流動。
  22. 如申請專利範圍第19項之覆晶封裝，其中該薄膜係抗機械性變形及體積變化。
  23. 如申請專利範圍第19項之覆晶封裝，其中該介電 性薄膜之材料包含有機聚合物。
  24. 如申請專利範圍第19項之覆晶封裝，其中該介電性薄膜之材料包含聚對二甲苯。
  25. 一種覆晶封裝，其包含具有一作用表面的一半導體晶粒，該半導體晶粒安裝且電氣連接於一基板，使得在該晶粒上的電氣互連面對在該基板的一晶粒安裝表面的對應的互連位置，該晶粒上的該電氣互連並列設置且電氣連接於在該基板的該晶粒安裝側之對應的互連位置，其中，該封裝包含形成於該基板的該晶粒安裝側上之一介電性薄膜，該介電性薄膜具有厚度，該厚度完全佔據該晶粒之該作用表面與該基板之該晶粒安裝表面之間的頂上空間，且該介電性薄膜具有複數個開孔，其曝露該互連位置，其中，該互連位置並未延伸至該介電性薄膜的薄膜表面，其中，該介電性薄膜包含對二甲苯或其衍生物之聚合物、聚二甲苯聚合物或聚對二甲苯。
  26. 如申請專利範圍第25項之覆晶封裝，其中該薄膜實質上不可流動。
  27. 如申請專利範圍第25項之覆晶封裝，其中該薄膜係抗機械性變形及體積變化。
  28. 如申請專利範圍第25項之覆晶封裝，其中該介電性薄膜之材料包含有機聚合物。
  29. 如申請專利範圍第25項之覆晶封裝，其中該介電性薄膜之材料包含聚對二甲苯。
TW099114942A 2009-05-14 2010-05-11 覆晶底部填充 TWI611485B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US17844309P 2009-05-14 2009-05-14
US61/178,443 2009-05-14
US12/776,262 2010-05-07
US12/776,262 US20110115099A1 (en) 2009-05-14 2010-05-07 Flip-chip underfill

Publications (2)

Publication Number Publication Date
TW201115662A TW201115662A (en) 2011-05-01
TWI611485B true TWI611485B (zh) 2018-01-11

Family

ID=43085512

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099114942A TWI611485B (zh) 2009-05-14 2010-05-11 覆晶底部填充

Country Status (3)

Country Link
US (1) US20110115099A1 (zh)
TW (1) TWI611485B (zh)
WO (1) WO2010132338A2 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8587088B2 (en) 2011-02-17 2013-11-19 Apple Inc. Side-mounted controller and methods for making the same
US9899339B2 (en) * 2012-11-05 2018-02-20 Texas Instruments Incorporated Discrete device mounted on substrate
US8847412B2 (en) 2012-11-09 2014-09-30 Invensas Corporation Microelectronic assembly with thermally and electrically conductive underfill

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080247149A1 (en) * 2004-04-27 2008-10-09 Advanced Semiconductor Engineering, Inc. Chip package structure
US20090045507A1 (en) * 2003-11-10 2009-02-19 Stats Chippac Ltd. Flip chip interconnection
US20090065916A1 (en) * 2007-09-10 2009-03-12 Vertical Circuits, Inc. Semiconductor die mount by conformal die coating

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040630A (en) * 1998-04-13 2000-03-21 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same
US6924171B2 (en) * 2001-02-13 2005-08-02 International Business Machines Corporation Bilayer wafer-level underfill
US7265994B2 (en) * 2003-01-31 2007-09-04 Freescale Semiconductor, Inc. Underfill film for printed wiring assemblies
US7215018B2 (en) * 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
TWI473183B (zh) * 2007-06-19 2015-02-11 Invensas Corp 可堆疊的積體電路晶片的晶圓水平表面鈍化
US20100117224A1 (en) * 2008-08-29 2010-05-13 Vertical Circuits, Inc. Sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090045507A1 (en) * 2003-11-10 2009-02-19 Stats Chippac Ltd. Flip chip interconnection
US20080247149A1 (en) * 2004-04-27 2008-10-09 Advanced Semiconductor Engineering, Inc. Chip package structure
US20090065916A1 (en) * 2007-09-10 2009-03-12 Vertical Circuits, Inc. Semiconductor die mount by conformal die coating

Also Published As

Publication number Publication date
WO2010132338A2 (en) 2010-11-18
TW201115662A (en) 2011-05-01
WO2010132338A3 (en) 2011-02-24
US20110115099A1 (en) 2011-05-19

Similar Documents

Publication Publication Date Title
TWI491007B (zh) 藉由脈衝式分配所形成之電互連
TWI515863B (zh) 載體安裝式電氣互連晶粒組成件
TWI570879B (zh) 半導體總成及晶粒堆疊總成
JP5186550B2 (ja) 電気的相互接続構造体及びその形成方法
US7618844B2 (en) Method of packaging and interconnection of integrated circuits
US8272120B2 (en) Apparatus for applying solder to semiconductor chips using decals with aperatures present therein
US8541291B2 (en) Thermo-compression bonded electrical interconnect structure and method
US9508594B2 (en) Fabricating pillar solder bump
CN110999551A (zh) 高密度互连粘合带
WO2006071611A1 (en) Microelectronic package having stacked semiconductor devices and a process for its fabrication
JP2004538619A (ja) バンプのない積層配線構造を有する超小型電子パッケージ
TW201603218A (zh) 導電連接、具有此種連接的結構、及製造方法
TW200525666A (en) Bump-on-lead flip chip interconnection
TWI462246B (zh) 緊密封裝陣列與可撓性電路之互接方法
TWI736072B (zh) 封裝結構與其形成方法
TWI611485B (zh) 覆晶底部填充
JP3917484B2 (ja) 半導体装置の製造方法および半導体装置
JP6769721B2 (ja) 電子部品、異方性接続構造体、電子部品の設計方法
US9263376B2 (en) Chip interposer, semiconductor device, and method for manufacturing a semiconductor device
TW201448071A (zh) 晶片堆疊、具有晶片堆疊之半導體裝置及晶片堆疊之製造方法
CN103681455A (zh) 管芯底部填充结构和方法
CN113035830A (zh) 半导体结构及其制造方法
CN218887167U (zh) 半导体封装装置
JP4566915B2 (ja) 半導体装置の実装体、半導体装置実装体の製造方法
TW201030935A (en) Semiconductor die interconnect formed by aerosol application of electrically conductive material

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees