CN103681455A - 管芯底部填充结构和方法 - Google Patents

管芯底部填充结构和方法 Download PDF

Info

Publication number
CN103681455A
CN103681455A CN201310384698.7A CN201310384698A CN103681455A CN 103681455 A CN103681455 A CN 103681455A CN 201310384698 A CN201310384698 A CN 201310384698A CN 103681455 A CN103681455 A CN 103681455A
Authority
CN
China
Prior art keywords
stage resin
resin layer
tube core
substrate
cup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310384698.7A
Other languages
English (en)
Other versions
CN103681455B (zh
Inventor
K·P·瓦赫莱尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103681455A publication Critical patent/CN103681455A/zh
Application granted granted Critical
Publication of CN103681455B publication Critical patent/CN103681455B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13561—On the entire surface of the core, i.e. integral coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本申请涉及管芯底部填充结构和方法。一种将具有从其一个面112突出的多个铜柱（CuP）114的IC晶片100附接到在其一个面132上具有多个接触焊盘134的衬底130的方法包括：将其中具有大量填料颗粒126的膜层124施加到晶片100的所述一个面112；将其中基本不具有填料颗粒的甲阶树脂122施加到衬底130的所述一个面132；以及将所述膜层124与所述甲阶树脂122接合。

Description

管芯底部填充结构和方法
背景技术
在过去十年，已经出现倒装芯片技术作为用于将诸如集成电路（IC）管芯和微机电系统（MEMS）这样的半导体器件互连到诸如印刷电路板这样的衬底、其它互连板和其它管芯的金属丝键合的普遍代替手段。
“倒装芯片”也被称为“受控塌陷芯片连接”或者简称“C4”。利用倒装芯片技术，焊料球/凸块被附接到管芯/芯片的一个面上的电连接焊盘。通常在晶片级处理管芯，即，当多个相同的管芯仍是大“晶片”的一部分时处理管芯。焊料球被沉积在晶片的顶侧上的芯片焊盘上。在此该晶片有时被“单粒化（singulated）”或者被“划片”（切割成单独管芯）以提供多个单独倒装芯片管芯，每个管芯具有位于顶面表面上的焊料球。然后芯片可以被“倒装”以将焊料球连接到衬底（诸如在上面安装倒装芯片的印刷电路板）的顶表面上的匹配的接触焊盘。通常通过回流加热来提供焊料球附接。
在焊料凸块形成之后并且仍然处于晶片形式时，有时晶片被进一步处理以将其连接到另一个大的衬底，诸如第二晶片，该衬底可以包括例如另一个倒装芯片晶片或者另一种类型的管芯的晶片。第一晶片上与稍后形成的管芯相对应的区域被附接到第二晶片上的对应区域。之后管芯单元上的各个管芯或者“倒装芯片组件”被从所附接的晶片上单粒化。在此情形下其它衬底通常在与连接倒装芯片管芯的一面相反的面上具有互联结构。然后该另一侧面可以连接到另一个衬底，诸如印刷电路板。随着IC管芯变得更复杂，倒装芯片上的焊料凸块/焊料球的数量急剧增加。尽管在过去通常通过附接到芯片接触焊盘的相对大的圆形焊料球来提供焊料球，但最近铜柱（CuP）已经被用于代替焊料球。CuP是细长铜桩构件，其一端附接到管芯上的接触焊盘。CuP沿着垂直于管芯的面的方向从管芯向外延伸。每个CuP具有附接在其远端的子弹形焊料件。如通过回流加热，CuP被这个子弹形焊料件焊接到衬底上的相应接触焊盘。CuP能够被比常规焊料球/凸块更加密集地定位，即以“更高的节距”定位。
附图说明
图1是涂覆了乙阶树脂的晶片的管芯部分的顶视平面图；
图2是图1的管芯部分将要附接的衬底部分的顶视平面图；
图3是附接到图2的衬底部分的图1的管芯部分的截面侧正视图；
图4是焊接到衬底上的接触焊盘的管芯上的CuP的放大照片，其中填料颗粒被束缚在焊料接头中；
图5是更高放大率的图4的照片；
图6是晶片和将要施加于其上的流延膜带的分解透视图；
图7是在紧接着被附接到衬底的相应部分之前的晶片的管芯部分的详细截面侧面图；
图8是图7的管芯部分和衬底部分在附接之后的放大截面侧正视图；
图9是从例如图8所示的晶片/衬底组件单粒化之后的管芯/衬底组件的透视图。
具体实施方式
本申请总体上公开了将具有从其一个面112突出的多个铜柱（CuP）114的IC晶片100附接到具有在其一个面132上的多个接触焊盘134的衬底130的方法。该方法包括将其中具有大量填料颗粒126的膜层124施加到管芯130的一个面112。该方法还包括将其中基本上不具有填料颗粒的甲阶树脂122施加到衬底130的一个面132，以及将膜层124与甲阶树脂122接合。本申请总体上还公开了电气装置170，该电气装置包括具有第一面132的衬底130，该第一面具有多个接触焊盘。装置170还包括具有第一面112的管芯110，该第一面具有从其延伸出的多个CuP114。每个CuP114具有远端，在该远端上安装有焊料尖头116。每个焊料尖头116也具有远端。第一丙阶树脂层124中具有相对较大量的填料颗粒126。第一丙阶树脂层124具有粘附于管芯110的第一面112的第一表面和与第一表面相反的第二表面。第二甲阶树脂层122中如果有也只具有相对较少量的填料颗粒126。第二丙阶树脂层122具有第一表面和与第一表面相反的第二表面，该第一表面粘附于衬底130的第一面132，该第二表面粘附于第一丙阶树脂层124的第二表面。至此公开了晶片/衬底附接方法和可以通过使用该方法形成的管芯组件170，下面将详细描述该方法和装置及其变体。
用于倒装芯片的底部填充物的主要目的是将倒装芯片牢固地物理附接到相关联的衬底。具有CuP的管芯也通过CuP与衬底的接触焊盘之间的焊料接头连接而被物理连接和电连接到相关联的衬底。尽管在此详细描述了具有CuP的倒装芯片的附接，但本领域技术人员应理解的是可以按照相同的基本方式来附接具有焊料球/凸块而不是CuP的倒装芯片。
底部填充物通常包含可热固化树脂成分和颗粒填料成分。与没有填料的底部填充物相比，颗粒填料成分充分增加了底部填充物的物理强度。底部填充物的树脂成分可以具有三种不同的物理阶段：甲阶（液体）；乙阶（膏体/部分固化）；以及丙阶（硬/完全固化）。存在多种方法来施加底部填充物。有时在已经做出管芯/晶片和衬底之间的焊料连接之后施加底部填充物。在这种情况下，其中树脂成分处于液体形式（甲阶树脂）的底部填充物被施加到衬底和上覆管芯/晶片的周围，并且通过芯吸或毛细作用被携带到管芯/晶片的下方。通过对管芯/晶片和衬底施加热量和压力，该甲阶树脂随后改变为乙阶树脂并且随后变为丙阶树脂。用于施加热量和压力的工具在本领域中是常规的且众所周知的。
如图1和图2所示，施加底部填充物的另一种方法是将树脂膏体（乙阶树脂）底部填充物22施加到晶片8的每个管芯部分10的面12（CuP14从该面12突出）。可替换地，树脂膏体底部填充物22可以被施加到将要附接管芯10的衬底30的一部分31的面32上。在将CuP14焊接到衬底接触焊盘34之前完成该膏体施加。使用这种方法，靠近每个管芯部分10或每个衬底部分31的中心以大致星形图案施加底部填充物，并且然后在对其施加热量的过程中抵靠衬底30推动/挤压（urge）晶片8。可以通过本领域已知的常规工具来施加热量和压力。在一个实施例中，挤压力可以是约70N并且温度可以是约270℃。晶片8和衬底30之间的压力促使被加热的底部填充物在CuP14周围“渗出”以填充到晶片8和衬底30之间的任何空隙中。然而，特别是对于高节距CuP14的管芯/晶片，由于来自CuP14的流动干扰并且由于底部填充物22的粘稠度随着其开始向外流动并固化而增加，底部填充物可能不能完全流到所有空隙中。另外，到达管芯10的外周的底部填充物22的量通常少于更靠近管芯的中心的量，导致管芯随着键合压力被施加而在边缘处翘曲，如图3所示。另一个问题是如图4所示，填料的颗粒23经常被束缚在CuP14的端部的焊料件16与相关联的接触焊盘34之间。作为这种颗粒23包埋的结果，焊料接头20比“干净”接头更弱并且对电子流具有增大的阻力。图4和图5的截面照片以不同的放大率示出具有被束缚填料颗粒23的此类焊料接头20。这种缺陷在是业内已被广泛认知，并且创建避免这种缺陷的工艺是世界范围内的研究的主题。该研究关注于使焊料熔点与底部填充物流动和底部填充物固化时间及温度属性相匹配的困难任务。相信本申请人是第一个认识到将焊料熔点与底部填充物属性分离以消除该缺陷的根本原因的方法。在最经常使用的倒装芯片以封装衬底附接的现有技术方法中，管芯被一次一个地安装在与管芯具有相同置着区（footprint）的衬底单元上。在管芯附接之前，衬底单元以预定图案被可去除地粘性安装在细长条带上。乙阶树脂（膏体）的星形片被施加到封装衬底单元上而不是芯片或晶片上。将其施加到衬底单元上进一步使得底部填充物流变能力的控制复杂化。封装衬底单元被定位在送入组装机器中的条带上的多个位置处。朝着条带的前边缘（前引到机器中的边缘）定位的衬底单元比靠近条带的尾部边缘的衬底在固化温度下花费更少的时间。这种时间和温度的变化造成工艺性能的进一步变化。使用本文公开的新工艺，甲阶材料可以进行到更大范围的固化并且仍流动而不成为障碍，并且因为其从较低程度的固化开始而具有高粘性。
图6示出典型的晶片100，其具有多个相同的物理连接的倒装芯片管芯部分110。通常，倒装芯片晶片100被单粒化或者被“划片”为单独的管芯110，然后管芯110被一次一个地附接到对应的小衬底单元131。存在布置在条带上并且通过制造操作并行处理的多个小衬底单元131。然而，有时整个晶片100被附接到第二晶片130（通常是另一个管芯晶片），并且第一晶片100和第二晶片130随后被一起划片为单独的倒装芯片110到衬底单元131组件（通常是管芯到管芯组件），如图9的170所示。这些组件170被进一步组装成各种形式的电子模块。应理解的是此处描述的管芯衬底附接工艺可以在管芯级或晶片级进行。因此，如此处作出的对管芯110和衬底单元131的引用或者对晶片100和衬底130的引用应被理解为总体上是可互换的，除非上下文清楚地展现出意欲表示其它含义。类似地，应理解的是，在图1、图3、图7和图8中，当描述晶片级操作时被称为晶片100的管芯部分110以及衬底130的部分131的部件将指代在管芯级进行附接操作时的各个管芯110和各个小衬底单元131。
图6所示的晶片100被显示为定位在流延膜124片材的下方，该流延膜片材可以被剪裁为如虚线125所示并且随后附接到晶片的第一面112。可替换地，可以在膜层124附接到晶片100之后进行剪裁。术语晶片的“第一面”或“一个面”是指CuP从其突出的面112。经常当本领域技术人员提及倒装芯片面时，该面112被称为“顶”面，因为在附接到衬底之前其被“翻转”。然而，由于在其被翻转之后该面112朝着衬底向下定位，所以有时也称为“底”面。为了避免混淆，当提及CuP从其突出的面112时，使用术语“第一面”或“一个面”。通过对其施加热量和压力达到取决于膜层124的成分的预定时间段，流延膜片124可以被附接到晶片110的第一面112。该膜层124可以是包含大量填料材料126的乙阶树脂。与不具有填料的情况下的强度相比，填料材料126极大地提高了该膜层的粘接强度。在图7和图8中以截面图示出了膜层124。适用于本申请的膜层的一个示例是Toray LNA2432，其厚度为20-30μm并且具有50-70%重量百分比的填料。此处所用的短语“大量填料材料”的含义将一定程度上依赖于所使用的树脂的类型和填料材料的类型，但是总体上表示填料材料的量大于膜层的总重量的约40%重量百分比。如图7和图8所示，膜层124可以具有与第一面122和CuP114上附接子弹形引导件16的一点之间的距离大致相同的厚度。可以使用具有屈服表面的工具将膜层124附接到晶片110，该屈服表面允许子弹形引导件116穿透膜层124并且从膜层外面129突出。作为施加热量和压力的结果，膜层内面128变为粘性附接到管芯表面122。
衬底130/衬底单元131具有“第一表面”或者“一个表面”132，在该表面上具有接触焊盘134。如图7和图8所示，接触焊盘134可以均由其上具有金属帽138的内部铜构件136构造，该金属帽138可以由镍、金或者各种合金成分的焊料制成。每个接触焊盘134可以被定位在阱或凹坑140中，该阱或凹坑140具有在衬底的顶表面148下方约10μm距离处的基底。衬底的顶表面148可以在常规印刷电路板焊料掩模的层142上。在一个实施例中，从凹坑的底部到顶表面148的距离可以是约25μm。在图7和图8所示的实施例中，每个凹坑140可以包含一个或更多个接触焊盘134（未示出）。每个接触焊盘凹坑140被甲阶树脂122填充，该甲阶树脂基本上不包含填料颗粒，即填料颗粒的数量名义上为零，但是某一少量的颗粒（例如2%重量百分比）是可以允许的，尽管是不期望的。树脂122可以被选择为与膜层124中的树脂键合的类型并且可以是相同类型的树脂。树脂122也被选择为与顶表面148上的焊料掩模材料键合的类型。施加树脂的一种方式是丝网印刷。另一种方式是喷墨印刷。这两种印刷技术都是本领域已知的。喷墨法可以允许更好地控制所施加的甲阶树脂的量。
如图7所示，晶片100被定位为使得其CuP114对准衬底上的接触焊盘134。晶片100被向下推动以使得每个CuP114上的子弹形焊料件112与衬底上的接触焊盘134进行接触，如图8所示。晶片100的向下运动是在诸如回流炉这样的加热环境下进行的，其中回流温度可以是例如约260℃。作为加压（例如约60-80N）和加热的结果，子弹形焊料件熔化并且与接触焊盘134键合。由于接触焊盘凹坑140中的甲阶树脂122中名义上没有填料颗粒，所以在其中形成的焊料接头120是不含颗粒的。因而产生高强度的键合。另外，由于膜层中的树脂被选择为与甲阶树脂122和表面148上的材料兼容，所以其与两者良好地键合，并且晶片110和衬底130被牢固地附接。从以上描述应理解的是作为液体施加的甲阶树脂122填充了衬底130的表面拓扑结构中的全部空隙。另外，由于膜层124在垂直于管芯表面的方向上作为片材被施加，因此不会遇到径向流阻，该径向流阻会导致在衬底110的周边或者在CuP周围的空隙中缺少底部填充物。另外，通过穿透甲阶树脂来将CuP114键合到封装衬底接触焊盘134所需要的压力低于要求CuP14穿透厚的乙阶树脂层的现有技术工艺中的压力。
在将CuP114焊接到相关联的接触焊盘134之后，每个管芯/衬底单元经历后烘烤工艺，在一个实施例中该后烘烤工艺是在约150℃的温度下持续约一小时的时间段。该后烘烤工艺将膜层124中的乙阶树脂转化为丙阶树脂并且将接触焊盘凹坑140中的甲阶树脂122转化为丙阶树脂。
如上所述在将晶片100附接到衬底130之后，得到的晶片和附接的衬底组件可以被单粒化成如图9所示的单独的管芯/衬底单元组件170。当在单独的管芯110和衬底单元131上执行附接工艺时，得到的单元的结构与图9的170相同。每个此类单元170具有上部管芯部分110，该上部管芯部分110通过图8的第一丙阶树脂层（之前的膜层124）和第二丙阶树脂层162（之前的甲阶树脂层122）以及通过在CuP114与接触焊盘134之间形成的焊料接头120机械地附接到衬底部分131。应理解的是在此使用图8来描述在管芯100/管芯部分111的CuP14与衬底130/衬底部分131的接触焊盘134首次接触时以及在焊接工艺和后烘烤固化工艺完成并且树脂层122、124均已转化为丙阶树脂层之后这两个时间的管芯/衬底单元的结构。
如前所述，可以在晶片级或管芯（经划片的晶片）级或部分在晶片级且部分在管芯级进行本文描述的附接工艺。因而应理解的是本说明书和权利要求书中使用的术语“管芯110”是指晶片100的划片前的管芯部分以及已经从管芯晶片100被单粒化的管芯单元。类似地，术语“衬底”在此用于指代大的衬底或者可以从其中划分出各个衬底单元的“衬底晶片”130以及与管芯110具有相同置着区的各个单元。
尽管本文公开了用于将管芯附接到衬底的方法和通过该方法形成的装置的某些特定实施例，但在阅读本公开之后本领域技术人员应理解可以对所描述的实施例做出各种变化并加以使用。除了由现有技术限定的范围以外，随附权利要求的语言意在被广泛理解为覆盖这些变化。

Claims (20)

1.一种将具有从其一个面突出的多个铜柱即CuP的IC管芯附接到在其一个面上具有多个接触焊盘的衬底的方法，所述方法包括：
将其中具有大量填料颗粒的膜层施加到所述管芯的所述一个面；以及
将其中基本不具有填料颗粒的甲阶树脂施加到所述衬底的所述一个面。
2.根据权利要求1所述的方法，其还包括：将所述膜层与所述甲阶树脂接合。
3.根据权利要求2所述的方法，其还包括：至少加热所述衬底并且在所述接合期间将所述管芯和所述衬底挤压在一起。
4.根据权利要求1所述的方法，其中所述将膜层施加到所述管芯的一个面包括施加具有树脂成分的膜层，所述树脂成分与施加到所述衬底的所述一个面的所述甲阶树脂的成分相同。
5.根据权利要求1所述的方法，其中所述施加膜层包括将流延膜层施加到所述管芯的所述一个面。
6.根据权利要求2所述的方法，其中所述施加所述膜层包括将所述膜层粘附于所述管芯的所述一个面。
7.根据权利要求5所述的方法，其还包括加热并固化施加到所述衬底的所述一个面的所述甲阶树脂以促使得到的乙阶树脂粘附于所述衬底的所述一个面并粘附于所述膜层。
8.根据权利要求1所述的方法，其还包括：利用所述CuP穿透所述膜层。
9.根据权利要求1所述的方法，其中所述将甲阶树脂施加到所述衬底的所述一个面包括利用所述甲阶树脂覆盖所述衬底上的所述多个接触焊盘。
10.根据权利要求9所述的方法，其中施加甲阶树脂包括将甲阶树脂施加至一深度，该深度约等于在所述衬底第一面表面上限定接触焊盘阱的结构的高度。
11.根据权利要求10所述的方法，其中所述施加膜层包括施加具有一厚度的膜层，所述厚度小于所述管芯的所述一个面表面与安装在从所述管芯的所述一个面表面延伸的所述多个CuP中的一个上的焊料尖头的远端之间的距离。
12.根据权利要求11所述的方法，其还包括：将所述焊料尖头焊接到所述多个接触焊盘中的一个。
13.根据权利要求12所述的方法，其包括：烘烤所述管芯和所述衬底直至两个树脂层中的树脂都被转化为丙阶树脂。
14.一种电气装置，其包括：
具有包括多个接触焊盘的第一面的衬底；
具有第一面的管芯；
从所述管芯的所述第一面延伸的多个CuP，每个CuP具有远端和安装在所述CuP远端上的焊料尖头，每个所述焊料尖头具有远端；
在其中具有相对较大量的填料颗粒的第一丙阶树脂层，所述第一丙阶树脂层具有粘附于所述管芯的所述第一面的第一表面并且具有与其所述第一表面相反的第二表面；以及
在其中如果有也只具有相对较少量的填料颗粒的第二丙阶树脂层，所述第二丙阶树脂层具有粘附于所述衬底第一面的第一表面并且具有粘附于所述第一丙阶树脂层的所述第二表面的与所述第一表面相反的第二表面。
15.根据权利要求14所述的电气装置，其中所述多个CuP中每一个的所述焊料尖头被焊接到所述接触焊盘中相关联的一个接触焊盘。
16.根据权利要求15所述的电气装置，其中所述第一丙阶树脂层具有一厚度，所述厚度小于所述管芯第一面表面与在所述焊料尖头熔化之前所述CuP上的所述焊料尖头的所述远端之间的距离。
17.根据权利要求16所述的电气装置，其中焊接到相关联的接触焊盘的每个所述焊料尖头被所述第二丙阶树脂层包封。
18.根据权利要求14所述的电气装置，其中所述第一丙阶树脂层具有一树脂成分，并且其中所述第二丙阶树脂层具有一树脂成分，并且其中所述第一丙阶树脂层的所述树脂成分与所述第二丙阶树脂层的所述树脂成分具有相同组分。
19.根据权利要求14所述的电气装置，其中所述第一丙阶树脂层具有在约30%重量百分比到约70%重量百分比之间的填料颗粒成分，并且其中所述第二丙阶树脂层具有约0%重量百分比的填料颗粒成分。
20.一种倒装芯片组件，其包括：
具有包括多个接触焊盘的第一面的衬底；
具有第一面的管芯；
从所述管芯的所述第一面延伸的多个CuP，每个CuP具有远端和安装在所述CuP远端上的焊料尖头，所述焊料尖头具有远端；
在其中具有相对大量的填料颗粒的第一丙阶树脂层，所述第一丙阶树脂层具有粘附于所述管芯的所述第一面的第一表面并且具有与其所述第一表面相反的第二表面；
在其中如果有也只具有相对较少量的填料颗粒的第二丙阶树脂层，所述第二丙阶树脂层具有粘附于所述衬底第一面表面的第一表面并且具有粘附于所述第一丙阶树脂层的所述第二表面的与所述第一表面相反的第二表面；
所述多个CuP中的每一个的所述焊料尖头被焊接到所述接触焊盘中相关联的一个接触焊盘；
所述第一丙阶树脂层具有一厚度，所述厚度小于所述管芯第一面表面与在所述焊料尖头熔化之前所述CuP中的一个CuP上的所述焊料尖头的所述远端之间的距离；
焊接到相关联的接触焊盘的每个所述焊料尖头被所述第二丙阶树脂层包封；
所述第一丙阶树脂层具有树脂成分并且其中所述第二丙阶树脂层具有与所述第一丙阶树脂层的所述树脂成分相同组分的树脂成分；以及
所述第一丙阶树脂层具有在约30%重量百分比到约70%重量百分比之间的填料颗粒，并且其中所述第二丙阶树脂层具有在约0%重量百分比到2%重量百分比之间的填料颗粒。
CN201310384698.7A 2012-08-31 2013-08-29 管芯底部填充结构和方法 Active CN103681455B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/600,621 US8823168B2 (en) 2012-08-31 2012-08-31 Die underfill structure and method
US13/600,621 2012-08-31

Publications (2)

Publication Number Publication Date
CN103681455A true CN103681455A (zh) 2014-03-26
CN103681455B CN103681455B (zh) 2018-10-12

Family

ID=50186337

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310384698.7A Active CN103681455B (zh) 2012-08-31 2013-08-29 管芯底部填充结构和方法

Country Status (2)

Country Link
US (1) US8823168B2 (zh)
CN (1) CN103681455B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393879A (zh) * 2016-03-25 2017-11-24 格罗方德半导体公司 预涂敷底部填充物所包覆芯片上对准标记的可视化
CN107706157A (zh) * 2016-08-08 2018-02-16 株式会社藤仓 安装体以及该安装体的制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10276479B1 (en) 2017-10-11 2019-04-30 Micron Technology, Inc. Methods of processing semiconductor devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848466A (en) * 1996-11-19 1998-12-15 Motorola, Inc. Method for forming a microelectronic assembly
TW516138B (en) * 2000-08-01 2003-01-01 Nec Corp Packaging method and packaging structure of semiconductor devices
US20060200985A1 (en) * 2003-03-26 2006-09-14 Delphi Technologies, Inc. Underfill method
CN101083239A (zh) * 2006-05-31 2007-12-05 万国半导体股份有限公司 与铜焊接相容的焊接垫板结构和方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
JP3346320B2 (ja) * 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
AU2002245103A1 (en) * 2000-11-14 2002-07-30 Henkel Loctite Corporation Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith
US7498197B2 (en) * 2006-09-13 2009-03-03 Delphi Technologies, Inc. Silica nanoparticles thermoset resin compositions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848466A (en) * 1996-11-19 1998-12-15 Motorola, Inc. Method for forming a microelectronic assembly
TW516138B (en) * 2000-08-01 2003-01-01 Nec Corp Packaging method and packaging structure of semiconductor devices
US20060200985A1 (en) * 2003-03-26 2006-09-14 Delphi Technologies, Inc. Underfill method
CN101083239A (zh) * 2006-05-31 2007-12-05 万国半导体股份有限公司 与铜焊接相容的焊接垫板结构和方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393879A (zh) * 2016-03-25 2017-11-24 格罗方德半导体公司 预涂敷底部填充物所包覆芯片上对准标记的可视化
CN107393879B (zh) * 2016-03-25 2019-12-24 格罗方德半导体公司 预涂敷底部填充物所包覆芯片上对准标记的可视化
CN107706157A (zh) * 2016-08-08 2018-02-16 株式会社藤仓 安装体以及该安装体的制造方法

Also Published As

Publication number Publication date
CN103681455B (zh) 2018-10-12
US8823168B2 (en) 2014-09-02
US20140061896A1 (en) 2014-03-06

Similar Documents

Publication Publication Date Title
JP4928945B2 (ja) バンプ−オン−リードフリップチップ相互接続
US7736950B2 (en) Flip chip interconnection
EP1840952A1 (en) Devices with microjetted polymer standoffs
JP5421863B2 (ja) 半導体パッケージの製造方法
JP5018155B2 (ja) 配線基板、電子部品の実装構造、及び半導体装置
JP6004441B2 (ja) 基板接合方法、バンプ形成方法及び半導体装置
CN106537571B (zh) 半导体安装品及其制造方法
CN102215639A (zh) 半导体芯片内置配线基板及其制造方法
TW200937539A (en) Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
JP2005064362A (ja) 電子装置の製造方法及びその電子装置並びに半導体装置の製造方法
CN110473796A (zh) 用于倒装芯片封装件的多个底部填充剂
TWI736072B (zh) 封裝結構與其形成方法
JP5453678B2 (ja) 半導体パッケージおよびその製造方法
CN103681455A (zh) 管芯底部填充结构和方法
JP3972209B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
CN108231717A (zh) 一种封装元件及其制备方法
JP2012028513A (ja) 半導体装置及びその製造方法
CN108198794A (zh) 一种芯片封装体及其制备方法
JP2008218758A (ja) 電子回路実装構造体
TWI611485B (zh) 覆晶底部填充
US11482502B2 (en) Semiconductor device and semiconductor device manufacturing method
CN104465427A (zh) 封装结构及半导体工艺
JP4561969B2 (ja) 半導体装置
JP4591715B2 (ja) 半導体装置の製造方法
US20080171450A1 (en) Wafer Bump Manufacturing Using Conductive Ink

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant