CN107706157A - 安装体以及该安装体的制造方法 - Google Patents

安装体以及该安装体的制造方法 Download PDF

Info

Publication number
CN107706157A
CN107706157A CN201710659852.5A CN201710659852A CN107706157A CN 107706157 A CN107706157 A CN 107706157A CN 201710659852 A CN201710659852 A CN 201710659852A CN 107706157 A CN107706157 A CN 107706157A
Authority
CN
China
Prior art keywords
circuit board
fixing body
pillar
chip
mentioned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710659852.5A
Other languages
English (en)
Inventor
和田英之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Publication of CN107706157A publication Critical patent/CN107706157A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10155—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11515—Curing and solidification, e.g. of a photosensitive bump material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/1713—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175—Material
    • H01L2224/17505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81095—Temperature settings
    • H01L2224/81096—Transient conditions
    • H01L2224/81098—Cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明涉及安装体以及该安装体的制造方法。本发明的一方式的安装体(1)通过具有热固性的支柱(30)将IC芯片(20)固定于在线膨胀系数具有各向异性的布线基板(10)。

Description

安装体以及该安装体的制造方法
技术领域
本发明涉及在布线基板安装电子部件的安装体以及该安装体的制造方法。
背景技术
在通信装置等电子设备中，在布线基板(例如，印刷布线板)安装有各种电子部件(例如，IC芯片)的安装体(例如，印刷电路安装品)被广泛使用。作为公开了上述的安装体的文献，例如能够列举专利文献1～4。
在专利文献1中，公开了使用Au等的凸块在母体基板倒装芯片安装MMIC(monolithic microwave integrated circuit：单片微波集成电路)芯片，向MMIC芯片与母体基板之间(特别地，包围MMIC芯片的内侧的电路的绝缘体壁的外侧)填充底填料的微波/毫米波电路装置。
另外，在专利文献2中，公开了使用低熔点的焊料与高熔点的焊料双方在电路基板倒装芯片安装半导体元件，向半导体元件与电路基板之间填充具有焊剂功能的密封树脂的半导体装置。
另外，在专利文献3中，公开了向基板倒装芯片安装功率放大器用高频IC芯片，向功率放大器用高频IC芯片与基板之间填充底填料而形成的无线装置。
在专利文献4中，公开了在基板倒装芯片安装IC芯片的倒装芯片安装构造。在该倒装芯片安装构造中，为了将IC芯片保持为规定的高度，向IC芯片下的空间不卷入气泡地填充底填料，而将干漆膜的支柱配设于IC芯片与基板之间。
倒装芯片安装能够最短地连接MMIC芯片的电路并能够大致维持MMIC芯片的性能，因此作为输入输出微波带或者毫米波带的信号的MMIC芯片的安装方法被广泛使用。
专利文献1：日本特开2000-269384号公报(2000年9月29日公开)
专利文献2：日本特开2006-54360号公报(2006年2月23日公开)
专利文献3：日本特开2013-102356号公报(2013年5月23日公开)
专利文献4：日本特开2001-6805号公报(2001年3月16日公开)
然而，上述的现有技术均未考虑布线基板的线膨胀系数与安装于该布线基板的电子部件的线膨胀系数的差所引起的安装的不良情况。
以下，以在LCP(Liquid Crystal Polymer：液晶聚合物)基板安装IC芯片(Si芯片)的情况为例，对该问题具体地进行说明。LCP基板在LCP基材的表面形成布线。LCP基材是线膨胀系数具有各向异性的材料，MD(Machine direction：流动方向)方向的线膨胀系数为1ppm/K，TD(Transverse direction：垂直方向)方向的线膨胀系数为64ppm/K。另一方面，IC芯片的线膨胀系数为2.6ppm/K左右。
图8表示将IC芯片120安装于LCP基板110的方法，图8中的(a)～(d)是构成该方法的各工序中的IC芯片120以及LCP基板110的侧视图。此外，在图8中的(a)～(d)中，纸面左右方向与LCP基板110的TD方向一致。
图8中的(a)表示将IC芯片120安装于LCP基板110的状态。LCP基板110由LCP基材111、形成于LCP基材111的上表面的基板布线层112以及以覆盖基板布线层112的一部分的方式形成于LCP基材111的上表面的钝化层113构成。IC芯片120由半导体基材121、形成于半导体基材121的背面的衬垫122、连接于衬垫122的Cu柱123以及形成于Cu柱123的前端的焊料层124构成。若将IC芯片120安装于LCP基板110上，则IC芯片120的Cu柱123的前端与LCP基板110的基板布线层112的露出位置经由焊料层124接触。
然后，图8中的(b)表示为了使焊料层124融解，而在加热气氛下实施回流焊处理的状态。在加热气氛下，LCP基板110以及IC芯片120相互独立地向TD方向膨胀(伸长)(焊料层124融解，因此不存在LCP基板110促进IC芯片120的膨胀、IC芯片120阻碍LC芯片110的膨胀的情况)。LCP基板110的TD方向的线膨胀系数大于IC芯片120的线膨胀系数，因此LCP基板110的TD方向的膨胀量(伸长量)大于IC芯片120的膨胀量。
接着，图8中的(c)表示回流焊处理结束，进行了冷却的(返回常温的)状态。伴随着冷却，IC芯片120朝向中心部(图中虚线图示)收缩。另一方面，LCP基材111具有热塑性，因此维持膨胀的状态。因此，焊料层124被破坏，从而Cu柱123从基板布线层112的露出位置脱落，或者如图8中的(c)所示，LCP基板110弯曲。
然后，为了消除LCP基板110的弯曲，若对LCP基板110向图8中的(d)所示的箭头方向施加外力，则焊料层124因剪断方向的应力而被破坏，而如图8中的(e)的虚线的圆圈位置所示，致使Cu柱123从基板布线层112的露出位置脱落。
如上，在焊接连接时的加热(回流焊)工序中，IC芯片以及LCP基板分别以不同的线膨胀系数膨胀，由此存在在焊接连接产生不良情况的担忧。
此外，在图8中，示出了LCP基板110的线膨胀系数为64ppm/K的TD方向。在图8的例子中，在LCP基板110的线膨胀系数为1ppm/K的MD方向，与IC芯片120的线膨胀系数不存在显著的区别，不产生TD方向那样的不良情况。
发明内容
因此，本发明是鉴于上述的问题点而完成的，其目的在于提供一种在布线基板安装电子部件且消除了布线基板的线膨胀系数与电子部件的线膨胀系数的差所引起的安装不良情况的安装体以及安装体的制造方法。
为了解决上述的课题，本发明的一个方式涉及的安装体的特征在于，
具备布线基板以及电子部件，其中，电子部件的端子焊接于上述布线基板的布线的，
上述电子部件被由热固性树脂构成且不与上述布线以及上述端子接触的支柱固定于上述布线基板。
为了解决上述的课题，本发明的一个方式涉及的安装体的制造方法用于制造具备布线基板与电子部件的安装体，所述安装体的制造方法的特征在于，包括：
堆积工序，在该堆积工序中，在上述布线基板上将未固化状态的热固性树脂以该热固性树脂不与上述布线基板的布线接触的方式堆积成柱状，或者在上述电子部件上将未固化状态的热固性树脂以该热固性树脂不与上述电子部件的端子接触的方式堆积成柱状；
接触工序，在该接触工序中，将上述电子部件的上述端子以上述热固性树脂不与上述端子以及上述布线接触的方式经由焊料与上述布线接触；
加热工序，在该加热工序中，对上述热固性树脂以及上述焊料进行加热，由此使上述热固性树脂固化，并且使上述焊料熔融；以及
冷却工序，在该冷却工序中，对上述焊料进行冷却，由此使上述焊料固化。
根据上述的构成，能够提供一种消除了布线基板的线膨胀系数与电子部件的线膨胀系数的差所引起的安装不良情况的安装体。
附图说明
图1是表示本发明的安装体的一实施方式的构成的图，图1中的(a)是安装体的俯视图，图1中的(b)是图1中的(a)所示的剖切线A-A′的箭头方向的剖视图，图1中的(c)是图1中的(a)所示的剖切线B-B′的箭头方向的剖视图。
图2是表示图1所示的安装体的制造方法的流程图。
图3是对在图2所示的流程图中被制造的安装体的制造过程进行说明的剖视图。
图4是表示本发明的安装体的其他的实施方式的构成的图，图4中的(a)是安装体的俯视图，图4中的(b)是图4中的(a)所示的剖切线A-A′的箭头方向的剖视图，图4中的(c)是图4中的(a)所示的剖切线B-B′的箭头方向的剖视图。
图5是表示本发明的安装体的又一其他的实施方式的构成的俯视图。
图6是表示本发明的安装体的又一其他的实施方式的构成的俯视图。
图7是表示本发明的安装体的又一其他的实施方式的构成的剖视图。
图8是对以往构成进行说明的图。
具体实施方式
〔实施方式1〕
以下，使用图1～图3对本发明的安装体以及该安装体的制造方法的一实施方式进行说明。
〔安装体的构成〕
图1是表示本实施方式1的安装体1的简要结构的图，图1中的(a)是安装体1的俯视图，图1中的(b)是图1中的(a)所示的剖切线A-A′的箭头方向的剖视图，图1中的(c)是图1中的(a)所示的剖切线B-B′的箭头方向的剖视图。此外，为了便于说明，图1中的(a)局部形成透视图。
本实施方式1的安装体1具备布线基板10、IC芯片20(电子部件)以及支柱30。
布线基板10具有LCP基材11、形成于LCP基材11的上表面的基板布线层12(布线)以及以覆盖基板布线层12的一部分的方式形成于LCP基材11的上表面的钝化层13。如图1中的(a)所示，LCP基材11具备具有四边形的上表面，从其周缘部分朝向该上表面的中心部延伸配置有由基板布线层12构成的多个布线。此外，由基板布线层12构成的布线数不限定于图1的(a)所示的情况。钝化层13形成为覆盖这些各布线的中间部分，在中心部设置有开口部13a。如上形成钝化层13，从而各布线的两端分别露出，而构成连接用端子。
此处，若对LCP基材11进一步进行说明，则LCP基材11在上表面内，线膨胀系数具有各向异性。具体而言，LCP基材11的、沿着图1中的(a)所示的TD方向(第一方向)的线膨胀系数大于沿着MD方向(第二方向)的线膨胀系数。例如，对于LCP基材11而言，沿着图1中的(a)所示的TD方向的线膨胀系数为64ppm/K，沿着MD方向的线膨胀系数为1ppm/K。即，LCP基材11具有若施加热，则与MD方向相比沿着TD方向更加伸长的特性。此外，在本实施方式1中，LCP基材11呈薄片状且具有可挠性。而且，即便是在LCP基材11上形成有基板布线层12以及钝化层13的状态(换句话说，布线基板10)，也保持可挠性，另外，即便是该状态，也保持LCP基材11具有的上述的各向异性。
如图1中的(a)所示，IC芯片20具备具有四边形的上表面的半导体基材21，进一步如图1中的(b)所示，具有在作为形成于半导体基材21的背面的MMIC的(外部)端子亦即I/O衬垫22配设的Cu柱23、形成于Cu柱23的前端的焊料层24以及焊剂25。I/O衬垫22在半导体基材21的具有四边形的背面的周缘部分设置有多个(例如外围配置)，这些I/O衬垫位于布线基板10的中心部的与露出的基板布线层12的连接用端子对置的位置。
此处，以下，将IC芯片20(半导体基材21)的背面内中的、形成有I/O衬垫22的区域称为“端子形成区域”，以下，将未形成有I/O衬垫22的区域称为“端子非形成区域”。即，在本实施方式1中，IC芯片20(半导体基材21)的背面的沿着四个端边的周边部为端子形成区域，由该周边部围起的包含中心部的区域为端子非形成区域。
此外，IC芯片20的集成电路(IC)除了能够使用MMIC以外的公知的高频IC之外，也不限定于高频，还能够使用公知的IC。
支柱30是与IC芯片20的端子非形成区域和LCP基材11(布线基板10)的上表面的同该端子非形成区域对置的区域接触，并立设于该端子非形成区域与该上表面之间的柱状的构造物。更具体而言，支柱30的下端与LCP基材11的上表面的未形成有基板布线层12的中心部及其附近接触固定，并且支柱30的上端与IC芯片20的端子非形成区域接触固定。高频信号在IC芯片20的端子内传送，因此涂覆于端子周边的绝缘树脂的相对介电常数/介质损耗角正切对传送损失影响较大。因此，优选相对介电常数为大致1的大气。因此，主要在IC芯片20的中心部(即，端子非形成区域)形成支柱30，从而提高安装强度，并且不使IC端子的传送特性劣化，从而优选。
支柱30由具有热固性以及绝缘性的树脂构成。另外，是与LCP基材11以及IC芯片20的粘合性良好的树脂。具体而言，是以环氧为主要成分的绝缘树脂，使用固化温度为200℃～250℃在10秒以内固化的树脂。此外，构成支柱30的树脂也可以不具有绝缘性，但在存在对IC芯片20的电特性产生影响的担忧的情况下，优选由绝缘性的树脂构成。而且，构成支柱30的树脂如后述那样具有高触变性。而且，构成支柱30的树脂优选在加热前(热固化前)的状态下粘度为45,000～300,000Pa·s。另外，构成支柱30的热固性树脂优选伴随着热固化而收缩。
凭借上述的支柱30，LCP基材11(布线基板10)在与支柱30的下端的接触位置，在安装时的回流焊的加热工序中位置被固定。由此，在该接触位置及其周边的区域，能够抑制LCP基材11(布线基板10)的膨胀。此处，IC芯片20的线膨胀系数为2.6ppm/K左右。因此，在LCP基材11的线膨胀系数为64ppm/K的TD方向，凭借支柱30将位置固定，从而能够抑制LCP基材11向TD方向的膨胀。另一方面，在LCP基材11的线膨胀系数为1ppm/K的MD方向，IC芯片20与LCP基材11相比稍微膨胀，但线性膨胀系数的差为微差，因此难以产生膨胀量的差所引起的安装的不良情况。
另外，在本实施方式1中，如图1中的(a)所示，两个支柱30(支柱、其他的支柱)沿着TD方向排列。如上所述，对于LCP基材11的线膨胀系数而言，TD方向大于MD方向，因此在沿着该TD方向的同一线上的多个位置配设支柱30，从而能够使用有限的个数的支柱30，有效地抑制加热所引起的沿着TD方向的膨胀。
此处，将一方的支柱30与LCP基材11的接触区域的沿着TD方向(更加正确而言，为上述的同一线)的直径的长度和另一方的支柱30与LCP基材11的接触区域的沿着TD方向(更加正确而言，为上述的同一线)的直径的长度的和设为X。X是各支柱30的沿着图1中的(b)的纸面左右方向的宽度的和。另一方面，将各支柱30与LCP基材11的接触区域的每一个的沿着其他的方向的直径的长度设为Y。Y例如是图1中的(c)中沿着纸面左右方向的支柱30的宽度。在该X与Y中，X＞Y的关系成立。
如上构成支柱30，从而以沿着TD方向比较宽的宽度固定LCP基材11的位置，因此能够有效地抑制向TD方向的膨胀。
如上，根据本实施方式1，能够提供一种具备支柱30，从而能够抑制LCP基材11的向TD方向的膨胀，进而消除了LCP基材11与IC芯片20的线膨胀系数的差所引起的安装不良情况的安装体。
此外，本实施方式1的安装体1未利用底层填料对IC芯片20与LCP基材11之间的间隙进行密封。即，在IC芯片20下存在空洞(空气层)。
此外，各个支柱30是如图1中的(a)所示在俯视时具有圆形的柱状的构造物，但俯视时的形状不限定于此。
〔安装体的制造方法〕
使用图2以及图3，对具备上述的构成的安装体1的制造方法进行说明。图2是对安装体1的制造方法进行说明的流程图。图3是对安装体1的制造方法进行说明的图，图3中的(a)～(f)均是从与图1中的(b)相同的方向观察布线基板10(LCP基材11)等的剖视图。
首先，准备布线基板10(图2的步骤S10)。具体而言，在LCP基材11的上表面例如通过电镀形成构成布线部、与IC芯片侧的承接衬垫、用于与布线以及其他的基板等接合的I/O衬垫的基板布线层12(例如Cu/Ni/Au)，另外，以覆盖基板布线层12中的不与外部连接的布线部的方式在LCP基材11的上表面形成钝化层13。该状态示于图3中的(a)。
接下来，在LCP基材11(布线基板10)的上表面的未形成基板布线层12的中心部及其附近涂覆构成支柱30的树脂的加热前的未固化状态的材料，使其堆积为柱状而形成支柱前驱物31(图2的步骤S11，堆积工序)。被涂覆的树脂具有高触变性，因此若在同一位置连续或者断续地涂覆，则沿着上表面的湿展性被抑制而向与上表面垂直的方向堆积进而形成柱状的支柱前驱物31。该状态示于图3中的(b)。此外，树脂的涂覆方法除了能够采用基于分配法的涂覆之外，也可以为基于喷墨法、印刷法的涂覆。
针对IC芯片20，准备具有形成于半导体基材21的背面的MMIC(未图示)、I/O衬垫22、配设于I/O衬垫22的Cu柱23(例如高度25～50μm)以及形成于Cu柱23的前端的焊料层24(例如SnAg焊料)的图3中的(c)所示的IC芯片20(图2的步骤S20)。
接下来，在IC芯片20的焊料层24涂覆焊剂而形成焊剂25(图2的步骤S21)。该状态示于图3中的(d)。
接下来，在通过图2的步骤S11形成有柱状的支柱前驱物31的布线基板10的上表面粘接通过图2的步骤S21形成的IC芯片20(接触工序)。此时，柱状的支柱前驱物31的前端部分与IC芯片20的端子非形成区域接触。图3的(e)中示出了该状态。
接着，在加热气氛下实施回流焊(图2的步骤S12，加热工序)。在该加热气氛下，柱状的支柱前驱物31逐渐热固化而成为支柱30，并且IC芯片20的焊料层24以及焊剂25熔融，从而与布线基板10的基板布线层12的IC芯片侧衬垫电连接。此外，回流焊只要从设置布线基板10的工作台进行加热、从保持IC芯片20的工具等进行加热即可。
然后，在图2的步骤S13中，结束加热，进行冷却(返回常温)(冷却工序)。由此，IC芯片20的焊料层24以及焊剂25在与布线基板10的基板布线层12的IC芯片侧衬垫接触的状态下固化，从而IC芯片20与基板布线层12的焊接连接完成。该状态示于图3中的(f)。
根据以上的流程，完成本实施方式1的安装体1。
〔变形例1〕
在上述的实施方式1中，将薄片状的LCP基材11列举为例进行了说明，但本发明不限定于此。也能够使用刚性基板。另外，也可以为在线膨胀系数具有各向异性的液晶聚合物以外的基板(基材)。作为在线膨胀系数具有各向异性的刚性基板，存在陶瓷基板，但本发明也可以使用该陶瓷基板。另外，在线膨胀系数也可以不具有各向异性。
此处，对IC芯片(电子部件)的线膨胀系数大于布线基板的线膨胀系数，且其差比较大的情况进行说明。即便在该情况下，本发明的支柱也在焊料融解时固化，因此能够抑制IC芯片的膨胀。如上所述，IC芯片在回流焊结束后收缩而返回至回流焊前的状态或者接近该状态的状态。因此，通过支柱能够抑制IC芯片的膨胀，从而与无法通过支柱抑制膨胀的情况相比，在回流焊结束后，IC芯片的收缩的程度变小。由此，能够缩小因电子部件的收缩而在布线基板产生的翘曲。
〔变形例2〕
在上述的实施方式1中，两个支柱30相互分离，但本发明的方式不限定于此，两个支柱30也可以接触。
另外，支柱30的配设个数也不限定于两处，也可以在三处以上设置。
〔变形例3〕
在上述的实施方式1中，在图2所示的制造流程中，在LCP基材11(布线基板10)的上表面的、未形成有基板布线层12的中心部及其附近涂覆构成支柱30的树脂的未固化状态的材料而形成支柱前驱物31，但本发明不限定于此，也可以将构成支柱30的树脂的未固化状态的材料涂覆于IC芯片20的端子非形成区域而形成支柱前驱物。
〔实施方式2〕
本发明的安装体不限定于图1所示的实施方式1的安装体1的构成。例如，图1的安装体1沿着TD方向使两个支柱30并设，但取而代之，也可以为以下说明的其他的方式。
图4是表示本实施方式2的安装体2的简要结构的图，图4中的(a)是安装体1的俯视图，图4中的(b)是图4中的(a)所示的剖切线A-A′的箭头方向的剖视图，图4中的(c)是图4中的(a)所示的剖切线B-B′的箭头方向的剖视图。此外，为了便于说明，图4中的(a)局部形成透视图。另外，为了便于说明，对与在实施方式1中说明的部件具有相同的功能的部件标注相同的附图标记，并省略其说明。
如图4所示，在本实施方式2中，代替实施方式1的两个支柱30，配设一个支柱30a。
支柱30a与实施方式1的支柱30相同，是与IC芯片20的端子非形成区域和布线基板10的上表面的同该端子非形成区域对置的区域在一处接触，并立设于该端子非形成区域与该上表面之间的柱状的构造物。然而，本实施方式2的支柱30a在为呈具有沿着布线基板10(LCP基材11)的TD方向平行的长轴与沿着布线基板10(LCP基材11)的MD方向平行的短轴的椭圆形的一个支柱30a这点与实施方式1的两个支柱30不同。
即，支柱30a在与IC芯片20的布线基板10(LCP基材11)之间，如图4的(b)所示沿着TD方向(纸面左右方向)以较宽的宽度与IC芯片20以及LCP基材11接触，另一方面，如图4中的(b)所示沿着MD方向(纸面左右方向)以较窄的宽度与IC芯片20以及LCP基材11接触。
此外，支柱30a由与实施方式1的支柱30相同的树脂构成。
如上，支柱30a的与布线基板10(LCP基材11)的接触区域的沿着上述线膨胀系数较大的方向的长度较长。由此，与实施方式1相同，能够抑制布线基板10的向TD方向的膨胀。
〔实施方式3〕
本发明的安装体不限定于图1所示的实施方式1的安装体1的构成。例如，图1的安装体1沿着TD方向使两个支柱30并设，但取而代之，也可以为以下说明的其他的方式。
图5是表示本实施方式3的安装体3的简要结构的俯视图。此外，为了便于说明，图5局部形成透视图。另外，为了便于说明，对与在实施方式1中说明的部件具有相同的功能的部件标注相同的附图标记，并省略其说明。
如图5所示，在本实施方式3中，代替实施方式1的两个支柱30，配设一个支柱30b。
支柱30b与实施方式1的支柱30相同，是与IC芯片20的端子非形成区域和布线基板10的上表面的同该端子非形成区域对置的区域接触，并立设于该端子非形成区域与该上表面之间的柱状的构造物。然而，本实施方式3的支柱30b在俯视时具有十字形这点与实施方式1的两个支柱30不同。
更具体而言，本实施方式3的支柱30b的与布线基板10的上表面接触的接触面的形状呈第一长方形和第二长方形组合而得的十字形，其中，第一长方形具有与TD方向平行的长边，第二长方形具有与MD方向平行的长边且长边的长度短于第一长方形的长边的长度。此外，支柱30b由具有与实施方式1的支柱30相同的特性的树脂构成。
如上，支柱30b的与布线基板10(LCP基材11)的接触区域的沿着上述线膨胀系数较大的方向的长度最长。由此，与实施方式1相同，能够抑制布线基板10的向TD方向的膨胀。
〔实施方式4〕
本发明的安装体不限定于图1所示的实施方式1的安装体1的构成。例如，图1的安装体1沿着TD方向使两个支柱30并设，但取而代之，也可以为以下说明的其他的方式。
图6是表示本实施方式4的安装体4的简要结构的俯视图。此外，为了便于说明，图6局部形成透视图。另外，为了便于说明，对与在实施方式1中说明的部件具有相同的功能的部件标注相同的附图标记，并省略其说明。
如图6所示，在本实施方式4中，代替实施方式1的两个支柱30，配设五个支柱30c。
各支柱30c与实施方式1的支柱30相同，是与IC芯片20的端子非形成区域和布线基板10的上表面的同该端子非形成区域对置的区域接触，并立设于该端子非形成区域与该上表面之间的柱状的构造物。然而，本实施方式4的支柱30c在分散于布线基板10的上表面这点，与并设于沿着TD方向的同一线上的实施方式1的两个支柱30不同。
通过本实施方式4的支柱30c，也与实施方式1的支柱30相同，布线基板10在与支柱30c的下端的接触位置，在安装时的回流焊的加热工序中将位置固定。由此，在该接触位置及其周边的区域，能够抑制基于LCP基材11具有的线膨胀系数的膨胀。另外，即使在IC芯片20中，也起到相同的效果，在与支柱30c的上端的接触位置，在安装时的回流焊的加热工序中将位置固定，因此能够在该接触位置及其周边的区域，抑制基于IC芯片20具有的线膨胀系数的膨胀。
而且，支柱30c能够考虑配设于IC芯片20的集成电路(IC)上的功能面而任意地配置，并且在IC芯片20的下方的空间，能够避开欲形成空间的部分来配设，从而配置具有自由度。
如上，根据本实施方式4，能够实现良好的倒装芯片安装。
〔实施方式5〕
本发明的半导体装置不限定于图1所示的实施方式1的半导体装置1的构成，也可以为以下说明的其他的方式。
图7是本实施方式5的安装体5的剖视图，与图1中的(b)所示的安装体1对应。
本实施方式5的安装体5在向图1中的(b)所示的安装体1的IC芯片20与布线基板10之间填充底填料40(填充材料)这点与实施方式1的安装体1不同。
底填料40能够使用以往公知的底层填料而构成，但在IC芯片20配设有MMIC，因此优选采用寄生电容较小的底层填料。
底填料40能够在支柱30形成后形成。在形成有支柱30的时刻，IC芯片20与布线基板10的连接强度与不设置支柱30的情况相比提高，因此能够抑制从焊接连接至填充底层填料的破坏的风险。
如上，具备底填料40，从而与IC芯片的接合强度提高，进而能够提供与芯片的连接部的可靠性更加提高的安装体5。
此外，基于上述的底层填料的密封也能够应用于实施方式2～4的安装体2～4。
〔总结〕
本发明的一方式的安装体的特征在于，具备：
布线基板以及电子部件，其中，电子部件的端子焊接于上述布线基板的布线，
上述电子部件被由热固性树脂构成且不与上述布线以及上述端子接触的支柱固定于上述布线基板。
根据上述的构成，能够提供一种消除了布线基板的线膨胀系数与电子部件的线膨胀系数的差所引起的安装不良情况的安装体。
即，电子部件与布线基板由不同的材料构成，在两者之间存在线膨胀系数的差。然而，根据上述的构成，通过凭借用于锡焊的加热而固化的支柱将两者固定，从而线膨胀系数较大的一方的部件的膨胀或者收缩被线膨胀系数较小的一方的部件的膨胀或者收缩抑制。
据此，即便是布线基板的线膨胀系数大于电子部件的线膨胀系数，且在回流焊时膨胀的布线基板，支柱也在焊料融解时固化，因此能够抑制布线基板的膨胀，从而能够抑制在回流焊结束后在布线基板产生的翘曲。另外，即便是在回流焊时收缩的布线基板，支柱也在焊料融解时固化，因此能够抑制其收缩，从而能够抑制在回流焊结束后在布线基板产生的翘曲。因此，在欲附加外力而消除布线基板的翘曲时，与翘曲的程度较大的情况相比较，赋予焊接部分的应力较小即可，能够减少焊接部分被破坏的风险。
另外，本发明的一方式的安装体除了上述的构成之外，也可以构成为：
上述电子部件是在背面的周边部排列有多个端子的IC芯片，
上述支柱配置于被上述多个端子围起的区域。
根据上述的构成，能够提供一种消除了布线基板的线膨胀系数与IC芯片的线膨胀系数的差所引起的安装的不良情况的安装体。
此外，作为IC芯片，能够采用后述的MMIC芯片。
另外，本发明的一方式的安装体除了上述的构成之外，也可以构成为：
对于上述布线基板而言，与板面平行的第一方向的线膨胀系数大于与板面平行的第二方向亦即与上述第一方向不同的第二方向的线膨胀系数，
上述布线基板与上述支柱的接触面的上述第一方向的宽度大于上述第二方向的宽度。
根据上述的构成，能够使用有限的体积的支柱，有效地抑制在回流焊时可能产生的沿着布线基板的第一方向的膨胀或者收缩。
此外，上述支柱的与上述布线基板的接触面的形状，(1)可以成为具有与上述第一方向平行的长轴和与上述第二方向平行的短轴的椭圆，(2)也可以成为将第一长方形和第二长方形组合而得的十字形，其中，第一长方形具有与上述第一方向平行的长边，第二长方形具有与上述第二方向平行的长边，并且长边的长度短于上述第一长方形的长边的长度。
另外，本发明的一方式的半导体装置除了上述的构成之外，
上述电子部件也可以除了上述支柱之外，被由热固性树脂构成的其他支柱亦即不与上述布线以及上述端子接触的其他支柱固定于上述布线基板，
对于上述布线基板而言，与板面平行的第一方向的线膨胀系数大于与板面平行的第二方向亦即与上述第一方向不同的第二方向的线膨胀系数，
上述支柱与上述其他的支柱沿着上述第一方向并排。
根据上述的构成，能够使用有限的个数的支柱，有效地抑制在回流焊时可能产生的沿着布线基板的第一方向的膨胀或者收缩。
另外，本发明的一方式的安装体除了上述的构成之外，
上述布线基板也可以是具备液晶聚合物基材以及形成于上述液晶聚合物基材的表面的布线的液晶聚合物基板，
上述第一方向为上述液晶聚合物基材的TD(Transverse direction)方向，上述第二方向为上述液晶聚合物基材的MD(Machine direction)方向。
根据上述的构成，能够提供一种消除了液晶聚合物基板的线膨胀系数与电子部件的线膨胀系数的差所引起的安装不良情况的安装体。
另外，本发明的一方式的安装体除了上述的构成之外，
也可以向上述电子部件与上述布线基板之间填充树脂。
根据上述构成，通过被填充的树脂增高电子部件与布线基板的接合强度，因此能够提供进一步提高锡焊实现的连接可靠性的安装体。
另外，本发明的一方式的安装体的制造方法为具备布线基板与电子部件的安装体的制造方法，其特征在于，包含：
堆积工序，在该工序中，在上述布线基板上将未固化状态的热固性树脂以该热固性树脂不与上述布线基板的布线接触的方式堆积成柱状，或者在上述电子部件上将未固化状态的热固性树脂以该热固性树脂不与上述电子部件的端子接触的方式堆积成柱状；
接触工序，在该工序中，将上述电子部件的上述端子以上述热固性树脂不与上述端子以及上述布线接触的方式经由焊料与上述布线接触；
加热工序，在该工序中，对上述热固性树脂以及上述焊料进行加热，由此使上述热固性树脂固化，并且使上述焊料熔融；以及
冷却工序，在该工序中，对上述焊料进行冷却，由此使上述焊料固化。
根据上述的构成，能够提供消除了布线基板的线膨胀系数与电子部件的线膨胀系数的差所引起的安装不良情况的安装体。
即，电子部件与布线基板由不同的材料构成，在两者之间存在线膨胀系数的差。然而，根据上述的构成，通过凭借用于锡焊的加热而固化的支柱将两者固定，从而线膨胀系数较大的一方的部件的膨胀或者收缩被线膨胀系数较小的一方的部件的膨胀或者收缩抑制。
据此，即便是布线基板的线膨胀系数大于电子部件的线膨胀系数，且在回流焊时膨胀的布线基板，支柱也在焊料融解时固化，因此能够抑制布线基板的膨胀，从而能够抑制在回流焊结束后在布线基板产生的翘曲。另外，即便是在回流焊时收缩的布线基板，支柱也在焊料融解时固化，因此能够抑制其收缩，从而能够抑制在回流焊结束后在布线基板产生的翘曲。因此，在欲附加外力而消除布线基板的翘曲时，与翘曲的程度较大的情况相比较，赋予锡焊部分的应力较小即可，能够减少锡焊部分被破坏的风险。
本发明不限定于上述的各实施方式，能够在权利要求所示的范围内进行各种变更，将不同的实施方式所分别公开的技术手段适当地组合而得的实施方式也包含于本发明的技术范围内。
符号说明
1、2、3、4、5…安装体；10…布线基板；11…液晶聚合物基材(LCP基材)；12…基板布线层(布线)；13…钝化层；13a…开口部；20…IC芯片(电子部件)；21…半导体基材；22…I/O衬垫(端子)；23…Cu柱；24…焊料层；25…焊剂；30、30a、30b、30c…支柱；31…支柱前驱物(柱状的支承体前驱物)；40…底填料(填充材料)。

Claims (9)

1.一种安装体，其特征在于，
具备布线基板以及电子部件，其中，所述电子部件的端子焊接于所述布线基板的布线，
所述电子部件被由热固性树脂构成且不与所述布线以及所述端子接触的支柱固定于所述布线基板。
2.根据权利要求1所述的安装体，其特征在于，
所述电子部件是在背面的周边部排列有多个端子的IC芯片，
所述支柱配置于被所述多个端子围起的区域。
3.根据权利要求1所述的安装体，其特征在于，
对于所述布线基板而言，与板面平行的第一方向上的线膨胀系数大于与板面平行且与所述第一方向不同的第二方向上的线膨胀系数，
所述布线基板与所述支柱的接触面在所述第一方向上的宽度大于在所述第二方向上的宽度。
4.根据权利要求3所述的安装体，其特征在于，
所述布线基板与所述支柱的接触面的形状呈具有与所述第一方向平行的长轴和与所述第二方向平行的短轴的椭圆。
5.根据权利要求3所述的安装体，其特征在于，
所述布线基板与所述支柱的接触面的形状呈将第一长方形和第二长方形组合而得的十字形，其中，所述第一长方形具有与所述第一方向平行的长边，所述第二长方形具有与所述第二方向平行的长边且该长边的长度短于所述第一长方形的长边的长度。
6.根据权利要求1所述的安装体，其特征在于，
所述电子部件被所述支柱、以及由热固性树脂构成且不与所述布线以及所述端子接触的其他支柱固定于所述布线基板，
对于所述布线基板而言，与板面平行的第一方向上的线膨胀系数大于与板面平行且与所述第一方向不同的第二方向上的线膨胀系数，
所述支柱与所述其他支柱沿着所述第一方向并排。
7.根据权利要求3或6所述的安装体，其特征在于，
所述布线基板是具备液晶聚合物基材以及形成于所述液晶聚合物基材的表面的布线的液晶聚合物基板，
所述第一方向为所述液晶聚合物基材的TD方向，所述第二方向为所述液晶聚合物基材的MD方向。
8.根据权利要求1或2所述的安装体，其特征在于，
所述电子部件与所述布线基板之间填充有树脂。
9.一种安装体的制造方法，用于制造具备布线基板与电子部件的安装体，所述安装体的制造方法的特征在于，包括：
堆积工序，在该堆积工序中，在所述布线基板上将未固化状态的热固性树脂以该热固性树脂不与所述布线基板的布线接触的方式堆积成柱状，或者在所述电子部件上将未固化状态的热固性树脂以该热固性树脂不与所述电子部件的端子接触的方式堆积成柱状；
接触工序，在该接触工序中，将所述电子部件的所述端子以所述热固性树脂不与所述端子以及所述布线接触的方式经由焊料与所述布线接触；
加热工序，在该加热工序中，对所述热固性树脂以及所述焊料进行加热，由此使所述热固性树脂固化，并且使所述焊料熔融；以及
冷却工序，在该冷却工序中，对所述焊料进行冷却，由此使所述焊料固化。
CN201710659852.5A 2016-08-08 2017-08-04 安装体以及该安装体的制造方法 Pending CN107706157A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-155713 2016-08-08
JP2016155713A JP6753725B2 (ja) 2016-08-08 2016-08-08 実装体

Publications (1)

Publication Number Publication Date
CN107706157A true CN107706157A (zh) 2018-02-16

Family

ID=61069353

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710659852.5A Pending CN107706157A (zh) 2016-08-08 2017-08-04 安装体以及该安装体的制造方法

Country Status (3)

Country Link
US (1) US20180040525A1 (zh)
JP (1) JP6753725B2 (zh)
CN (1) CN107706157A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7293056B2 (ja) * 2019-09-12 2023-06-19 キオクシア株式会社 半導体装置およびその製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210938A (en) * 1991-08-05 1993-05-18 Rohm Co., Ltd. Method of assembling an electronic part device
JPH10112478A (ja) * 1996-10-04 1998-04-28 Denso Corp ボールグリッドアレイ半導体装置及びその実装方法
JPH11163049A (ja) * 1997-11-28 1999-06-18 Matsushita Electric Ind Co Ltd バンプ付電子部品の実装構造および実装方法
CN1271509A (zh) * 1997-10-02 2000-10-25 松下电器产业株式会社 将半导体元件安装到电路板上的方法及半导体器件
CN101366325A (zh) * 2006-09-22 2009-02-11 松下电器产业株式会社 电子部件安装结构
CN102349362A (zh) * 2009-05-19 2012-02-08 松下电器产业株式会社 电子部件安装方法和电子部件安装结构
CN102474988A (zh) * 2009-07-08 2012-05-23 松下电器产业株式会社 电子元件单元和加强粘合剂
CN103681455A (zh) * 2012-08-31 2014-03-26 德克萨斯仪器股份有限公司 管芯底部填充结构和方法
CN105206540A (zh) * 2014-06-24 2015-12-30 松下知识产权经营株式会社 电子元件安装结构体及电子元件安装结构体的制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4876120A (en) * 1987-04-21 1989-10-24 General Electric Company Tailorable multi-layer printed wiring boards of controlled coefficient of thermal expansion
JP2932840B2 (ja) * 1992-08-06 1999-08-09 日本電気株式会社 半導体素子のボンディング方法
JP3642885B2 (ja) * 1996-06-28 2005-04-27 ジャパンゴアテックス株式会社 Ｉｃチップ実装用インターポーザ及びｉｃチップパッケージ
JP3520208B2 (ja) * 1997-10-02 2004-04-19 松下電器産業株式会社 回路基板への半導体素子の装着方法、及び半導体装置
JP2000208557A (ja) * 1999-01-08 2000-07-28 Pfu Ltd 小型半導体装置および小型半導体装置の実装構造
JP2002334906A (ja) * 2001-05-09 2002-11-22 Matsushita Electric Ind Co Ltd フリップチップの実装方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210938A (en) * 1991-08-05 1993-05-18 Rohm Co., Ltd. Method of assembling an electronic part device
JPH10112478A (ja) * 1996-10-04 1998-04-28 Denso Corp ボールグリッドアレイ半導体装置及びその実装方法
CN1271509A (zh) * 1997-10-02 2000-10-25 松下电器产业株式会社 将半导体元件安装到电路板上的方法及半导体器件
JPH11163049A (ja) * 1997-11-28 1999-06-18 Matsushita Electric Ind Co Ltd バンプ付電子部品の実装構造および実装方法
CN101366325A (zh) * 2006-09-22 2009-02-11 松下电器产业株式会社 电子部件安装结构
CN102349362A (zh) * 2009-05-19 2012-02-08 松下电器产业株式会社 电子部件安装方法和电子部件安装结构
CN102474988A (zh) * 2009-07-08 2012-05-23 松下电器产业株式会社 电子元件单元和加强粘合剂
CN103681455A (zh) * 2012-08-31 2014-03-26 德克萨斯仪器股份有限公司 管芯底部填充结构和方法
CN105206540A (zh) * 2014-06-24 2015-12-30 松下知识产权经营株式会社 电子元件安装结构体及电子元件安装结构体的制造方法

Also Published As

Publication number Publication date
US20180040525A1 (en) 2018-02-08
JP6753725B2 (ja) 2020-09-09
JP2018026403A (ja) 2018-02-15

Similar Documents

Publication Publication Date Title
KR100459970B1 (ko) 반도체 장치 및 그 제조 방법과, 회로기판 및 전자기기
US6313521B1 (en) Semiconductor device and method of manufacturing the same
US7091064B2 (en) Method and apparatus for attaching microelectronic substrates and support members
TWI241675B (en) Chip carrier for semiconductor chip
US20030052156A1 (en) Hollow solder structure having improved reliability and method of manufacturing same
JP4864810B2 (ja) チップ内蔵基板の製造方法
US5661337A (en) Technique for improving bonding strength of leadframe to substrate in semiconductor IC chip packages
TW202131479A (zh) 半導體封裝體及包含半導體封裝體之裝置
US6657313B1 (en) Dielectric interposer for chip to substrate soldering
WO2000052739A2 (en) A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material
JP3243956B2 (ja) 半導体装置およびその製造方法
US20090120675A1 (en) Mounted structural body and method of manufacturing the same
CN107706157A (zh) 安装体以及该安装体的制造方法
US7129587B2 (en) Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
JP2000150560A (ja) バンプ形成方法及びバンプ形成用ボンディングツール、半導体ウエーハ、半導体チップ及び半導体装置並びにこれらの製造方法、回路基板並びに電子機器
JP4123321B2 (ja) 配線基板の接合方法
JP4018936B2 (ja) 回路モジュールの製造方法
US20050196907A1 (en) Underfill system for die-over-die arrangements
JP4318895B2 (ja) ３次元モジュール、３次元モジュールの製造方法
JPH10247706A (ja) ボールグリッドアレイパッケージ
KR100665288B1 (ko) 플립칩 패키지 제조방법
JP4591715B2 (ja) 半導体装置の製造方法
CN220254474U (zh) 一种滤波器封装结构、模组及电子产品
JPH0974149A (ja) 小型パッケージ及びその製造方法
JP2798861B2 (ja) 混成集積回路装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180216

WD01 Invention patent application deemed withdrawn after publication