SG11202104885PA - Novel 3d nand memory device and method of forming the same - Google Patents
Novel 3d nand memory device and method of forming the sameInfo
- Publication number
- SG11202104885PA SG11202104885PA SG11202104885PA SG11202104885PA SG11202104885PA SG 11202104885P A SG11202104885P A SG 11202104885PA SG 11202104885P A SG11202104885P A SG 11202104885PA SG 11202104885P A SG11202104885P A SG 11202104885PA SG 11202104885P A SG11202104885P A SG 11202104885PA
- Authority
- SG
- Singapore
- Prior art keywords
- novel
- forming
- same
- memory device
- nand memory
- Prior art date
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/119908 WO2020113578A1 (en) | 2018-12-07 | 2018-12-07 | Novel 3d nand memory device and method of forming the same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11202104885PA true SG11202104885PA (en) | 2021-06-29 |
Family
ID=66190470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11202104885PA SG11202104885PA (en) | 2018-12-07 | 2018-12-07 | Novel 3d nand memory device and method of forming the same |
Country Status (10)
Country | Link |
---|---|
US (5) | US10950623B2 (zh) |
EP (1) | EP3864700A4 (zh) |
JP (2) | JP2022513730A (zh) |
KR (2) | KR102714410B1 (zh) |
CN (2) | CN111276486B (zh) |
AU (1) | AU2018451633B2 (zh) |
BR (1) | BR112021007364B1 (zh) |
SG (1) | SG11202104885PA (zh) |
TW (1) | TWI677970B (zh) |
WO (1) | WO2020113578A1 (zh) |
Families Citing this family (54)
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KR102442933B1 (ko) * | 2017-08-21 | 2022-09-15 | 삼성전자주식회사 | 3차원 반도체 장치 |
AU2018451633B2 (en) * | 2018-12-07 | 2022-06-30 | Yangtze Memory Technologies Co., Ltd. | Novel 3D NAND memory device and method of forming the same |
KR102546653B1 (ko) | 2018-12-11 | 2023-06-22 | 삼성전자주식회사 | 콘택 플러그를 갖는 반도체 소자 |
KR102681258B1 (ko) * | 2018-12-27 | 2024-07-03 | 에스케이하이닉스 주식회사 | 복수의 채널층을 구비하는 비휘발성 메모리 장치 |
US11189635B2 (en) | 2019-04-01 | 2021-11-30 | Applied Materials, Inc. | 3D-NAND mold |
KR20210145246A (ko) | 2019-06-17 | 2021-12-01 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 슬릿 구조물의 지지 구조물을 갖는 3차원 메모리 디바이스 및 그 형성 방법 |
CN110896673B (zh) | 2019-06-17 | 2021-02-19 | 长江存储科技有限责任公司 | 用于利用支撑结构形成三维存储器件的方法和产生的三维存储器件 |
CN113745235B (zh) | 2019-06-17 | 2024-04-26 | 长江存储科技有限责任公司 | 具有在栅极线缝隙中的支撑结构的三维存储器件和用于形成其的方法 |
CN110211964B (zh) * | 2019-06-17 | 2022-03-18 | 长江存储科技有限责任公司 | 3d nand存储器及其形成方法 |
JP7279202B2 (ja) * | 2019-06-17 | 2023-05-22 | 長江存儲科技有限責任公司 | ゲート線スリットがない3次元メモリデバイスおよびそれを形成するための方法 |
WO2021035603A1 (en) | 2019-08-29 | 2021-03-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory and fabrication method thereof |
US11638377B2 (en) | 2019-09-13 | 2023-04-25 | Applied Materials, Inc. | Self-aligned select gate cut for 3D NAND |
US11450601B2 (en) * | 2019-09-18 | 2022-09-20 | Micron Technology, Inc. | Assemblies comprising memory cells and select gates |
CN111108600B (zh) * | 2019-12-24 | 2022-07-08 | 长江存储科技有限责任公司 | 三维存储器件及其形成方法 |
CN111293121B (zh) * | 2020-01-02 | 2021-08-13 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
CN111771281B (zh) | 2020-01-17 | 2021-07-20 | 长江存储科技有限责任公司 | 三维存储器件及其制作方法 |
WO2021146897A1 (en) * | 2020-01-21 | 2021-07-29 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional nand memory device and method of forming the same |
US11587796B2 (en) * | 2020-01-23 | 2023-02-21 | Applied Materials, Inc. | 3D-NAND memory cell structure |
CN111326525B (zh) * | 2020-03-13 | 2023-09-26 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
CN111527605B (zh) | 2020-03-20 | 2021-07-20 | 长江存储科技有限责任公司 | 三维存储器件及其制造方法 |
US11411020B2 (en) * | 2020-04-22 | 2022-08-09 | Macronix International Co., Ltd. | Memory device with sub-slits |
JP7317995B2 (ja) * | 2020-04-24 | 2023-07-31 | 長江存儲科技有限責任公司 | ドレイン選択ゲートカット構造を備えた三次元メモリデバイスおよびこれを形成するための方法 |
CN111540743B (zh) * | 2020-04-24 | 2021-08-13 | 长江存储科技有限责任公司 | 三维存储器件及形成方法 |
CN111819691B (zh) | 2020-05-25 | 2021-04-16 | 长江存储科技有限责任公司 | 存储器件及其形成方法 |
CN111758159B (zh) * | 2020-05-25 | 2021-04-27 | 长江存储科技有限责任公司 | 存储器件及其形成方法 |
CN114743985A (zh) | 2020-05-27 | 2022-07-12 | 长江存储科技有限责任公司 | 三维存储器件 |
EP3942612B1 (en) | 2020-05-27 | 2024-01-03 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices |
CN111801798B (zh) | 2020-05-27 | 2021-04-16 | 长江存储科技有限责任公司 | 三维存储器件 |
CN111801799B (zh) | 2020-05-27 | 2021-03-23 | 长江存储科技有限责任公司 | 用于形成三维存储器件的方法 |
CN111599819A (zh) * | 2020-05-29 | 2020-08-28 | 长江存储科技有限责任公司 | 三维存储器及其制作方法 |
CN112885839B (zh) * | 2020-06-18 | 2021-12-28 | 长江存储科技有限责任公司 | 三维存储器及制备方法、电子设备 |
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JP7532127B2 (ja) * | 2020-07-20 | 2024-08-13 | キオクシア株式会社 | 半導体記憶装置及び半導体記憶装置の製造方法 |
JP2022023663A (ja) * | 2020-07-27 | 2022-02-08 | キオクシア株式会社 | 半導体記憶装置 |
JP2022051180A (ja) * | 2020-09-18 | 2022-03-31 | キオクシア株式会社 | 半導体記憶装置 |
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TWI747638B (zh) * | 2020-12-02 | 2021-11-21 | 旺宏電子股份有限公司 | 記憶元件及其製造方法 |
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CN112992909B (zh) * | 2021-03-15 | 2021-12-17 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
CN112864170B (zh) * | 2021-03-26 | 2022-10-11 | 长江存储科技有限责任公司 | 三维存储器及其制备方法 |
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US11758717B2 (en) * | 2021-05-06 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor memory devices with one-sided staircase profiles and methods of manufacturing thereof |
CN113594174B (zh) * | 2021-08-10 | 2023-12-05 | 长江存储科技有限责任公司 | 三维存储器及其制作方法 |
TWI785804B (zh) * | 2021-09-16 | 2022-12-01 | 旺宏電子股份有限公司 | 三維and快閃記憶體元件及其製造方法 |
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CN116438935A (zh) | 2021-11-10 | 2023-07-14 | 长江存储科技有限责任公司 | 垂直存储器器件及其操作方法 |
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US12087694B2 (en) * | 2022-03-01 | 2024-09-10 | Macronix International Co., Ltd. | Memory device |
JP2024001746A (ja) * | 2022-06-22 | 2024-01-10 | キオクシア株式会社 | 半導体記憶装置 |
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TW202023030A (zh) | 2020-06-16 |
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CN109690776B (zh) | 2020-01-10 |
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AU2018451633B2 (en) | 2022-06-30 |
WO2020113578A1 (en) | 2020-06-11 |
EP3864700A1 (en) | 2021-08-18 |
CN111276486B (zh) | 2021-03-12 |
US20220328523A1 (en) | 2022-10-13 |
US11404441B2 (en) | 2022-08-02 |
EP3864700A4 (en) | 2022-05-04 |
US10950623B2 (en) | 2021-03-16 |
BR112021007364B1 (pt) | 2024-01-30 |
US11825656B2 (en) | 2023-11-21 |
TWI677970B (zh) | 2019-11-21 |
US20200185408A1 (en) | 2020-06-11 |
CN111276486A (zh) | 2020-06-12 |
JP2023112004A (ja) | 2023-08-10 |
BR112021007364A2 (pt) | 2021-07-20 |
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