KR920704334A - 박막 실리콘-위-절연체 층의 제조방법 - Google Patents

박막 실리콘-위-절연체 층의 제조방법

Info

Publication number
KR920704334A
KR920704334A KR1019920700715A KR920700715A KR920704334A KR 920704334 A KR920704334 A KR 920704334A KR 1019920700715 A KR1019920700715 A KR 1019920700715A KR 920700715 A KR920700715 A KR 920700715A KR 920704334 A KR920704334 A KR 920704334A
Authority
KR
South Korea
Prior art keywords
silicon
layer
corrosion
forming
stopping
Prior art date
Application number
KR1019920700715A
Other languages
English (en)
Other versions
KR950006967B1 (ko
Inventor
제이. 고드베이 데이비드
엘. 휴즈 해롤드
제이. 쿠브 프랑시스
Original Assignee
원본미기재
해군성 장관에 의하여 대표되는 미합중국
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 원본미기재, 해군성 장관에 의하여 대표되는 미합중국 filed Critical 원본미기재
Publication of KR920704334A publication Critical patent/KR920704334A/ko
Application granted granted Critical
Publication of KR950006967B1 publication Critical patent/KR950006967B1/ko

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

내용 없음.

Description

박막 실리콘-위-절연체 층의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 시드 웨이퍼(seed wafer)의 예시도,
제2도는 핸들 웨이퍼(handle wafer)의 예시도,
제3도는 함께 결합된 시드 및 핸들 웨이퍼의 예시도,
제4도는 래칭 및 플리싱 과정이 끝난 이후의 제3도의 구조 예시도,
제5도는 실리콘-게르마늄 합금층에 선택적으로 에칭이 된 후에 제4도의 구조 예시도.

Claims (20)

  1. 연속적으로 형성된 반도체 구조상에 박막 반도체 층을 형성하는 방법에 있어서, 하나 또는 그 이상의 실리콘 기판을 선택하고, 상기 하나 또는 그 이상의 실리콘 기판중 적어도 하나의 위에 실리콘과 4족원소의 합금으로 된 부식-중지층을 형성하며, 그 부식-중지층 위에 실리콘 캡층을 형성하고, 그 실리콘 캡층을 기계적 기판 위에 부착하며, 상기 실리콘 캡층의 하부를 제외한 상기 하나 또는 그 이상의 실리콘 기판중 적어도 하나 및 상기 부식-중지층을 제거하여 상기 기계적 기판위에 남아있는 상기 실리콘 캡층의 하부부분에 의해 박막 실리콘층을 형성하는 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  2. 제1항에 있어서, 상기 부식-중지층이, 실리콘-주석 합금인 것을 특징으로 하는 박막 실리콘-위-절연체층의 형성방법.
  3. 제1항에 있어서, 상기 부식-중지층이, 실리콘-납 합금인 것을 특징으로 하는 박막 실리콘-위-절연체층의 형성방법.
  4. 제1항에 있어서, 상기 부식-중지층이, 실리콘-게르마늄 합금인 것을 특징으로 하는 박막 실리콘-위-절연체의 형성방법. 연속적으로 형성된
  5. 제4항에 있어서, 상기 실리콘-게르마늄 합금이, Si1,xGex의 합성물(여기서, x=0.1-0.5)인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  6. 제1항에 있어서, 상기 부식-중지층을 형성하는 단계가 실리콘과 다른 4족원소로 이루어진 합금층을 증착하는 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  7. 제6항에 있어서, 상기 합금이 실리콘-게르마늄 합금인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  8. 제6항에 있어서, 합금이 실리콘-주석 합금인 것을 특징으로 하는 박막 실리콘-위-절연체층의 형성방법.
  9. 제6항에 있어서, 상기 합금이 실리콘-납 합금인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  10. 제1항에 있어서, 상기 실리콘 캡층을 기계적 기판위에 부착하는 단계는, 상기 실리콘 캡층의 노출된 표면에 실리콘 산화물층을 형성하고, 상기 기계적 기판의 노출된 표면에 실리콘 산화물층을 형성하며, 상기 실리콘 산화물층을 서로 접촉시킨 상태에서 상기 실리콘 산화물 층을 가열하여 서로 결합시키도록 하는 것을 특징으로 하는
  11. 제1항에 있어서, 상기 실리콘 캡층을 기계적 기판위에 부착하는 단계는, 상기 실리콘 캡층의 노출된 표면에 실리콘 산화물층을 형성하고, 그 실리콘 산화물층과 상기 기계적 기판을 접촉시킨 상태에서 상기 실리콘 산화물 층과 기계적 기판을 가열하여 서로 결합시키도록 하는 것을 특징으로 하는 박막 실리콘-위-절연체층의 형성 방법.
  12. 제1항에 있어서, 상기 실리콘 캡층을 기계적 기판위에 부착하는 단계는, 상기 기계적 기판의 노출된 표면에 실리콘 산화물층을 형성하고, 그 실리콘 산화물층과 상기 실리콘 캡층을 접촉시킨 상태에서 상기 실리콘 산화물 층과 상기 실리콘 캡층을 가열하여 서로 결합시키도록 하는 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  13. 제1항에 있어서, 상기 하나 또는 그이상의 실리콘 기판중 적어도 하나의 상기 부식-중지층을 제거하는 단계는, 상기 하나 또는 그이상의 실리콘 기판중 적어도 하나를 기계적으로 제거하고, 선택적 부식액에 의해 상기 부식-중지층의 일부분 및 상기 하나 또는 그이상의 실리콘 기판중 적어도 하나의 남아있는 부분을 선택적으로 부식시키며, 상기 부식-중지층을 선택적으로 제거하는 제2부식액에 의해 상기 부식-중지층의 남아있는 부분을 부식시키는 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  14. 제1항에 있어서, 상기 하나 또는 그이상의 기판이 적어도 첫번째와 두번째 기판이고, 그 첫번째 기판을 적어도 상기 하나 또는 그이상의 실리콘 기판중의 하나이고, 상기 부식-중지층이 첫번째 부식-중지층이고, 상기 실리콘 캡층이 첫번째 실리콘 캡층이고, 박막 반도체층의 형성방법이, 상기 두번째 실리콘 기판위에 실리콘-게르마늄 합금으로 된 부가적인 부식-중지층을 형성하고, 그 부가적인 부식-중지층 위에 부가적인 실리콘 캡층을 형성하며, 상기 첫번째 실리콘 기판에 대해 반대측의 상기 기계적 기판의 상기 두번째 실리콘 기판을 결합하고, 상기 첫번째 및 두번째 실리콘 캡층의 하부를 제거하지 않고 상기 첫번째 및 두번재 기판과 상기 변형된 첫번째 및 두번째 부식-중지층을 제거하여 상기 기계적 기판의 양표면에 남아있는 상기 실리콘 캡층의 하부 부분에 의해 박막 반도체 층을 형성하는 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  15. 제1항에 있어서, 상기 부식-중지층을 형성하는 단계는, 상기 실리콘 층안에 실리콘이외의 4족이온을 주입하여 실리콘-4족 합금 매입층을 형성하는 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  16. 제15항에 있어서, 상기 매입층은, 주석이온을 주입하여 그 매입층이 실리콘-주석 합금인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  17. 제15항에 있어서, 상기 매입층은, 납 이온을 주입하여 그 매입층이 실리콘-납 합금인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  18. 제15항에 있어서, 상기 매입층은, 게르마늄이온을 주입하여 그 매입층이 실리콘-게르마늄 합금인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  19. 제1항에 있어서, 상기 부식-중지층이 첫번째 부식-중지층이고, 그 부식-중지층의 형성단계는, 상기 첫번째 부식-중지층에 공간층(Spacer Layer)을 형성하고, 그 공간층위에 실리콘-게르마늄 합금이 포함된 두번째 부식-중지층을 형성하며, 그 두번째 부식-중지층위에 실리콘 캡층을 형성하는 단계이고, 상기 제거단계는, 상기 실리콘 캡층의 하부부분을 제거하지 않고 상기 첫번째 및 두번째 부식-중지층과 상기 실리콘 기판을 제거하는 단계인 것을 특징으로 하는 박막 실리콘-위-절연체 층의 형성방법.
  20. 제19항에 있어서, 상기 이온은, 게르마늄이온으로 매입층이 실리콘-게르마늄 합금인 것을 특징으로 하는 연속적으로 박막 실리콘-위-절연체 층의 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920700715A 1989-09-29 1990-09-28 박막 실리콘-위-절연체 층의 제조방법 KR950006967B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US414,225 1989-09-29
US414225 1989-09-29
US07/414,225 US5013681A (en) 1989-09-29 1989-09-29 Method of producing a thin silicon-on-insulator layer
PCT/US1990/005432 WO1991005366A1 (en) 1989-09-29 1990-09-28 Method of producing a thin silicon-on-insulator layer

Publications (2)

Publication Number Publication Date
KR920704334A true KR920704334A (ko) 1992-12-19
KR950006967B1 KR950006967B1 (ko) 1995-06-26

Family

ID=23640518

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920700715A KR950006967B1 (ko) 1989-09-29 1990-09-28 박막 실리콘-위-절연체 층의 제조방법

Country Status (6)

Country Link
US (1) US5013681A (ko)
EP (1) EP0493503A1 (ko)
JP (1) JP2684455B2 (ko)
KR (1) KR950006967B1 (ko)
CA (1) CA2066193C (ko)
WO (1) WO1991005366A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030058571A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 반도체소자의 제조방법

Families Citing this family (210)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2640428B1 (fr) * 1988-12-09 1992-10-30 Thomson Csf Procede de durcissement vis-a-vis des rayonnements ionisants de composants electroniques actifs, et composants durcis de grandes dimensions
US5213993A (en) * 1989-09-13 1993-05-25 Kabushiki Kaisha Tobisha Method of manufacturing semiconductor substrate dielectric isolating structure
US5141887A (en) * 1990-07-02 1992-08-25 Motorola, Inc. Low voltage, deep junction device and method
US5212397A (en) * 1990-08-13 1993-05-18 Motorola, Inc. BiCMOS device having an SOI substrate and process for making the same
US5248621A (en) * 1990-10-23 1993-09-28 Canon Kabushiki Kaisha Method for producing solar cell devices of crystalline material
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
US5110748A (en) * 1991-03-28 1992-05-05 Honeywell Inc. Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations
JPH07187892A (ja) * 1991-06-28 1995-07-25 Internatl Business Mach Corp <Ibm> シリコン及びその形成方法
TW211621B (ko) * 1991-07-31 1993-08-21 Canon Kk
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
EP0536790B1 (en) * 1991-10-11 2004-03-03 Canon Kabushiki Kaisha Method for producing semiconductor articles
EP0537677B1 (en) * 1991-10-16 1998-08-19 Sony Corporation Method of forming an SOI structure with a DRAM
JP2602597B2 (ja) * 1991-12-27 1997-04-23 信越半導体株式会社 薄膜ｓｏｉ基板の製造方法
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JP3250673B2 (ja) * 1992-01-31 2002-01-28 キヤノン株式会社 半導体素子基体とその作製方法
JPH05217824A (ja) * 1992-01-31 1993-08-27 Canon Inc 半導体ウエハ及びその製造方法
JP3261685B2 (ja) 1992-01-31 2002-03-04 キヤノン株式会社 半導体素子基体及びその作製方法
DE69331816T2 (de) * 1992-01-31 2002-08-29 Canon Kk Verfahren zur Herstellung eines Halbleitersubstrats
KR100289348B1 (ko) * 1992-05-25 2001-12-28 이데이 노부유끼 절연기판실리콘반도체장치와그제조방법
US5227313A (en) * 1992-07-24 1993-07-13 Eastman Kodak Company Process for making backside illuminated image sensors
US5244817A (en) * 1992-08-03 1993-09-14 Eastman Kodak Company Method of making backside illuminated image sensors
US5268326A (en) * 1992-09-28 1993-12-07 Motorola, Inc. Method of making dielectric and conductive isolated island
US5270221A (en) * 1992-11-05 1993-12-14 Hughes Aircraft Company Method of fabricating high quantum efficiency solid state sensors
JP2908150B2 (ja) * 1992-11-27 1999-06-21 日本電気株式会社 Ｓｏｉ基板構造及びその製造方法
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US5264395A (en) * 1992-12-16 1993-11-23 International Business Machines Corporation Thin SOI layer for fully depleted field effect transistors
US5258323A (en) * 1992-12-29 1993-11-02 Honeywell Inc. Single crystal silicon on quartz
US5455202A (en) * 1993-01-19 1995-10-03 Hughes Aircraft Company Method of making a microelectric device using an alternate substrate
US5380669A (en) * 1993-02-08 1995-01-10 Santa Barbara Research Center Method of fabricating a two-color detector using LPE crystal growth
GB9305448D0 (en) * 1993-03-17 1993-05-05 British Tech Group Semiconductor structure and method of manufacturing same
US5344524A (en) * 1993-06-30 1994-09-06 Honeywell Inc. SOI substrate fabrication
US5413679A (en) * 1993-06-30 1995-05-09 The United States Of America As Represented By The Secretary Of The Navy Method of producing a silicon membrane using a silicon alloy etch stop layer
US5310451A (en) * 1993-08-19 1994-05-10 International Business Machines Corporation Method of forming an ultra-uniform silicon-on-insulator layer
US6004865A (en) * 1993-09-06 1999-12-21 Hitachi, Ltd. Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator
US5395481A (en) * 1993-10-18 1995-03-07 Regents Of The University Of California Method for forming silicon on a glass substrate
US5488012A (en) * 1993-10-18 1996-01-30 The Regents Of The University Of California Silicon on insulator with active buried regions
US5414276A (en) * 1993-10-18 1995-05-09 The Regents Of The University Of California Transistors using crystalline silicon devices on glass
US5399231A (en) * 1993-10-18 1995-03-21 Regents Of The University Of California Method of forming crystalline silicon devices on glass
US5360752A (en) * 1993-10-28 1994-11-01 Loral Federal Systems Company Method to radiation harden the buried oxide in silicon-on-insulator structures
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
JPH1027893A (ja) * 1993-10-29 1998-01-27 Amer Fib Inc 電荷シンク又は電位ウェルとして設けられた絶縁層の下の基板内に電気的に結合され別に形成されたドープされた領域を有するｓｏｉウエーハ上に設けられた集積回路（ｉｃ）装置
JP2980497B2 (ja) * 1993-11-15 1999-11-22 株式会社東芝 誘電体分離型バイポーラトランジスタの製造方法
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
US5468674A (en) * 1994-06-08 1995-11-21 The United States Of America As Represented By The Secretary Of The Navy Method for forming low and high minority carrier lifetime layers in a single semiconductor structure
JPH0831791A (ja) * 1994-07-11 1996-02-02 Mitsubishi Electric Corp 半導体層の製造方法
US5455193A (en) * 1994-11-17 1995-10-03 Philips Electronics North America Corporation Method of forming a silicon-on-insulator (SOI) material having a high degree of thickness uniformity
JP3265493B2 (ja) * 1994-11-24 2002-03-11 ソニー株式会社 Ｓｏｉ基板の製造方法
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US6277696B1 (en) * 1995-06-27 2001-08-21 Hewlett-Packard Company Surface emitting laser using two wafer bonded mirrors
US5985728A (en) * 1995-09-01 1999-11-16 Elantec Semiconductor, Inc. Silicon on insulator process with recovery of a device layer from an etch stop layer
US5792678A (en) * 1996-05-02 1998-08-11 Motorola, Inc. Method for fabricating a semiconductor on insulator device
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US5793913A (en) * 1996-07-10 1998-08-11 Northern Telecom Limited Method for the hybrid integration of discrete elements on a semiconductor substrate
US5773326A (en) * 1996-09-19 1998-06-30 Motorola, Inc. Method of making an SOI integrated circuit with ESD protection
WO1998042010A1 (en) * 1997-03-17 1998-09-24 Genus, Inc. Bonded soi wafers using high energy implant
US6391744B1 (en) 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
ATE283549T1 (de) * 1997-06-24 2004-12-15 Massachusetts Inst Technology Kontrolle der verspannungsdichte durch verwendung von gradientenschichten und durch planarisierung
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US6027956A (en) * 1998-02-05 2000-02-22 Integration Associates, Inc. Process for producing planar dielectrically isolated high speed pin photodiode
US6548878B1 (en) 1998-02-05 2003-04-15 Integration Associates, Inc. Method for producing a thin distributed photodiode structure
US6303967B1 (en) 1998-02-05 2001-10-16 Integration Associates, Inc. Process for producing an isolated planar high speed pin photodiode
US6458619B1 (en) 1998-02-05 2002-10-01 Integration Associates, Inc. Process for producing an isolated planar high speed pin photodiode with improved capacitance
US6753586B1 (en) 1998-03-09 2004-06-22 Integration Associates Inc. Distributed photodiode structure having majority dopant gradient and method for making same
US7227176B2 (en) * 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6689211B1 (en) 1999-04-09 2004-02-10 Massachusetts Institute Of Technology Etch stop layer system
WO1999053539A1 (en) 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Silicon-germanium etch stop layer system
US6207530B1 (en) 1998-06-19 2001-03-27 International Business Machines Corporation Dual gate FET and process
JP2000173976A (ja) * 1998-12-02 2000-06-23 Mitsubishi Electric Corp 半導体装置の製造方法
US6890827B1 (en) * 1999-01-13 2005-05-10 Agere Systems Inc. Method of fabricating a silicon on insulator transistor structure for imbedded DRAM
US20040175901A1 (en) * 1999-02-10 2004-09-09 Commissariat A L'energie Atomique Method for forming an optical silicon layer on a support and use of said method in the production of optical components
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US6277666B1 (en) 1999-06-24 2001-08-21 Honeywell Inc. Precisely defined microelectromechanical structures and associated fabrication methods
JP2001036054A (ja) * 1999-07-19 2001-02-09 Mitsubishi Electric Corp Ｓｏｉ基板の製造方法
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6690078B1 (en) 1999-08-05 2004-02-10 Integration Associates, Inc. Shielded planar dielectrically isolated high speed pin photodiode and method for producing same
US6242324B1 (en) * 1999-08-10 2001-06-05 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating singe crystal materials over CMOS devices
US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6503773B2 (en) * 2000-01-20 2003-01-07 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
WO2001099169A2 (en) * 2000-06-22 2001-12-27 Massachusetts Institute Of Technology Etch stop layer system for sige devices
EP1350290B1 (en) * 2000-08-04 2006-11-22 Amberwave Systems Corporation Silicon wafer with embedded optoelectronic material for monolithic oeic
DE60125952T2 (de) * 2000-08-16 2007-08-02 Massachusetts Institute Of Technology, Cambridge Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6808956B2 (en) 2000-12-27 2004-10-26 Honeywell International Inc. Thin micromachined structures
US6582985B2 (en) * 2000-12-27 2003-06-24 Honeywell International Inc. SOI/glass process for forming thin silicon micromachined structures
US6497763B2 (en) * 2001-01-19 2002-12-24 The United States Of America As Represented By The Secretary Of The Navy Electronic device with composite substrate
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002082514A1 (en) 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US7238622B2 (en) * 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
US7019339B2 (en) 2001-04-17 2006-03-28 California Institute Of Technology Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
KR100456526B1 (ko) * 2001-05-22 2004-11-09 삼성전자주식회사 식각저지막을 갖는 에스오아이 기판, 그 제조방법, 그위에 제작된 에스오아이 집적회로 및 그것을 사용하여에스오아이 집적회로를 제조하는 방법
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
AU2002349881A1 (en) 2001-09-21 2003-04-01 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
JP2003168789A (ja) * 2001-11-29 2003-06-13 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
US6559058B1 (en) * 2002-01-31 2003-05-06 The Regents Of The University Of California Method of fabricating three-dimensional components using endpoint detection
US7202139B2 (en) * 2002-02-07 2007-04-10 Taiwan Semiconductor Manufacturing Company , Ltd. MOSFET device with a strained channel
JP2003249641A (ja) * 2002-02-22 2003-09-05 Sharp Corp 半導体基板、その製造方法及び半導体装置
US7060632B2 (en) 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
WO2003105189A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7615829B2 (en) * 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
EP2267762A3 (en) 2002-08-23 2012-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7067015B2 (en) * 2002-10-31 2006-06-27 Texas Instruments Incorporated Modified clean chemistry and megasonic nozzle for removing backside CMP slurries
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2848725B1 (fr) * 2002-12-17 2005-02-11 Commissariat Energie Atomique Procede de formation de motifs alignes de part et d'autre d'un film mince
EP2337062A3 (en) * 2003-01-27 2016-05-04 Taiwan Semiconductor Manufacturing Company, Limited Method for making semiconductor structures with structural homogeneity
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
EP1602125B1 (en) 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation process
US6949451B2 (en) * 2003-03-10 2005-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. SOI chip with recess-resistant buried insulator and method of manufacturing the same
US6902962B2 (en) * 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US6864149B2 (en) 2003-05-09 2005-03-08 Taiwan Semiconductor Manufacturing Company SOI chip with mesa isolation and recess resistant regions
FR2856844B1 (fr) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
WO2005104192A2 (en) * 2004-04-21 2005-11-03 California Institute Of Technology A METHOD FOR THE FABRICATION OF GaAs/Si AND RELATED WAFER BONDED VIRTUAL SUBSTRATES
US20060021565A1 (en) * 2004-07-30 2006-02-02 Aonex Technologies, Inc. GaInP / GaAs / Si triple junction solar cell enabled by wafer bonding and layer transfer
US7560361B2 (en) * 2004-08-12 2009-07-14 International Business Machines Corporation Method of forming gate stack for semiconductor electronic device
JP4617820B2 (ja) * 2004-10-20 2011-01-26 信越半導体株式会社 半導体ウェーハの製造方法
US7846759B2 (en) * 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
KR100601976B1 (ko) * 2004-12-08 2006-07-18 삼성전자주식회사 스트레인 실리콘 온 인슐레이터 구조체 및 그 제조방법
US7262087B2 (en) * 2004-12-14 2007-08-28 International Business Machines Corporation Dual stressed SOI substrates
DE102004060364A1 (de) * 2004-12-15 2006-06-29 Austriamicrosystems Ag Halbleitersubstrat mit Mehrschichtaufbau und Verfahren zur Herstellung
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
TW200707799A (en) * 2005-04-21 2007-02-16 Aonex Technologies Inc Bonded intermediate substrate and method of making same
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7544964B2 (en) * 2005-12-01 2009-06-09 National Institute Of Information And Communications Technology, Incorporated Administrative Agency Method for fabricating thin layer device
KR101319468B1 (ko) * 2005-12-02 2013-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치의 제조방법
JP5064695B2 (ja) * 2006-02-16 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
JP2008034411A (ja) * 2006-07-26 2008-02-14 Toshiba Corp 窒化物半導体素子
US7361574B1 (en) * 2006-11-17 2008-04-22 Sharp Laboratories Of America, Inc Single-crystal silicon-on-glass from film transfer
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
DE102007010913A1 (de) * 2007-03-05 2008-09-11 Endress + Hauser Gmbh + Co. Kg Drucksensor
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US9034637B2 (en) * 2007-04-25 2015-05-19 Nxp, B.V. Apparatus and method for molecule detection using nanopores
KR101495153B1 (ko) * 2007-06-01 2015-02-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 제작 방법 및 반도체장치
CN101743616B (zh) * 2007-06-28 2012-02-22 株式会社半导体能源研究所 半导体装置的制造方法
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2925221B1 (fr) * 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
EP2333824B1 (en) 2009-12-11 2014-04-16 Soitec Manufacture of thin SOI devices
RU2461090C1 (ru) * 2010-12-23 2012-09-10 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления полупроводниковой структуры
US8486814B2 (en) 2011-07-21 2013-07-16 International Business Machines Corporation Wafer backside defectivity clean-up utilizing selective removal of substrate material
JP6082385B2 (ja) * 2012-03-23 2017-02-15 Hoya株式会社 多層反射膜付き基板、ｅｕｖリソグラフィー用反射型マスクブランク、ｅｕｖリソグラフィー用反射型マスクの製造方法、及び半導体装置の製造方法
US9082684B2 (en) 2012-04-02 2015-07-14 Applied Materials, Inc. Method of epitaxial doped germanium tin alloy formation
FR2993703A1 (fr) * 2012-07-23 2014-01-24 Soitec Silicon On Insulator Procede de transfert d'une couche de semi-conducteur
US8686571B2 (en) * 2012-08-09 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding layer structure and method for wafer to wafer bonding
WO2014178421A1 (ja) * 2013-05-02 2014-11-06 富士フイルム株式会社 エッチング液およびエッチング液のキット、これをもちいたエッチング方法および半導体基板製品の製造方法
JP6223756B2 (ja) * 2013-09-10 2017-11-01 Hoya株式会社 多層反射膜付き基板、ｅｕｖリソグラフィー用反射型マスクブランク、ｅｕｖリソグラフィー用反射型マスク及びその製造方法、並びに半導体装置の製造方法
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US11049797B2 (en) * 2016-04-15 2021-06-29 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
SG11201901196RA (en) 2016-08-12 2019-03-28 Qorvo Us Inc Wafer-level package with enhanced performance
JP7035014B2 (ja) 2016-08-12 2022-03-14 コーボ ユーエス，インコーポレイティド 性能が強化されたウェハレベルパッケージ
SG11201901194SA (en) 2016-08-12 2019-03-28 Qorvo Us Inc Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10840080B2 (en) * 2017-09-20 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming SOI substrates
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10395974B1 (en) 2018-04-25 2019-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a thin semiconductor-on-insulator (SOI) substrate
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
WO2020009759A1 (en) * 2018-07-02 2020-01-09 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US10658474B2 (en) * 2018-08-14 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming thin semiconductor-on-insulator (SOI) substrates
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
KR20210129656A (ko) * 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US11387157B2 (en) * 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235066A1 (en) * 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US11456204B1 (en) * 2021-04-04 2022-09-27 Alexander Yuri Usenko Silicon-on-insulator wafer and low temperature method to make thereof
US20230026052A1 (en) * 2021-07-22 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition bonding layer for joining two semiconductor devices
FR3125631A1 (fr) 2021-07-23 2023-01-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d’un substrat semi-conducteur sur isolant de type soi ou sigeoi par besoi et structure pour fabriquer un tel substrat

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3721588A (en) * 1971-08-13 1973-03-20 Motorola Inc Thin single crystal silicon on an insulating substrate and improved dielectric isolation processing method
US3959045A (en) * 1974-11-18 1976-05-25 Varian Associates Process for making III-V devices
US3997381A (en) * 1975-01-10 1976-12-14 Intel Corporation Method of manufacture of an epitaxial semiconductor layer on an insulating substrate
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment
US4116751A (en) * 1975-10-08 1978-09-26 Solomon Zaromb Methods and apparatus for producing unsupported monocrystalline films of silicon and of other materials
US4142925A (en) * 1978-04-13 1979-03-06 The United States Of America As Represented By The Secretary Of The Army Method of making silicon-insulator-polysilicon infrared image device utilizing epitaxial deposition and selective etching
GB1602498A (en) * 1978-05-31 1981-11-11 Secr Defence Fet devices and their fabrication
US4255208A (en) * 1979-05-25 1981-03-10 Ramot University Authority For Applied Research And Industrial Development Ltd. Method of producing monocrystalline semiconductor films utilizing an intermediate water dissolvable salt layer
US4226649A (en) * 1979-09-11 1980-10-07 The United States Of America As Represented By The Secretary Of The Navy Method for epitaxial growth of GaAs films and devices configuration independent of GaAs substrate utilizing molecular beam epitaxy and substrate removal techniques
US4230505A (en) * 1979-10-09 1980-10-28 Rca Corporation Method of making an impatt diode utilizing a combination of epitaxial deposition, ion implantation and substrate removal
US4292730A (en) * 1980-03-12 1981-10-06 Harris Corporation Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization
JPS58200525A (ja) * 1982-05-18 1983-11-22 Nec Corp 半導体装置用基板の製造方法
US4599792A (en) * 1984-06-15 1986-07-15 International Business Machines Corporation Buried field shield for an integrated circuit
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element
DE3425063A1 (de) * 1984-07-07 1986-02-06 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Maske fuer die roentgenlithographie
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPH0669085B2 (ja) * 1986-09-05 1994-08-31 富士通株式会社 半導体基板の製造方法
US4875086A (en) * 1987-05-22 1989-10-17 Texas Instruments Incorporated Silicon-on-insulator integrated circuits and method
DE3718683A1 (de) * 1987-06-04 1988-12-22 Licentia Gmbh Verfahren zum herstellen eines beidseitig kontaktierbaren halbleiterbauelements
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
JP2699359B2 (ja) * 1987-11-20 1998-01-19 ソニー株式会社 半導体基板の製造方法
JPH01226167A (ja) * 1988-03-07 1989-09-08 Seiko Epson Corp 半導体装置基板の製造方法
US4855075A (en) * 1988-03-14 1989-08-08 Sandoz Ltd. Ethoxylates of alkyl and alkenyl catechols
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030058571A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 반도체소자의 제조방법

Also Published As

Publication number Publication date
US5013681A (en) 1991-05-07
KR950006967B1 (ko) 1995-06-26
CA2066193A1 (en) 1991-03-30
WO1991005366A1 (en) 1991-04-18
EP0493503A1 (en) 1992-07-08
EP0493503A4 (ko) 1994-01-19
JPH04506587A (ja) 1992-11-12
JP2684455B2 (ja) 1997-12-03
CA2066193C (en) 1993-10-12

Similar Documents

Publication Publication Date Title
KR920704334A (ko) 박막 실리콘-위-절연체 층의 제조방법
JPH0254532A (ja) Ｓｏｉ基板の製造方法
US4684435A (en) Method of manufacturing thin film transistor
KR960002872A (ko) Soi 기판 및 그 제조 방법
JPS5516464A (en) Method of forming wafer for semiconductor device
JPS6482620A (en) Manufacture of semiconductor device
ATE19712T1 (de) Verfahren zum herstellen einer isolierschicht zwischen metallisierungsebenen von integrierten halbleiterschaltungen.
JPS57155765A (en) Manufacture of semiconductor device
JPS61133641A (ja) 半導体装置の製造方法
KR840005930A (ko) 반도체 장치(半導體裝置)
JPS575372A (en) Thin film diode and manufacture thereof
JPS6459940A (en) Manufacture of semiconductor device
JPS62113483A (ja) 薄膜太陽電池
JPH071791B2 (ja) 半導体基板の製造方法
JPS55120180A (en) Fabricating method of photovoltaic device
EP0726594A3 (en) Semiconductor device and method of manufacturing the same
KR20000002807A (ko) 박막 트랜지스터의 제조방법
TW344108B (en) A bipolar transistor and method of manufacturing thereof
KR950021090A (ko) 반도체 소자의 콘택홀 형성방법
JPS5789242A (en) Fabrication of semiconductor device
KR830008393A (ko) 반도체기판의 제조방법
EP0228183A3 (en) Method for manufacturing semiconductor device
CA2014048A1 (en) Semiconductor device isolation
JPS55145356A (en) Fabricating method of semiconductor device
JPS5792872A (en) Diode

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20000506

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee