SG11201901196RA - Wafer-level package with enhanced performance - Google Patents

Wafer-level package with enhanced performance

Info

Publication number
SG11201901196RA
SG11201901196RA SG11201901196RA SG11201901196RA SG11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA
Authority
SG
Singapore
Prior art keywords
international
redistribution
thinned die
mold compound
north carolina
Prior art date
Application number
SG11201901196RA
Inventor
Jan Vandemeer
Jonathan Hammond
Julio Costa
Original Assignee
Qorvo Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US201662374447P priority Critical
Application filed by Qorvo Us Inc filed Critical Qorvo Us Inc
Priority to PCT/US2017/046779 priority patent/WO2018031999A1/en
Publication of SG11201901196RA publication Critical patent/SG11201901196RA/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00777Preserve existing structures from alteration, e.g. temporary protection during manufacturing
    • B81C1/00785Avoid chemical alteration, e.g. contamination, oxidation or unwanted etching
    • B81C1/00801Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0009Structural features, others than packages, for protecting a device against environmental influences
    • B81B7/0025Protection against chemical alteration
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/007Interconnections between the MEMS and external electrical signals
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023Packaging together an electronic processing unit die and a micromechanical structure die
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/01Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/012Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/07Interconnects
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/09Packages
    • B81B2207/091Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094Feed-through, via
    • B81B2207/096Feed-through, via through the substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/11Structural features, others than packages, for protecting a device against environmental influences
    • B81B2207/115Protective layers applied directly to the device before packaging
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/05Temporary protection of devices or parts of the devices during manufacturing
    • B81C2201/053Depositing a protective layers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/07Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0785Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
    • B81C2203/0792Forming interconnections between the electronic processing unit and the micromechanical structure
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    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
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    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H05K2203/308Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -C.-- -.` 1#11111110111010101111101 1010 01111 OM 0111110111011101110111011# Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .../ WO 2018/031999 Al 15 February 2018 (15.02.2018) WIP0 I PCT (51) International Patent Classification: (72) Inventors: HO1L 23/31 (2006.01) H01L 21/60 (2006.01) erfield Lane, HO1L 21/56 (2006.01) HAMMOND, (21) International Application Number: Oak Ridge, PCT/US2017/046779 6601 Ashton (US). (22) International Filing Date: (74) Agent: WITHROW, 14 August 2017 (14.08.2017) va, P.L.L.C., (25) Filing Language: English olina 27511 (26) Publication Language: English (81) Designated kind of national (30) Priority Data: AO, AT, AU, 62/374,447 12 August 2016 (12.08.2016) US CA, CH, CL, (71) Applicant: QORVO US, INC. [US/US]; 7628 Thorndike DZ, EC, EE, Road, Greensboro, North Carolina 27409 (US). HR, HU, ID, IL, IN, KR, KW, MG, MK, North Carolina 27310 (US). COSTA, Julio, C.; Park Drive, Oak Ridge, North Carolina 27310 VANDEMEER, Kernersville, Jonathan, Jan, Edward; 279 Weath- North Carolina 27284 (US). Hale; 5808 Autumn Gate Drive, Benjamin, S.; Withrow & Terrano- Pinedale Springs Way, Cary, North Car- (unless otherwise indicated, for every available): AE, AG, AL, AM, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, ES, FI, GB, GD, GE, GH, GM, GT, HN, IR, IS, JO, JP, KE, KG, KH, KN, KP, LC, LK, LR, LS, LU, LY, MA, MD, ME, MX, MY, MZ, NA, NG, NI, NO, NZ, protection 106 (US). States AZ, CN, EG, KZ, LA, MN, MW, (54) Title: WAFER — -LEVEL PACKAGE WITH ENHANCED PERFORMANCE 2 38 42 redistribution layer (24) the first device between the redistribution within the the top surface = = _ = — = = = 24 : 6 . „ = = . . ' . = 18 : (18), from to package and mold compound and over the first thinned die. the first thinned die. (57) 01 structure M redistribution interconnects and --.... structure W . 7 7: / t , . ,,, , . . 6 L y c l +.,,,,, , AV • 0 6 ••. . , -- 4 l ' 40 ,,,, ;/07. 7 . '-', /-:1-. % J = 46 44 The present disclosure relates to a wafer-level package that includes a first thinned die (12), a a first mold compound glass materials. contacts (44) around the first thinned die, and extends A (20), and The multilayer redistribution on a bottom surface the first device layer are solder-free. The first mold compound resides over the 44 46 44 46 FIG. i a second mold compound (22). The first thinned die includes a first device structure includes redistribution interconnects that of the multilayer redistribution beyond a top surface of the first thinned die to define The second mold compound fills the opening and is in contact 44 46 44 multilayer connect multilayer an opening with = = = ,-1 C'N formed 01 ,1 layer 0 GC first 1-1 C of N structure. Herein, the connections C [Continued on next page] WO 2018/031999 Al MIDEDIMOMOIDEIREEMODHOMMEHOHOMEin OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3)) — with amended claims and statement (Art. 19(1))
SG11201901196RA 2016-08-12 2017-08-14 Wafer-level package with enhanced performance SG11201901196RA (en)

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US20180044177A1 (en) 2018-02-15

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