KR890015361A - 반도체장치의 제조방법 및 그 장치 - Google Patents

반도체장치의 제조방법 및 그 장치 Download PDF

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KR890015361A
KR890015361A KR1019890003912A KR890003912A KR890015361A KR 890015361 A KR890015361 A KR 890015361A KR 1019890003912 A KR1019890003912 A KR 1019890003912A KR 890003912 A KR890003912 A KR 890003912A KR 890015361 A KR890015361 A KR 890015361A
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semiconductor device
etching
flow rate
intermediate semiconductor
etching rate
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KR1019890003912A
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KR920006261B1 (ko
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도루 와타나베
가츠야 오쿠무라
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/913—Diverse treatments performed in unitary chamber

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Weting (AREA)

Abstract

내용 없음

Description

반도체장치의 제조방법 및 그 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 따른 장치의 제 1 실시예에 관한 전체 구성도. 제 2 도는 CF4O2혼합가스의 마이크로파 방전프라즈마에 의한 실리폰(Si) 및 실리콘산화막(SiO2)의 에칭속도의 온도의 존성을 나타낸 그래프. 제 3 도는 본 발명에 따른 장치의 제 2 실시예에 관한 전체 구성도. 제 4 도는 CF4와 O2혼합가스의 마이크로파 방전프라즈마에 의한 Si 및 SiO2의 에칭속도와 가스유량비(O2/(CF4+O2))의 관계를 나타낸 그래프. 제 5 도는 기판재료와 그 산화물의 에칭속도의 비율이 5 이하로 되기 위한 에칭조건의 영역을 나타낸 그래프.

Claims (4)

  1. 할로겐화합물가스와 산소가스로 이루어진 혼합가스의 방전활성종에 의해 상기 혼합가스의 유량에 대한 상기 산소가스의 유량의 비와 산기 중간반도체장치의 온도를 제어함으로써 실리콘의 에칭속도와 실리콘산화물의 에칭속도를 가급적 근접시킨 에칭조건하에 하부층으로서의 중간반도체장치 표면의 산화막을 제거하는 공정과, 상기 산화물을 제거한 상기 중간반도체 장치의 표면을 대기에 노출시키지 않고 상기 표면에 막을 형성시키는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제 1 항에 있어서, 에칭조건이 실리콘산화물의 에칭속도에 대한 실리콘의 에칭속도의 에칭속도비가 5 이하인 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제 2 항에 있어서, 에칭속도가 5 이하인 에칭조건이 혼합가스의 유량에 대한 산소가스의 유량의 비를 Y(%)로 하고 중간반도체장치의 온도를 T(℃)로 했을때
    Y -0.13T+106.3
    으로 되는 식을 만족시킴으로써 얻어지도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  4. 할로겐화합물가스와 산소가스로 이루어지는 혼합가스의 방전활성종에 의해 상기 혼합가스의 유량에 대한 상기 산소가스의 유량의 비와 상기 중간반도체장치의 온도를 제어함으로써 실리콘의 에칭속도와 실리콘산화물의 에칭속도의 차를 작게 한 에칭조건하에서 하부층으로서 중간반도체장치의 표면의 산화막을 제거하는 수단(10,2-4)과, 상기 산화물을 제거한 상기 중간반도체장치의 표면을 대기에 노출시키지 않고 상기 표면에 막을 형성하는 수단(10,3-10)을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890003912A 1988-03-28 1989-03-28 반도체장치의 제조방법 및 그 장치 KR920006261B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP88-73628 1988-03-28
JP63073628A JP2768685B2 (ja) 1988-03-28 1988-03-28 半導体装置の製造方法及びその装置
JP63-73628 1988-03-28

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KR890015361A true KR890015361A (ko) 1989-10-30
KR920006261B1 KR920006261B1 (ko) 1992-08-01

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US (1) US5067437A (ko)
EP (1) EP0335313A3 (ko)
JP (1) JP2768685B2 (ko)
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Cited By (1)

* Cited by examiner, † Cited by third party
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