KR960042996A - 화학량론적으로 변화된 질화물 에치 정치층을 사용한 고밀도의 선택적 SiO_2 : Si_3N_4 에칭 - Google Patents

화학량론적으로 변화된 질화물 에치 정치층을 사용한 고밀도의 선택적 SiO_2 : Si_3N_4 에칭 Download PDF

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KR960042996A
KR960042996A KR1019960012358A KR19960012358A KR960042996A KR 960042996 A KR960042996 A KR 960042996A KR 1019960012358 A KR1019960012358 A KR 1019960012358A KR 19960012358 A KR19960012358 A KR 19960012358A KR 960042996 A KR960042996 A KR 960042996A
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stoichiometrically
stop layer
etch stop
nitride
oxide
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KR1019960012358A
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KR100209041B1 (ko
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디. 아마코스트 마이클
도브진스키 데이비드
감비노 제프리
뉴구엔 선
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윌리엄 티. 엘리스
인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Si3N4에 대한 SiO2의 선택도가 반도체칩 제조 중에 고농도 실리콘 질화물 컨포멀충을 부가함으로써 증가된다. 고농도 실리콘 질화물 컨포멀층이, 제조 과정에서 표준 질화물 컨포멀층을 대체하여 또는 그것에 부가해서 사용될 수 있다.

Description

화학량론적으로 변화된 질화물 에치 정치층을 사용한 고밀도의 선택적 SiO2: Si3N4에칭
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 고 선택적 산소 : 질소 에치 공정 및 저항 스트립 후의 무경계 접촉 구조의 단면도.

Claims (7)

  1. 더 낮은 위치의 에지 인지(susceptible)재료 위에서 코너를 도포하는 질화물 층을 에치 정지층으로 사용 하여 애퍼쳐에 중착된 산화물을 에치하는 방법에 있어서, 산화물 위에서 향상된 에치 선택도를 부여하는 재료를 부가하여 화학량론적으로 형성된 질화물 에치 정지층을 에치 인지 재료 위에 증착시키는 단계, 상기 산화물 위에서 애퍼쳐를 패턴화하는 단계, 및 상기 산화물을 통해 에치하고, 질화물 에치 정지층 위에서 에치를 멈추는 단계를 포함하는 것을 특징으로 하는 산화물 에치하는 방법.
  2. 제1항에 있어서, 상기 질화물에 화학량론적으로 부가된 상기 재료가 실리콘인 것을 특징으로 하는 산화물을 에치하는 방법.
  3. 제2항에 있어서, 상기 실리콘이 43.1에서 65까지의 원자비율(atomic percent)의 농도 범위를 갖는 것을 특징으로 하는 산화물을 에치하는 방법.
  4. 제2항에 있어서, 상기 농도 범위가 50에서 60까지의 원자비율인 것을 특징으로 하는 산화물을 에치하는 방법.
  5. 제1항에 있어서, 상기 질화물에 화학량론적으로 부가된 상기 재료가 SiO2에 비해 낮은 에치율을 갖는 재료인 것을 특징으로 하는 산화물을 에치하는 방법.
  6. 제5항에 있어서, 상기 질화물에 화학량론적으로 부가된 상기 재료가 Al2O3인 것을 특징으로 하는 산화물을 에치하는 방법.
  7. 제5항에 있어서, 상기 질화물에 화학량론적으로 부가된 재료가 Y2O3인 것을 특징으로 하는 산화물 에치하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960012358A 1995-05-08 1996-04-23 화학량론적으로 변환된 질화물 에치 정지층을 사용한 고밀도의 선택적 sio2:si3n4 에칭 KR100209041B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/435,063 1995-05-08
US08/435,063 US5622596A (en) 1995-05-08 1995-05-08 High density selective SiO2 :Si3 N4 etching using a stoichiometrically altered nitride etch stop
US8/435,063 1995-05-08

Publications (2)

Publication Number Publication Date
KR960042996A true KR960042996A (ko) 1996-12-21
KR100209041B1 KR100209041B1 (ko) 1999-07-15

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US (1) US5622596A (ko)
EP (1) EP0742584A3 (ko)
JP (1) JP3193632B2 (ko)
KR (1) KR100209041B1 (ko)
TW (1) TW301777B (ko)

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US5880005A (en) * 1997-10-23 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a tapered profile insulator shape
US6207575B1 (en) * 1998-02-20 2001-03-27 Advanced Micro Devices, Inc. Local interconnect etch characterization using AFM
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US6063711A (en) * 1998-04-28 2000-05-16 Taiwan Semiconductor Manufacturing Company High selectivity etching stop layer for damascene process
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
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US5622596A (en) 1997-04-22
TW301777B (ko) 1997-04-01
KR100209041B1 (ko) 1999-07-15
JP3193632B2 (ja) 2001-07-30
EP0742584A3 (en) 1997-10-08
JPH08306658A (ja) 1996-11-22
EP0742584A2 (en) 1996-11-13

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