TW301777B - - Google Patents
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- TW301777B TW301777B TW085100436A TW85100436A TW301777B TW 301777 B TW301777 B TW 301777B TW 085100436 A TW085100436 A TW 085100436A TW 85100436 A TW85100436 A TW 85100436A TW 301777 B TW301777 B TW 301777B
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- 150000004767 nitrides Chemical class 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229920000642 polymer Polymers 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002013 dioxins Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Description
經濟部中央標準局負工消費合作社印裝 A7 B7 五、發明説明(1 ) 發明背景 發明領域 本發明一般係關於半導體晶片製造且,更特定言之,係 關於使用一化學計量改變之氮化物蚀刻停止的Si02對Si3N4 選擇性蝕刻。 背景説明 次0.5微米超大型積體(Ultra Large Scale Integrated,下文簡 稱ULSI)電略應用需要反應性離子蚀刻(reactive ion etch,下 文簡稱RIE)製程,該製程將相對於氮化物而高度選擇地蝕 刻氧化物。這已在平坦表面上展現出來,但是先進應用中 爲人信服的基礎规則需要在露出角落之上的高氮化物選擇 度。這類的最普通實例是擴散接點覆蓋一閘極之處。在閘 極的露出角落上需要大於12對1的選擇度以防止由閘極至 接點的漏電。 選擇性氧化物:氮化物蚀刻製程已導入,但是這些製程 需要聚合物形成到離子能控制的微妙平衡。這些條件對類 似於氮化物成份的環境擾動非常敏感,且不幸地,該製程 合格間窗對製造應用而言,變得太小。 已在裝置邊緣上導入厚氧化物間隔物以吸收蚀刻期間可 能發生的任何氮化物浸蝕。然而這種程序不能用於具有非 常高之構裝密度的應用中。 -4- 本紙張尺度適用中國囷家標牟(CNS ) A4说格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) .丨.装. 、-=5 A7 301777 — ----—________ 五、發明説明(2 ) 一~~' ' 發明摘述 本發明之一目的,係在氧化物蝕刻製程期間提供強化露 出部分角落處之氮化物選擇度的方法,並降低氮化物角落 1^1. n —· ϊ. .....1 - I I ! 乂~Ί— · - - _ ——... I— • i f靖先閱讀背面之注意事項再填寫本頁) 浸姓。 根據本發明的一個觀點,積體電路製備有氮化物密接層 作爲蝕刻停止。氮化物蝕刻停止層沈積於蝕刻敏感材料的 一個角落之上。這個氮化物蝕刻停止層具有特徵爲,由於 一材料的添加而化學計量地形成的氮化物,該材料引入對 於氧化物之_改良的蝕刻選擇度。在氧化物之上形成一個開 口圖樣’然後施行蝕刻穿過氧化物,其停止於氮化物層上 而沒有浸蚀。藉由增加矽的濃度,或藉由添加八12〇3或γ2〇3 來改變密接層中的氮化物。 附圖簡要説明 前述和其他的目的、觀點及優點從下列之本發明較佳具 體實施例的詳細説明,參考附圖,將更易於瞭解,該附圖 中: 經濟部中央橾準局員工消費合作社印製 圖1是無邊界接點結構在高選擇度氧化物:氮化物蝕刻 製程和隔絕層剝除之後的橫斷面; 圖2是添加所提出之改變膜之如圖1中之無邊界接點結構 的橫斷面; 圖3是具有變化之矽原子百分比之富含矽氮化物薄樣品 的電容-電壓曲線圖形;及 圖4是具有變化之矽原子百分比之富含矽氮化物薄樣品 ______ *5' 木纸張編5中國國—- 經濟部中央標準局員工消費合作社印製 五、發明説明(3 的電流-電壓曲線圖形 主f明較佳具體實施例詳細部BE[ 現在參考附圖’且更特定言之,參考圖1,其處顯示一 個需要高氧化物對氮化物選擇度的典型部分,其由具有閘 極電極2,厚度約是2000·8000埃,的矽基板i組成。閘極電 極2具有氮化物頂部3 ’且電極和基板填覆有薄密接氮化物 層4,其厚度通常是在10〇_1〇〇〇埃之間。然後將這些部分填 充諸如二氧_化矽的介電物5,將其平坦化並使用光阻形成 圖樣且加以蝕刻。 、 在本發明中,導入化學計量變化的氮化物層作爲整個或 部分的密接氮化物層。如在圖2中所能見到,構建出具有 矽基板1、閘極電極2、頂部3和密接氮化物層4的部分。 添加上改變的密接氮化物層6。這個結構可構建成讓改變 的密接氮化物層6取代第一密接氮化物層4。這種相同類型 的改變氮化物可另外包括於閘極電極2的頂部3中。這種氮 化物層含有較高濃度的某些材料,諸如矽和氫,其在蝕刻 製程期間增加相當的選擇度給氮化物膜,而幾乎完全不會 改變材料的介電性質。 高選擇度氧化物蝕刻製程在整個半導體工業中普遍地爲 人所知。特定而言,對矽大於4〇 : i的選擇度已在平坦的 表面上獲得。當使用廢氣排除媒質時,這些類型的選擇度 可因爲石們的獨立射頻偏壓、低壓力及低氟含量聚合物而 在先進的蝕刻系統中,諸如AME世紀型(temu氧化物蝕 _ ' 6 ' 本紙張賴t關家料(CNS )爾彳^7210Χ21^^Τ .— ·-!<.裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央棣準局貝工消費合作衽印製
五、發明説明(4 ) 刻機,輕易地達到。仓,丨』 … π,對多晶矽的高選擇度甚至可在 延長的過度姓刻時間中於矣工f Μ 中於表面m獲得。這是値得注意 的,因爲當導入表面形能眭 ^, 思 、時,路出之角落上的離子撞擊居 生作用而去除沈積的麽人榀 m 躓的聚合物’因而容許了多晶矽角落的飛 濺。 54 需要導電性姓刻停止的製程對製造而言,並不爲人期 待。,些膜爲電氣短路提供了通道,且在欢的情形中,將 材料氧化掉的企圖會導致應力相關的損壞。因此,諸如
Sl3N4之爲人-所熟知的絕緣體是蝕刻停止的理想類型候選材 料0 表面形態之上的選擇性氧化物:氮化物蝕刻是困難的, 因爲角落選擇度對離子撞擊極端敏感。這個敏感度大於對 多阳碎蚀刻停止者,造成更小的製程合格間窗。爲了增大 σ格間窗’要改變叫队成份’如此它含有較高的妙百 刀比,在43_1至65原子百分比的範圍中。該材料在這整個 範圍中疋絕緣性的,如顯示於圖3之圖形中的電容-電壓特 性所顯現。在這個圖形中,最底部曲線21代表具有431原 子百为比之矽的樣品,最頂部曲線22代表具有67原子百分 比足矽的樣品。化學計量可使用光學性質,特別是,膜的 折射率加以監看。具有43至60%矽原子百分比之樣品的折 射率自1 _90變化至2.11。具有65至6»7原子百分比之砂·的樣品 擁有2.20的折射率。電容-電壓上的一個偏移以箭頭23顯 不。這個偏移是因電荷積陷而引起。然而,可在裝置穩定 上具有決疋性效果的電荷積陷在較向砂含量時,變得更 f請先閲y背面之注意事項再填寫本^) 訂- * 乂·'1 紙張尺度it用巾g| gj家縣(CNS ) A4^^. 210X297 公釐) A7 B7 S01777 五、發明説明(5 爲嚴重’如從顯示於圖4之圖报击4Λ 囫形中t電容·電壓特性的偏移 所見到。電容·電壓特性之傯孩 公付[疋偏移的増加對應於積陷電荷的 增加數量。這條曲線也代表蒗4 '衣尋的,在300·400埃之間,而具 有43」至67矽原子百分比的氮化物樣品。因此,使蝕刻選 擇度最大而”使導電度最小的最佳濃度範圍是5〇至⑼原 子百分比。^’當這個氮化物保有將防止短路的絕緣體 特性時,它將也具有製造程序所需要之增大的選擇度。 在電漿強化化學氣相沈積(Plasma Enhaneed QemiW VapQf Deposition ’厂下文簡稱PECVD)製程期間,藉由調整別艮流量 相對NH3或&比例可輕易地完成氮化物化學計量的調整。 以k種方式可用最少的製程最佳化得到變化自約原子 百为比的/展度。也可藉由濺鍍或藉由其他的化學氣相沈積 製程沈積,或者以離子佈植形心匕學計量改變的氮化物 膜。 經濟部中央標準局員工消费合作社印製 這項技術,儘管以富含矽的氮化物展示,可擴展至包括 其他種類的選擇度強化物。這些可包括氫,其可在蝕刻期 間作爲聚合物來源。其他爲人所知的蝕刻停止材料,諸如 Si2〇3、A〖2〇3、或Υ2〇3 ’也可藉由濺鍍、CVD、或離子佈植 而併入氮化物膜中,其將容許它表現出如同氮化物的行 爲’但具有足夠的添加膜特性以改良氧化物蚀刻化學作用 上的選擇度。 這個製程增加最少的複雜性。這種化學計量改變的膜可 添加於既存之低壓化學氣相沈積(LpcvD)氮化物的上方, 或者,如果信賴度可接受的話,可用作單獨的蝕刻停止, -8 - 本紙張用巾闕家料(CNS ) Α4·_ ( 2!〇χ297公釐 A7 B7 五、發明説明(6 其不需要額外的製程步驟。 另外,本發明是爲人期待的 ^ 、 疋乃力伃的,因為它指出無邊界接點製 程的施行視要控制的部分而定 心’向+早只是蝕刻製程。雖 然高密度電漿蝕刻對蝕刻高縱橫比並在平坦表面上獲得對 氮化物的選擇度可能具關鍵性,但是它本身並不是裊 邊界接點的方法。 &典 儘管本發明已經以單一個較佳具體實施例說明,但是熟 請此技藝者將認知到,本發明可根據在附加之申請專利範 圍之精神和之内的修正而實施。 (請先閲讀背面之注意事項再填寫本頁} -訂 ,—x’ 經濟部中央揉準局貝工消费合作社印製 本紙張尺反逋用中國國家標準(CNS ) Μ規格(2iOX297公釐)
Claims (1)
- 經濟部中央揉準局貝工消費合作社印製 1. -種蚀刻沈積於開口中之氧化物的方法,其使用氮化物 層作爲㈣停止,該氮化物覆蓋位於較低之#㈣感材 料之上的角落,其包含步驟有: 沈積氮化物蝕刻停止層於蝕刻敏感材料之上,氮化物 触刻停止層是·由於-材料之添加而化學計量地形成的氮 化物該材料引入對於氧化物之改良的蝕刻選擇度; 在氧化物之上形成一個開口圖樣;及 蝕刻穿過氧化物,停止於氮化物蝕刻停止層上。 2. 根據申明鼻利範圍第i項之方法,其中化學計量地添加 至該氮化物的該材料是矽。 3. 根據申請專利範圍第2項之方法 65原子百分比的濃度範圍。 4_根據申請專利範圍第2項之方法 至60原子百分比β 5-根據申請專利範圍第i項之方法一 至該氮化物的該材料是一種相對於Si〇2具有低蝕刻速^ 的材料。 6. 根據申請專利範圍第5項之方法,其中化學計量地心 至該氮化物的該材料是A1203。 7. 根據申請專利範圍第5項之方法,其中化學計量地添乂 至該氮化物的該材料是γ2〇3。 其中該矽具有43.1 J 其中該濃度範圍是5 其中化學計量地添;j (請先閲讀背面之注意事項再填寫本頁) 'tr .i ·
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US08/435,063 US5622596A (en) | 1995-05-08 | 1995-05-08 | High density selective SiO2 :Si3 N4 etching using a stoichiometrically altered nitride etch stop |
Publications (1)
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TW301777B true TW301777B (zh) | 1997-04-01 |
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Family Applications (1)
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TW085100436A TW301777B (zh) | 1995-05-08 | 1996-01-16 |
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US (1) | US5622596A (zh) |
EP (1) | EP0742584A3 (zh) |
JP (1) | JP3193632B2 (zh) |
KR (1) | KR100209041B1 (zh) |
TW (1) | TW301777B (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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US6040619A (en) * | 1995-06-07 | 2000-03-21 | Advanced Micro Devices | Semiconductor device including antireflective etch stop layer |
US5897372A (en) * | 1995-11-01 | 1999-04-27 | Micron Technology, Inc. | Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer |
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US4656729A (en) * | 1985-03-25 | 1987-04-14 | International Business Machines Corp. | Dual electron injection structure and process with self-limiting oxidation barrier |
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US5252515A (en) * | 1991-08-12 | 1993-10-12 | Taiwan Semiconductor Manufacturing Company | Method for field inversion free multiple layer metallurgy VLSI processing |
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US5324690A (en) * | 1993-02-01 | 1994-06-28 | Motorola Inc. | Semiconductor device having a ternary boron nitride film and a method for forming the same |
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1995
- 1995-05-08 US US08/435,063 patent/US5622596A/en not_active Expired - Fee Related
-
1996
- 1996-01-16 TW TW085100436A patent/TW301777B/zh active
- 1996-04-04 EP EP96480038A patent/EP0742584A3/en not_active Withdrawn
- 1996-04-23 KR KR1019960012358A patent/KR100209041B1/ko not_active IP Right Cessation
- 1996-04-30 JP JP10911196A patent/JP3193632B2/ja not_active Expired - Fee Related
Also Published As
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KR100209041B1 (ko) | 1999-07-15 |
EP0742584A2 (en) | 1996-11-13 |
JP3193632B2 (ja) | 2001-07-30 |
US5622596A (en) | 1997-04-22 |
EP0742584A3 (en) | 1997-10-08 |
KR960042996A (ko) | 1996-12-21 |
JPH08306658A (ja) | 1996-11-22 |
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