KR20060110097A - 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법 - Google Patents
미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910003697 SiBN Inorganic materials 0.000 claims description 4
- 229910004541 SiN Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 69
- 239000011295 pitch Substances 0.000 description 38
- 125000006850 spacer group Chemical group 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000001878 scanning electron micrograph Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- CGEORJKFOZSMEZ-MBZVMHRFSA-N (+)-sesamin monocatechol Chemical compound C1=C(O)C(O)=CC=C1[C@@H]1[C@@H](CO[C@@H]2C=3C=C4OCOC4=CC=3)[C@@H]2CO1 CGEORJKFOZSMEZ-MBZVMHRFSA-N 0.000 description 1
- IMSOBGJSYSFTKG-PKPIPKONSA-N Lysinoalanine Chemical compound OC(=O)[C@@H](N)CCCCNCC(N)C(O)=O IMSOBGJSYSFTKG-PKPIPKONSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 210000004087 cornea Anatomy 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (20)
- 기판상의 피식각막 위에 제1 피치(pitch)를 가지고 제1 방향으로 반복 형성되는 복수의 제1 라인 패턴으로 이루어지는 제1 하드마스크 패턴을 형성하는 단계와,상기 제1 라인 패턴 중 상호 인접한 2개의 제1 라인 패턴 사이에 리세스(recess)가 형성되는 상면을 가지도록 상기 제1 하드마스크 패턴의 상면 및 측벽을 균일한 두께로 덮는 제1 막을 형성하는 단계와,상기 제1 막 위의 상기 리세스 내에서 상기 제1 방향으로 연장되는 제2 라인 패턴으로 이루어지는 제2 하드마스크 패턴을 형성하는 단계와,상기 제1 라인 패턴 및 제2 라인 패턴을 식각 마스크로 하여 상기 제1 막을 이방성 식각하여 상기 제1 라인 패턴과 상기 제2 라인 패턴과의 사이에서 상기 피식각막을 노출시키는 단계와,상기 제1 하드마스크 패턴 및 제2 하드마스크 패턴를 식각 마스크로 하여 상기 피식각막을 이방성 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제1항에 있어서,상기 제1 막 형성 단계에서 상기 제1 막 상면에는 복수의 리세스가 형성되고,상기 제2 라인 패턴은 상기 복수의 리세스 중에서 선택되는 일부의 리세스 내에만 형성되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제1항에 있어서,상기 제2 하드마스크 패턴을 형성하는 단계는상기 제1 막과 식각 선택비 차이가 있는 제2 막을 상기 제1 막 위에 형성하는 단계와,상기 제2 막 중 일부를 제거하여 상기 리세스 내에 상기 제2 막의 나머지 일부로 이루어지는 상기 제2 라인 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제3항에 있어서,상기 제2 막 중 일부를 제거하기 위하여 습식 식각 방법을 이용하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제3항에 있어서,상기 제2 라인 패턴은 상기 제1 피치의 1/4인 폭을 가지도록 형성되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제3항에 있어서,상기 제1 막 형성 단계에서 상기 제1 막 상면에는 복수의 리세스가 형성되고,상기 제2 막의 일부를 제거하는 동안 상기 복수의 리세스 중에서 선택되는 일부의 리세스 내에서는 상기 제2 막이 완전히 제거되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제6항에 있어서,상기 제2 라인 패턴은 상기 복수의 리세스 중에서 선택되는 일부의 리세스 내에만 형성되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제1항에 있어서,상기 제1 라인 패턴 및 제2 라인 패턴에 의하여 상기 기판상에 상기 제1 피치의 1/2인 피치를 가지는 복수의 라인 앤드 스페이스 패턴 (line and space pattern)이 형성되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제1항에 있어서,상기 제1 하드마스크 패턴은 상기 피식각막 위에 차례로 적층된 제3 막 및 제4 막으로 이루어지고,상기 제2 라인 패턴은 상기 제4 막과 동일한 수평면상에 위치되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제4 막 및 상기 제2 라인 패턴은 상호 동일한 물질로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제1 막은 산화막으로 이루어지고,상기 제4 막 및 제2 라인 패턴은 각각 질화막 또는 폴리실리콘막으로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제11항에 있어서,상기 제1 막은 열산화막, CVD 산화막, USG막 (undoped silicate glass film) 및 HDP 산화막 (high density plasma oxide film)으로 이루어지는 군에서 선택되는 적어도 하나의 막으로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제11항에 있어서,상기 제4 막 및 제2 라인 패턴은 각각 SiON, SiN, SiBN, BN 및 폴리실리콘막으로 이루어지는 군에서 선택되는 적어도 하나의 막으로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제1 막은 질화막으로 이루어지고,상기 제4 막 및 제2 라인 패턴은 각각 산화막으로 이루어지는 군에서 선택되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제14항에 있어서,상기 제1 막은 SiON, SiN, SiBN 및 BN으로 이루어지는 군에서 선택되는 적어도 하나의 막으로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제14항에 있어서,상기 제4 막 및 제2 라인 패턴은 각각 SOG막 (silicon on glass film) 및 FOX막 (flowable oxide film)으로 이루어지는 군에서 선택되는 적어도 하나의 막으로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제1 막 및 제3 막은 상호 동일한 물질로 이루어지는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제1 막 및 제3 막은 서로 다른 물질로 이루어진 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제4 막 및 제2 라인 패턴은 서로 다른 물질로 이루어진 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제9항에 있어서,상기 제4 막 및 제2 라인 패턴은 상호 동일한 물질로 이루어진 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050032297A KR100640640B1 (ko) | 2005-04-19 | 2005-04-19 | 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법 |
US11/367,437 US7473647B2 (en) | 2005-04-19 | 2006-03-06 | Method of forming pattern using fine pitch hard mask |
JP2006113557A JP5052814B2 (ja) | 2005-04-19 | 2006-04-17 | 微細ピッチのハードマスクを用いた半導体素子の微細パターン形成方法 |
US11/699,476 US7576010B2 (en) | 2005-04-19 | 2007-01-30 | Method of forming pattern using fine pitch hard mask |
US12/327,006 US8062981B2 (en) | 2005-04-19 | 2008-12-03 | Method of forming pattern using fine pitch hard mask |
US12/966,110 US8361904B2 (en) | 2005-04-19 | 2010-12-13 | Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same |
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KR1020050032297A KR100640640B1 (ko) | 2005-04-19 | 2005-04-19 | 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법 |
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KR20060110097A true KR20060110097A (ko) | 2006-10-24 |
KR100640640B1 KR100640640B1 (ko) | 2006-10-31 |
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US (3) | US7473647B2 (ko) |
JP (1) | JP5052814B2 (ko) |
KR (1) | KR100640640B1 (ko) |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100790998B1 (ko) * | 2006-10-02 | 2008-01-03 | 삼성전자주식회사 | 셀프 얼라인 더블 패터닝법을 사용한 패드 패턴 형성 방법 및 셀프 얼라인 더블 패터닝법을 사용한 콘택홀 형성방법 |
KR100833201B1 (ko) | 2007-06-15 | 2008-05-28 | 삼성전자주식회사 | 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법 |
KR100843917B1 (ko) * | 2006-09-08 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자 제조 방법 |
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Also Published As
Publication number | Publication date |
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JP2006303500A (ja) | 2006-11-02 |
KR100640640B1 (ko) | 2006-10-31 |
JP5052814B2 (ja) | 2012-10-17 |
US7473647B2 (en) | 2009-01-06 |
US8062981B2 (en) | 2011-11-22 |
US7576010B2 (en) | 2009-08-18 |
US20090117497A1 (en) | 2009-05-07 |
US20070123037A1 (en) | 2007-05-31 |
US20060234166A1 (en) | 2006-10-19 |
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