JP6026375B2 - 半導体装置の製造方法 - Google Patents
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
Description
図1(a)〜図2(d)は、第1実施形態の半導体装置の製造方法を示す模式断面図である。
図3(a)〜図4(e)は、第2実施形態の半導体装置の製造方法を示す模式断面図である。
図5(a)〜図6(d)は、第3実施形態の半導体装置の製造方法を示す模式断面図である。
Claims (4)
- 下地上に、第1の膜のラインパターンを形成する工程と、
前記第1の膜のラインパターンの側壁および上面に、コンフォーマルに第2の膜を堆積させる工程と、
前記第2の膜をエッチバックして、前記第1の膜のラインパターンの上面上の前記第2の膜を除去し、前記第1の膜のラインパターンの側壁に前記第2の膜を残す工程と、
前記第1の膜のラインパターンをエッチングして除去し、前記下地上に前記第2の膜のラインパターンを残す工程と、
前記第2の膜のラインパターンの側壁および上面に、コンフォーマルに第3の膜を堆積させる工程と、
前記第3の膜をエッチバックして、前記第2の膜のラインパターンの上面上の前記第3の膜を除去し、前記第2の膜のラインパターンの側壁に前記第3の膜を残す工程と、
前記第2の膜のラインパターンをエッチングして除去し、前記下地上に前記第3の膜のラインパターンを残す工程と、
を備え、
前記第2の膜を堆積させる工程、前記第2の膜をエッチバックする工程、および前記第1の膜のラインパターンをエッチングする工程を、同じプラズマ処理装置内で続けて行い、
前記第3の膜を堆積させる工程、前記第3の膜をエッチバックする工程、および前記第2の膜のラインパターンをエッチングする工程を、同じプラズマ処理装置内で続けて行う半導体装置の製造方法。 - 第1の下地膜と、前記第1の下地膜の上に形成された第2の下地膜とを有する下地上に、第1の膜のラインパターンを形成する工程と、
前記第1の膜のラインパターンの側壁および上面に、コンフォーマルに第2の膜を堆積させる工程と、
前記第2の膜をエッチバックして、前記第1の膜のラインパターンの上面上の前記第2の膜を除去し、前記第1の膜のラインパターンの側壁に前記第2の膜を残す工程と、
前記第1の膜のラインパターンをエッチングして除去し、前記下地上に前記第2の膜のラインパターンを残す工程と、
前記第2の膜のラインパターンをマスクにしたエッチングにより、前記第2の下地膜をラインパターンに加工する工程と、
前記第2の膜のラインパターンをエッチングして除去し、前記第1の下地膜上に前記第2の下地膜のラインパターンを残す工程と、
前記第2の下地膜のラインパターンの側壁および上面に、コンフォーマルに第3の膜を堆積させる工程と、
前記第3の膜をエッチバックして、前記第2の下地膜のラインパターンの上面上の前記第3の膜を除去し、前記第2の下地膜のラインパターンの側壁に前記第3の膜を残す工程と、
前記第2の下地膜のラインパターンをエッチングして除去し、前記第1の下地膜上に前記第3の膜のラインパターンを残す工程と、
を備え、
前記第2の膜を堆積させる工程、前記第2の膜をエッチバックする工程、および前記第1の膜のラインパターンをエッチングする工程を、同じプラズマ処理装置内で続けて行い、
前記第2の下地膜を加工する工程、前記第2の膜のラインパターンをエッチングする工程、前記第3の膜を堆積させる工程、前記第3の膜をエッチバックする工程、および前記第2の下地膜のラインパターンをエッチングする工程を、同じプラズマ処理装置内で続けて行う半導体装置の製造方法。 - 炭素を含むガスを用いたプラズマ処理で、炭素を含む前記第3の膜を堆積させる請求項1または2に記載の半導体装置の製造方法。
- 炭素を含む前記第1の膜に対して、シリコン及び酸素を含むガスを用いたプラズマ処理で、シリコン及び酸素を含む前記第2の膜を堆積させ、
フッ化炭素を含むガスを用いたプラズマ処理で、前記第2の膜をエッチバックする請求項1〜3のいずれか1つに記載の半導体装置の製造方法。
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JP2013181636A JP6026375B2 (ja) | 2013-09-02 | 2013-09-02 | 半導体装置の製造方法 |
US14/147,360 US9105584B2 (en) | 2013-09-02 | 2014-01-03 | Method of manufacturing a semiconductor device |
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US9711368B2 (en) * | 2013-04-15 | 2017-07-18 | United Microelectronics Corp. | Sidewall image transfer process |
JP2015198135A (ja) * | 2014-03-31 | 2015-11-09 | 株式会社東芝 | 半導体装置の製造方法 |
JP6757624B2 (ja) * | 2016-08-12 | 2020-09-23 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
US10453686B2 (en) * | 2016-08-31 | 2019-10-22 | Tokyo Electron Limited | In-situ spacer reshaping for self-aligned multi-patterning methods and systems |
WO2020033405A1 (en) * | 2018-08-08 | 2020-02-13 | Tokyo Electron Limited | Method utilizing using post etch pattern encapsulation |
JP2020145309A (ja) * | 2019-03-06 | 2020-09-10 | 株式会社東芝 | パターン形成方法及びパターン構造 |
JP2021047342A (ja) * | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | パターン形成方法及び半導体装置の製造方法 |
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JPH05144779A (ja) | 1991-11-21 | 1993-06-11 | Matsushita Electric Ind Co Ltd | シリコン酸化膜のドライエツチング方法 |
JP3607061B2 (ja) | 1997-10-29 | 2005-01-05 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4381694B2 (ja) * | 2003-02-25 | 2009-12-09 | 株式会社日立ハイテクノロジーズ | 試料の表面処理方法 |
JP2006245234A (ja) * | 2005-03-02 | 2006-09-14 | Tokyo Electron Ltd | プラズマ処理方法および装置 |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
KR100640640B1 (ko) * | 2005-04-19 | 2006-10-31 | 삼성전자주식회사 | 미세 피치의 하드마스크를 이용한 반도체 소자의 미세 패턴형성 방법 |
US7790360B2 (en) * | 2007-03-05 | 2010-09-07 | Micron Technology, Inc. | Methods of forming multiple lines |
KR100886219B1 (ko) | 2007-06-07 | 2009-02-27 | 삼성전자주식회사 | 자기정렬된 이중 패터닝을 채택하는 미세 패턴 형성 방법 |
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JP2009289974A (ja) * | 2008-05-29 | 2009-12-10 | Toshiba Corp | 半導体装置の製造方法 |
JP4756063B2 (ja) * | 2008-08-15 | 2011-08-24 | 株式会社東芝 | 半導体装置の製造方法 |
TWI476816B (zh) * | 2009-06-26 | 2015-03-11 | 羅門哈斯電子材料有限公司 | 自我對準間隔之多重圖案化方法 |
US20120222813A1 (en) * | 2011-03-01 | 2012-09-06 | Applied Materials, Inc. | Vacuum chambers with shared pump |
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