TW202045749A - 基板處理方法 - Google Patents

基板處理方法 Download PDF

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TW202045749A
TW202045749A TW109101634A TW109101634A TW202045749A TW 202045749 A TW202045749 A TW 202045749A TW 109101634 A TW109101634 A TW 109101634A TW 109101634 A TW109101634 A TW 109101634A TW 202045749 A TW202045749 A TW 202045749A
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substrate
mask
deposition
plasma chamber
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久松亨
本田昌伸
木原嘉英
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日商東京威力科創股份有限公司
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Abstract

本案提出電漿腔室內的基板處理方法。此方法包含提供一基板，於該基板上將蝕刻一底層且形成一遮罩。此方法更包含形成一保護膜於遮罩上。此方法更包含執行異向性沉積以選擇性地在遮罩的頂部形成一沉積層。

Description

基板處理方法
在此揭示的一例示性實施例係關於基板處理方法及設備。
最近幾年，各式各樣的遮罩圖案化技術隨著縮放比例的繼續加大而已成為焦點。這裡面包含了雙倍及四倍的圖案化。另一方面，極紫外光微影成像(Extreme Ultraviolet Lithography；EUVL)及圖案化已被廣泛地研究。當一維度(1D)的布局圖案的緊密間距透過EUV微影成像而達成時，在後續的蝕刻製程中便需要高精密的臨界尺寸(Critical Dimension；CD)控制；例如，原子等級的X-Y CD可控性及降低諸如線緣粗糙度(Line Edge Roughness；LER)、線寬粗糙度(Line Width Roughness；LWR)及局部臨界尺寸均勻度(Local Critical Dimension Uniformity；LCDU)之局部變異性。
舉例而言，使用EUVL將圖案化之特徵的邊緣平滑化的方法及設備已被提出(例如，見美國專利申請第2018/0190503A1號)。同時，其他技術已被提出以於高深寬比孔的蝕刻期間減少遮罩損耗(例如，見美國專利申請第2018/0233357A1號)。
根據一實施例，電漿腔室內的基板處理方法包含：提供一基板，於該基板上將蝕刻一底層且形成一遮罩；形成一保護膜於遮罩上；及執行異向性沉積以選擇性地在遮罩的頂部形成一沉積層。
根據一實施例，電漿腔室內的基板處理方法包含：提供一基板，於該基板上將蝕刻一底層且形成一遮罩；以一預定速率將基板暴露於生成自包含Cx Hy Fz 及N2 、O2 、H2 及F中至少其一之一處理氣體的一電漿。在Cx Hy Fz 中，(i)x是不小於1的自然數，y是不小於1的自然數且z是0或不小於1的自然數，或(ii)x是不小於1的自然數，y是0或不小於1的自然數且z是不小於1的自然數。
根據一實施例，電漿腔室內的基板處理方法包含：提供一基板，於該基板上將蝕刻一底層且形成一遮罩；以一預定速率將基板暴露於生成自包含Cx Hy Fz 及N2 、O2 、H2 及F中至少其一之一處理氣體的一電漿；形成一保護膜於遮罩上；執行異向性沉積以選擇性地在遮罩的頂部形成一沉積層。在Cx Hy Fz 中，(i)x是不小於1的自然數，y是不小於1的自然數且z是0或不小於1的自然數，或(ii)x是不小於1的自然數，y是0或不小於1的自然數且z是不小於1的自然數。
以下將參考附隨圖式詳細描述本申請案中揭示的基板處理之方法和設備的例示性實施例。以下揭示的說明性實施例無意以任何方式限制本申請案。
如上所述，圖案粗糙度已成為半導體製造之先進微影成像製程中的一個主要問題。已付出各式各樣的努力以降低微影製程後及蝕刻後特徵的粗糙度。然而，改善LCDU的同時還維持理想的CD並不容易。根據實施例的製程
根據底下實施例的製程實現了LCDU和X-Y CD可控性的改善。圖1是根據一實施例之基板處理的一例示性製程的流程圖。圖2A至2D是根據一實施例之基板處理之一例示性製程的說明示意圖。
首先，提供一基板100(圖2A，步驟S101)。在基板100上，形成各式各樣的層，舉例來說，這些層包含了如圖(見圖2A)所示順序之底層101，亦即要被蝕刻的層、抗反射塗層102及遮罩103。遮罩103可經由EUVL形成且可具有一預定圖案。然後，在遮罩103上形成保護膜200(圖2B，步驟S102)。從保護膜200的上方，進行異向性沉積(圖2C，步驟S103)。步驟S103中的異向性沉積之製程條件的設定係使得沉積物層104選擇性地形成在遮罩103的頂部TP上。舉例來說，層104實質上僅在遮罩103的頂部TP上形成，但不在基板100上之圖案的底部BTM和/或側壁部SD上形成。因此，步驟S103之異向性沉積的作用在於以層104實質地增加遮罩103的厚度。可選地，可以執行X-Y CD控制(步驟S104)。為了X-Y CD控制，可執行後面將描述到的再沉積。在步驟104之後，執行蝕刻以蝕刻底層101(圖2D，步驟S105)。可選地，可執行進一步的製程(步驟S106)。因此，根據一個實施例的製程結束。
此處，基板100可以是矽(Si)基板。
底層101可以包括不止一層。底層101可以包括氧化物、金屬(例如鉿、鈷、鎢、鈦)或金屬氧化物、導電膜(例如鈦矽化物、鈦氮化物、鈷矽化物)、介電材料(例如矽氧化物、矽氮化物、旋塗式玻璃(spin-on-glass；SOG))、硬遮罩材料(例如非晶碳、非晶矽)或其他。
抗反射塗層102可以是含矽的抗反射塗層(silicon- containing anti-reflection coating；SiARC)或無氮的抗反射層(nitrogen-free anti-reflective layer；NFARL)。底層101可以包括旋塗式碳(spin-on carbon；SOC)層。
遮罩103可以是有機材料的遮罩，例如光阻劑。遮罩103可以是通過EUV微影製程所形成的有機光阻遮罩。遮罩103可以包括諸如鎢(W)或鈦(Ti)的金屬。
保護膜200可以是無機膜。保護膜200可以包括矽。保護膜200可以包括SiOx或SiNx。保護膜200可以包括金屬。保護膜200可以藉由下面描述的直流電疊加(direct current superposition；DCS)、化學氣相沉積(chemical vapor deposition；CVD)、物理氣相沉積(physical vapor deposition；PVD)或原子層沉積(atomic layer deposition；ALD)來形成。在以上的描述中，保護膜200係被描述為一沈積物層。可選地，保護膜200可以是遮罩103的表面。在這種情況下，遮罩103的表面以例如氬氣的處理氣體藉由DCS而固化以作為保護膜200。保護膜200具有至少一個原子層的厚度。例如，保護膜200的厚度可以為1-2奈米。
層104可以包含碳。
實現沉積的技術沒有特別限制。舉例而言，CVD、PVD、ALD和其他技術可以用於沉積。類似地，蝕刻可以通過例如乾式蝕刻和原子層蝕刻(atomic layer etching；ALE)來實現。在步驟S103的異向性沉積中，可以使用含有Cx Hy 和N2 、O2 、H2 和F中的至少其一的處理氣體。例如，可以使用包含甲烷(CH4 )和氮氣(N2 )的處理氣體。較佳地，處理氣體不包含氟化物(F)。換言之，處理氣體可以包含Cx Hy Fz ，其中(i)x是不小於1的自然數、y是不小於1的自然數且z是0或不小於1的自然數，或(ii)x是不小於1的自然數、y是0或不小於1的自然數且z是不小於1的自然數。在一實施例中，每個製程可在相同的電漿腔室或在相同的系統中執行，或可在不同的腔室或不同的系統中執行。
在圖1中，X-Y CD控制被描述為在異向性沉積(S103)之後執行。然而，X-Y CD控制的製程可以在異向性沉積(S103)之前、或者在保護膜200形成(S102)之前執行。舉例而言，在保護膜200形成之前可以執行後面將描述的平衡電漿製程。異向性沉積
在圖1的製程中，異向性沉積在步驟S103中執行。此異向性沉積的細節將在底下描述。
這裡，異向性沉積是指在沉積過程中，沉積物實質上僅在沿著圖案的一方向延伸的表面上形成層、而不在另一方向延伸的表面上形成層。在一實施例中，沉積物層實質上僅形成在基板之圖案的頂部上而不形成在圖案的底部或側壁部上。異向性沉積可以藉由各種製程條件的調整來實現。在本實施例中，異向性沉積係透過在沉積和蝕刻之間取得平衡來實現。
圖3顯示根據一實施例之異向性沉積的機制。在圖3的示例中，一個包含頂部TP、側壁部SD和底部BTM的圖案形成在基板上。當在該圖案上執行沉積製程時，沉積物可基於例如負載效應而在頂部TP上形成比在底部BTM或側壁部SD上更厚的層。同時，當在圖案上執行蝕刻製程時，欲蝕刻的量可以與在頂部TP和底部BTM上的蝕刻量相同。因此，如果在電漿製程中同時供應不同的氣體至基板，一氣體(例如碳氣體(C))用於在圖案上形成沉積物，而另一氣體(例如氮氣(N*、N+))用於蝕刻圖案，在底部BTM處的蝕刻和沈積可能會相互抵消，而在頂部TP處的沉積可能比蝕刻更突出。在圖3的情況下，沉積物層可以僅在頂部TP上形成。
圖4是用以說明根據一實施例的異向性沉積的圖表。
在圖4中，「初始」係將顯影後之光阻遮罩的垂直截面表示為初始狀態；「CH4 /N2 ：60秒」表示在使用包含CH4 和N2 的處理氣體執行異向性沉積60秒後之該光阻遮罩的狀態；「N2 ：60秒」表示將該光阻遮罩施以N2 氣體處理60秒的狀態；及「CH4 ：20秒」表示將該光阻遮罩施以CH4 氣體處理20秒的狀態。
如圖4所示，當CH4 氣體(主要用於沉積)和N2 氣體(主要用於蝕刻)在異向性沉積中使用60秒時，相較於初始狀態下觀察到的尺寸，遮罩的CD和高度兩者沒有明顯變化。另一方面，當僅使用N2 氣體60秒時，實質上除去了遮罩。此外，當僅使用CH4 氣體20秒時，儘管遮罩的高度從35.6nm增加到40.2nm，但是遮罩的整體形狀被扭曲且CD從30.8nm減小為28.2nm。因此，吾人可以說，通過在一個步驟中使用平衡條件來執行沉積和蝕刻兩者，可以實現期望的CD和遮罩高度。在此，這樣的在一個步驟中實現沉積和蝕刻的平衡效果的異向性沉積製程被稱為「平衡電漿製程」。
圖5顯示根據一實施例的實驗結果。在圖5的示例中，提供一個其上形成有光阻遮罩的基板。之後，如圖5所示，在遮罩中形成圖案(圖5中的「初始」)。之後，藉由向腔室內的上電極施加直流電，由氬氣(Ar)產生的電漿將遮罩圖案固化。之後，本實施例的異向性沉積使用包含CH4 和N2 的處理氣體執行了0秒(圖5中的「示例1」)、240秒(圖5中的「示例2」)和480秒(圖5中的「示例3」)。圖5中清楚顯示了，當不執行異向性沉積時，原始矩形之遮罩圖案的垂直截面隨著頂部變形而變成梯形(圖5中的「示例1」)。另一方面，當執行實施例的異向性沉積時，如示例2和示例3中那樣，遮罩的高度實質增加了。此外，LWR由於異向性沉積製程的結果而改善了。異向性沉積的貢獻因素
在執行異向性沉積的電漿腔室內，各種因素均有助於異向性沉積，例如分壓、黏滯係數、基板溫度和電荷密度，即離子密度。
圖6顯示欲處理圖案之側壁部的氣體黏滯係數與該圖案之深寬比之間的關係。從圖6可看出，當黏滯係數較低時，更多的自由基在孔內傳輸。當黏滯係數較高時，自由基不會在孔內傳輸且沉積物可能不會形成在孔的側壁或底部上。藉由利用黏滯係數的差異，可以控制圖案之側壁部上的沉積物的量。因此，在異向性沉積中較佳係使用諸如C4 F6 、SiCl4 和CH4 之具有高黏滯係數的氣體以及諸如O2 和N2 之具有低黏滯係數的氣體的組合。
圖7顯示圖案底部之離子密度和深寬比的關係。當圖案之底部的離子密度低時，在底部上形成的沉積物的量減少，換言之，將會有更多的負載效應。如圖7所示，當生成電漿的能量(eV)較低時，底部的離子密度較低。因此，為了利用負載效應，較低能量是較佳的。
沉積量也可基於施加的電壓來控制。此外，沉積量也可基於放置基板的靜電吸盤(electrostatic chuck；ESC)的溫度來控制。沉積量隨著ESC溫度的降低而增加。此外，ESC可被分為一個以上的區段，使得每個區段的溫度可以分別被控制。之後，沉積量可基於ESC的每個區段的溫度來控制。這可提升放置在ESC上之整個基板的沉積量的一致性。
將上述因素考慮進來，可對根據一實施例之異向性沉積的製程條件進行設定。建立遮罩
接著，將描述根據實施例來建立遮罩的效果。如上所述，當遮罩103為通過EUVL所形成的光阻遮罩時，遮罩103的厚度傾向於薄，例如約50nm。因此，如果在遮罩103上執行蝕刻，遮罩103可能很容易就被蝕刻掉。
在本實施例中，為了減少遮罩損耗，異向性沉積係為了建立遮罩而執行。之後，可執行進一步的製程。
圖8A是用以說明一比較例中之遮罩損耗的圖示。圖8B是用以說明一實施例中透過異向性沉積建立遮罩的圖示。
在圖8A的樣本基板S上，依序形成有底層ML、抗反射塗層(SiARC)和光阻遮罩PR。此外，一保護膜PF形成在光阻遮罩PR上。在圖8A的示例中，例如DCS的技術(圖12)係用來形成保護膜PF。之後，執行再沉積製程。
此處，再沉積製程包括沉積步驟和濺射步驟。如果在隨後的濺射步驟中所要濺射的材料已存在於圖案上，則可以省略沉積步驟。首先，在沉積步驟中，通過諸如化學氣相沉積(CVD)的沉積技術在圖案上形成沉積物。之後，在濺射步驟中，使處理氣體的加速離子轟擊基板上的圖案。舉例來說，處理氣體是例如氬氣(Ar)的稀有氣體。轟擊會使圖案中的沉積物顆粒從圖案中噴出，然後再次沉積在圖案的附近表面上。此處，如果圖案包括孔，當孔相對較大時，沉積物顆粒可從孔中跳脫出；而當孔相對較小時，沉積物顆粒可沉積在孔的側壁上。此再沉積技術可用來達成例如X＞Y的收縮。儘管以再沉積作為一個示例進行了說明，其他技術也可用於X-Y之控制。
如圖8A的(2)所示，參照圖8A，當在圖8A的(1)的樣本基板上執行再沉積製程時，光阻遮罩PR的頂緣和抗反射塗層(SiARC)的一部分被蝕刻掉，且光阻遮罩PR的理想矩形截面變成梯形。
圖8B是用以說明一實施例中透過異向性沉積建立遮罩的圖示。使用相似於圖8A中的基板，首先，如在圖8A的示例中那樣，採用DCS來形成保護膜PF。之後，從保護膜PF的上方執行本實施例的異向性沉積。所得之圖案顯示在圖8B的(1)中。從圖8的(1)可清楚看見，藉由異向性沉積大大增加了遮罩的高度，並且很好地保留了原來的光阻遮罩PR。之後，在相同於圖8A的條件下執行再沉積。無論再沉積結果如何，光阻遮罩PR的矩形截面實質不變，且濺射的沉積顆粒主要沉積在抗反射塗層(SiARC)的側壁上(圖8B的(2))。因此，在遮罩高度大大地增加的同時，實質上維持了光阻遮罩PR的形狀。因此，根據一實施例，即使為了實現期望的X-Y CD而多次執行再沉積製程，仍可防止遮罩損耗和圖案的變形。加強蝕刻選擇性
當遮罩的高度透過異向性沉積而增加時，圖案的蝕刻選擇性也改善了。
圖9顯示根據一實施例之異向性沉積所形成之膜的蝕刻選擇性。圖9中，將藉由異向性沉積形成之遮罩的蝕刻選擇性(圖9中的「TOPDEPO」)與藉由EUV微影成像法形成之光阻遮罩(見圖8A的PR)的蝕刻選擇性(圖9中的「EUV」)及藉由DCS形成之膜(見圖8A的PF)的蝕刻選擇性(圖9中的「DCS」) 相比較。當在光阻遮罩PR上使用CF4 執行10秒蝕刻時，約20nm的光阻遮罩PR被去除。另一方面，以本實施例的異向性沉積形成的遮罩之被去除量約為10nm。因此，無需任何特殊處理，以本實施例的異向性沉積形成的遮罩比EUV光阻遮罩PR具有更高的蝕刻選擇性。此外，當使用氬氣代替CF4 執行120秒蝕刻時，結果大致相同。
因此，當執行一實施例的異向性沉積時，可維持圖案的CD且增強遮罩的高度及遮罩的品質(蝕刻選擇性)。X-Y CD 控制
圖10A顯示透過根據一實施例之比較性製程及例示性製程獲得之生成圖案的樣本。圖10B是圖10A之實驗所得結果的圖形。
在圖10A的示例(1)中，圖案(見「初始」)受到了DCS和為了X-Y CD控制的再沉積製程。從圖10A中可看出，再沉積導致橢圓形圖案變薄。當施加電壓為200(脈波)+200W時，遮罩圖案被堵塞了，而當施加電壓為3300+200W時，孔消失了(遮罩破裂)。
另一方面，在圖10A的示例(2)中，圖案受到了一實施例的異向性沉積，之後接受為了X-Y CD控制的再沉積製程。從圖10A的(2)中可看出，不管施加的電壓值為何，橢圓形的孔保持其形狀。此外，CD保持不變且X/Y比得到良好控制。
如圖10B所示，遮罩的堵塞和遮罩的破裂發生在比較例(1)中。當相同的製程條件(施加於腔室中的電極的電壓)下採用了實施例中的異向性沉積時，相較於比較例來說，ΔX/ΔY的比值高得多而CD相對完整。因此，證實了實施例的異向性沉積適用於改善X-Y CD的可控性。
這裡，X-Y CD控制是指在兩個正交方向上(即X方向和Y方向上)控制圖案的臨界尺寸。舉例來說，當包括了多個具有橢圓形水平截面的孔的圖案形成時，橢圓形的一個軸(例如X方向上的軸)可以短於另一個軸(例如Y方向上的軸)。
將圖案之Y方向上的尺寸減至小於圖案之X方向上的尺寸的控制稱為「X＜Y收縮」或「X＜Y控制」；將圖案之X方向上的尺寸減至小於圖案之Y方向上的尺寸的控制稱為「X＞Y收縮」或「X＞Y控制」；以及將圖案之X方向上的尺寸和Y方向上的尺寸減小大約相同量的控制稱為「X=Y收縮」或「X=Y控制」。LCDU 改善
發明人證實，當在EUV遮罩上執行平衡電漿製程時，LCDU得到改善。圖11顯示透過根據一實施例之例示性製程所獲得的LCDU之改善效果。
在圖11的示例(1)中，厚度為70nm的旋塗碳(SOC)層形成在矽(Si)基板上。之後，厚度為10nm的SiARC膜形成在SOC層上。在SiARC膜上，形成了厚度為35nm的EUV遮罩。在經過顯影後對LCDU(3σ)和CD檢查時，發現CD為28.87nm且LCDU為3.59。在經過平衡電漿製程和後續的蝕刻後，發現CD為27.05nm而LCDU為2.01。因此，在CD沒有很大收縮的情況下，LCDU得到了改善。在圖11的示例(2)中，SOC層和SiARC膜的厚度分別改變為130nm和20nm。在經過顯影的初始狀態下，CD為25.33nm且LCDU為4.35。在經過平衡電漿製程和後續的蝕刻後，CD為25.45nm且LCDU為2.97。因此，在兩個樣本中，LCDU都得到了改善而CD卻沒有很大的收縮。直流電疊加 (DCS)
保護膜200(見圖1的步驟S102和圖2B)可以使用DCS形成。圖12是用以說明DCS的一個機制的圖示。DCS是藉由將負的直流電電壓施加在電漿腔室中的上電極來處理基板的技術，藉此使包含在上電極中的材料，例如矽，掉落到位於上電極下方的基板上。DCS可以根據例如美國專利申請第2018/0151333號所描述的技術來執行。
DCS可用於在晶圓上形成膜。DCS也可例如使用H2 /N2 的處理氣體來用於固化遮罩103。在本實施例中，DCS被用來在遮罩103上形成保護膜200。為了保護膜200的沉積，可以在基板的上方進一步佈置靶材。例示性的設備
為了實現實施例中的異向性沉積，執行異向性沉積的電漿處理設備較佳係包括一個從上部結構(即上部電極)產生電壓的機構。當用於電漿生成的射頻電壓從下部結構施加時，沉積物傾向於被輸送到圖案的底部。因此，為了實現實施例中的異向性沉積，較佳係使用諸如感應耦合電漿(ICP)設備、電容耦合電漿(CCP)設備及類似的設備。
圖13顯示一個電容耦合電漿(CCP)型之電漿系統。圖13的系統包括腔室1、上電極3和下電極4。RF功率從RF源6、7耦合到上電極3和下電極4。功率耦合可以包括不同的RF頻率6、7。下電極4包括一個用於支撐及固持基板W的靜電吸盤(ESC)5。氣體源8連接至腔室1以供應處理氣體至腔室1中。一個例如渦輪分子泵(TMP)的排氣裝置9連接到腔室1以排空腔室1。隨著RF功率被供應到上電極3和下電極4中的至少一個，電漿2形成於上電極3和下電極4之間靠近基板W處。或者，多個RF功率源6、7可以耦合到同一電極。此外，可變直流(DC)電源10可以耦合到上電極3。
圖14顯示一個電感耦合電漿(ICP)型之電漿系統。該系統包括一腔室11、介電窗21和下電極14。一電感元件(線圈)20佈置在介電窗21的上方。RF功率從RF源16、17耦合到電感元件20和下電極14。功率耦合可以包括不同的RF頻率16、17。下電極14包括一個用以支撐和固持基板W的靜電吸盤(ESC)15。一氣體源18連接到腔室11以供應處理氣體至腔室11內。一個例如渦輪分子泵(TMP)的排氣裝置19連接至腔室11以排空腔室11。隨著RF功率供應至介電窗21和下電極14中的至少一個時，電漿12形成於介電窗21和下電極14間靠近基板W處。
在為了X-Y CD控制而形成保護膜200之前可以執行平衡電漿製程。
儘管為了本發明的完整且清楚揭示，已就具體實施例進行了描述，後附的申請專利範圍不因此受限而是將被解釋成涵蓋所屬技術領域之通常知識者能想到的在一定程度上落入本文所提出的基本教示的所有變化例及替代結構。
1:腔室 2:電漿 3:上電極 4:下電極 5:靜電吸盤 6:RF源 7:RF源 8:氣體源 9:排氣裝置 10:直流電源 11:腔室 12:介電窗 14:下電極 15:靜電吸盤 16:RF源 17:RF源 18:氣體源 19:排氣裝置 20:電感元件 101:底層 102:抗反射塗層 103:遮罩 104:層 200:保護膜 S101~S106:步驟
藉由參照底下的詳細描述並當結合所附圖式來思考，將更容易獲得本申請及其許多附帶優點之更完整的理解，其中：
圖1是根據一實施例之基板處理的一例示性製程的流程圖； 圖2A至2D是根據一實施例之製造半導體元件之一例示性製程的說明示意圖； 圖3顯示根據一實施例之異向性沉積的一個機制； 圖4是用以說明根據一實施例的異向性沉積的圖表； 圖5顯示根據一實施例之實驗結果； 圖6顯示有關欲處理之圖案之側壁部的氣體黏滯係數和該圖案之深寬比之間的關係； 圖7顯示一圖案之底部的離子密度和深寬比的關係； 圖8A是用以說明一比較例中的遮罩損耗的圖示； 圖8B是用以說明一實施例中透過異向性沉積建立遮罩的圖示； 圖9顯示根據一實施例之異向性沉積所形成的膜的蝕刻選擇性； 圖10A顯示透過根據一實施例之比較性的製程及例示性的製程獲得的生成圖案的樣本； 圖10B是圖10A之實驗所獲得結果的圖形； 圖11顯示透過根據一實施例之例示性製程所獲得的LCDU之改善效果； 圖12是用以說明一個DCS機制的圖示； 圖13顯示一個電容耦合電漿(CCP)型之電漿系統之一個示意結構；及 圖14顯示一個電感耦合電漿(ICP)型之電漿系統。
S101~S106:步驟

Claims (16)

  1. 一種電漿腔室內的基板處理方法，包含： 提供一基板，於該基板上將蝕刻一底層且形成一遮罩； 形成一保護膜於該遮罩上；及 執行異向性沉積以選擇性地在該遮罩的頂部形成一沉積層。
  2. 如請求項1之電漿腔室內的基板處理方法，其中該形成該保護膜的步驟係通過施加一直流電至該電漿腔室的一上電極而引起配置於該基板上方之一靶材的濺射、或通過執行原子層沉積(ALD)、物理氣相沉積(PVD)及化學氣相沉積(CVD)中的至少其一來形成包含矽的該保護膜。
  3. 如請求項1之電漿腔室內的基板處理方法，其中該形成該保護膜的步驟形成厚度為至少一原子層的該保護膜。
  4. 如請求項1之電漿腔室內的基板處理方法，其中該提供該基板的步驟提供其上形成一有機材料之該遮罩的該基板；且形成該保護膜的步驟形成一無機材料或金屬的該保護膜。
  5. 如請求項1之電漿腔室內的基板處理方法，其中該提供該基板的步驟提供其上形成包含金屬之該遮罩的該基板。
  6. 如請求項1之電漿腔室內的基板處理方法，其中該提供該基板的步驟提供其上形成包含鎢(W)或鈦(Ti)之該遮罩的該基板。
  7. 如請求項1之電漿腔室內的基板處理方法，其中該執行該異向性沉積的步驟通過將該基板暴露於生成自包含Cx Hy 及N2 、O2 、H2 及F中的至少其一之一處理氣體的電漿來執行該異向性沉積。
  8. 如請求項1之電漿腔室內的基板處理方法，更包含： 在該異向性沉積之後，通過依序將該基板暴露於生成自用以引發沉積之一第一氣體的電漿及生成自用以引發濺射及蝕刻中的至少其一之一第二氣體的電漿來調整該基板上一圖案的尺寸。
  9. 如請求項8之電漿腔室內的基板處理方法，其中該第一氣體包含Si、Cx Hy Fz 及N2 或O2 ，且該第二氣體包含He、Ne、Ar、Kr、Xe及N2 中的至少其一。
  10. 如請求項8之電漿腔室內的基板處理方法，其中該第一氣體包含Si、Cx Hy Fz 及N2 或O2 ，且該第二氣體包含Cx Hy Fz 。
  11. 如請求項1之基板處理方法，更包含： 在該異向性沉積之後，從該遮罩的上方蝕刻該底層。
  12. 如請求項11之電漿腔室內的基板處理方法，其中該異向性沉積及該蝕刻係在相同的該電漿腔室內或在相同的系統內執行。
  13. 一種電漿腔室內的基板處理方法，包含： 提供一基板，於該基板上將蝕刻一底層且形成一遮罩；及 以一預定速率將該基板暴露於生成自包含Cx Hy Fz 及N2 、O2 、H2 及F中的至少其一之一處理氣體的電漿，其中(i)x是不小於1的自然數，y是不小於1的自然數且z是0或不小於1的自然數，或(ii)x是不小於1的自然數，y是0或不小於1的自然數且z是不小於1的自然數。
  14. 如請求項13之電漿腔室內的基板處理方法，其中該預定速率的決定係使得所導致的蝕刻實質上被所導致的沉積抵銷。
  15. 一種電漿腔室內的基板處理方法，包含： 提供一基板，於該基板上將蝕刻一底層且形成一遮罩； 以一預定速率將該基板暴露於生成自包含Cx Hy Fz 及N2 、O2 、H2 及F中的至少其一之一處理氣體的電漿，其中(i)x是不小於1的自然數，y是不小於1的自然數且z是0或不小於1的自然數，或(ii)x是不小於1的自然數，y是0或不小於1的自然數且z是不小於1的自然數； 形成一保護膜於該遮罩上；及 執行異向性沉積以選擇性地在該遮罩的頂部形成一沉積層。
  16. 如請求項15之電漿腔室內的基板處理方法，更包含： 在該異向性沉積之後，調整該基板上一圖案的尺寸。
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