TW201732876A - 形成圖案的方法 - Google Patents

形成圖案的方法 Download PDF

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TW201732876A
TW201732876A TW105110842A TW105110842A TW201732876A TW 201732876 A TW201732876 A TW 201732876A TW 105110842 A TW105110842 A TW 105110842A TW 105110842 A TW105110842 A TW 105110842A TW 201732876 A TW201732876 A TW 201732876A
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pattern
hard mask
forming
layer
pitch
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TWI651757B (zh
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周國耀
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美光科技公司
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

一種形成圖案的方法。首先提供一基材，具有一目標材料層，再於目標材料層上形成第一硬遮罩層、第二硬遮罩層及光阻層，再進行一微影製程，於第二硬遮罩層形成第一圖案；蝕刻掉未被第一圖案保護的第二硬遮罩層，形成第二圖案，再整修第二硬遮罩層上的第一圖案，形成整修特徵結構，接著在修整特徵結構的側壁上自我對準形成複數個第一側壁子，在第二圖案的側壁上自我對準形成複數個第二側壁子，再將修整特徵結構去除，然後進行一非等向性乾蝕刻製程，蝕刻未被第一側壁子保護到的第二圖案，形成複數個圖案，具有更小且更密的節距。

Description

形成圖案的方法
本發明係有關於半導體裝置製造技術，更特定言之，本發明係有關於一種形成圖案的方法，該圖案具有更小且更密的節距（pitch）。
隨著電子消費性產品蓬勃的發展，消費者對於電子產品的可攜性、運算能力、記憶體容量及能源效率的需求也愈大，驅使此類電子產品朝向更小尺寸且設計更精密的方向發展。
隨著特徵結構尺寸不斷的縮減，使得業界對形成積體電路中特徵結構之相關製程技術有更大的需求，例如，積體電路中特徵結構通常是利用光學微影技術來進行圖案轉移。由於微影技術通常藉由將光或輻射投射至一表面上，因此特定微影技術的最終解析度取決於諸如光學元件及光或輻射波長等因素。
在許多應用中，常常需要將特徵結構，例如線寬和間隔，盡可能地縮小。較小的線寬或圖案週期意味著更高的性能和/或更高密度的電路。因此，該技術領域仍在持續的探索，以達到光微影系統的最高解析，從而降低圖案化基底的線寬或圖案週期。
由此可知，目前該技術領域仍需要有一種改良的方法，能夠利用常規的光微影系統，製造出特徵結構尺寸小於所述光微影系統微影極限的次微影尺寸的線和間距圖案。
本發明涉及提供一種形成圖案的方法，其能夠克服目前光學微影技術的限制及瓶頸，並提升半導體製程的圖案解析能力。
根據本發明實施例，提供一種形成圖案的方法，包含：提供一基材，其上具有一目標材料層；於該目標材料層上形成一第一硬遮罩層、一第二硬遮罩層及一光阻層；進行一微影製程，將該光阻層轉變成位於該第二硬遮罩層上的一第一圖案，該第一圖案具有一節距P1 ；蝕刻掉未被該第一圖案保護到的該第二硬遮罩層的區域，如此形成一第二圖案，其符合且對準該第一圖案；進行一光阻整修步驟，僅整修位於該第二硬遮罩層上的該第一圖案，形成整修特徵結構；在該修整特徵結構的上表面及側壁、該第二圖案的上表面及側壁，及該第一硬遮罩層的顯露出的上表面，順應的沉積一側壁子材料層；非等向性蝕刻該側壁子材料層，如此在該修整特徵結構的側壁上自我對準形成複數個第一側壁子，並在該第二圖案的側壁上自我對準形成複數個第二側壁子；將該修整特徵結構去除；以及進行一非等向性乾蝕刻製程，蝕刻未被該第一側壁子保護到的該第二圖案的區域，如此形成複數個圖案，其具有更小且更密的節距P2 ，其為節距P1 的四分之一。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明實施例細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節，使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
因此，下文的細節描述將不被視為一種限定，且本發明所涵蓋之範疇僅被所附之申請專利範圍以及其同意義的涵蓋範圍。
本發明之一或多個實施例將參照附圖描述，其中，相同元件符號始終用以表示相同元件，且其中闡述的結構未必按比例所繪製。
文中所使用的術語「基材」包括任何具有暴露表面之結構，於所述表面上根據本發明沉積一層，例如，形成積體電路（integrated circuit，IC）結構。「基材」被理解為包括半導體晶圓。「基材」亦可用以指加工過程中之半導體結構，且可包括已被製造在其上之其他層。「基材」包括摻雜及未摻雜半導體、由基底半導體或絕緣體支撐的磊晶半導體層（epitaxial semiconductor layers），以及其他本發明所屬領域具有通常知識者所熟知的半導體結構。
文中所使用的術語「水平」是指平行於基材或基板的常規主平面或表面，而不管其方向。術語「垂直」是指垂直所述水平的方向。術語「上」、「上方」及「下」是指相對於水平面。
術語“臨界尺寸（CD）”泛指積體電路製作過程中某技術節點下所能製作出的最小幾何特徵尺寸，例如內連線、接觸結構或溝槽的寬度。
術語“節距加倍（pitch doubling）”或“節距倍增（pitch multiplication）”通常是指一種半導體製程方法，用於延伸光學微影技術的曝光極限能力，使其最終圖案能超過該光學微影技術所能形成的最小節距。節距的概念可以用於描述的關鍵的電路特徵尺寸，諸如細密的導線。節距被定義為在兩個相鄰特徵相同點之間的距離。
這些特徵結構通常由相鄰特徵結構間的空間定義出間距，其中該些空間通常由如絕緣體的材料所填充。因此，節距可以被視為所述一特徵結構的寬度與相鄰特徵結構的一間距的總和。通常，節距“倍增”實際上涉及通過某因子而縮減的節距。在本文中保留上述常規的術語。
本發明關於一種節距倍增方法，涉及單次光學微影步驟與光阻修整步驟，以定義臨界尺寸，隨後形成自我對準側壁子來實現節距倍增。
請參閱第1圖至第10圖，其為依據本發明實施例所繪示的一種形成具有更小且更密節距的圖案的方法的示意圖。如第1圖所示，提供一基材10。根據本發明實施例，基材10可以是半導體基材，例如矽基材、矽鍺（SiGe）基材、矽覆絕緣（silicon-on-insulator，SOI）基材、磊晶矽基材等等。在基材10的主表面上形成有一目標材料層11。根據本發明實施例，目標材料層11可以是一介電層、一多晶矽層或一金屬層，但不限於此。本發明的主要目的係在目標材料層11中形成細節距圖案。
根據本發明實施例，在目標材料層11上形成有一第一硬遮罩層12。在第一硬遮罩層12上形成有一第二硬遮罩層13。第一硬遮罩層12可以包含多晶矽、氧化矽、氮化矽或含碳材料，但不限於此。在某些實施例中，第一硬遮罩層12可以包含金屬。第二硬遮罩層13可以包含相對於第一硬遮罩層12具高蝕刻選擇比的抗蝕材料。
舉例來說，第二硬遮罩層13可以包括，但不限於，商業上可獲得的日本信越化學有限公司（Shin-Etsu Chemical Company, Ltd.）生產的旋塗高分子材料（spin-on polymer material），商品名ODL系列，例如ODL301。第二硬遮罩層13可以在後續圖案轉移的蝕刻製程中提供出額外的蝕刻抵擋能力。
根據本發明實施例，在第二硬遮罩層13形成一光阻層14。根據本發明實施例，光阻層14可以包含一光敏含矽抗蝕劑，例如，I-line光阻，但不限於此。光阻層14可以包含不同的光阻化學成分，以適合微影製程應用。光阻層14對預定光源發出的電磁輻射能產生預定的光化學反應。光阻層14可以是化學放大的正調（正片）或負調（負片）有機光阻劑。根據本發明實施例，光阻層14相對於第二硬遮罩層13具有高蝕刻選擇比。
如第2圖所示，接著進行一微影製程，於第二硬遮罩層13上形成第一圖案14a，例如線型圖案。所述微影製程通常涉及紫外線或深紫外線的曝光、後續的烘烤，如此誘發光化學反應，改變光阻層14中經過曝光區域的溶解度（對特定顯影液）。接著，利用一合適的顯影液，通常為鹼性水溶液，選擇性的去除光阻層14中經過曝光區域（對正調光阻而言）。
此時，第一圖案14a具有一節距P1 ，其為各個第一圖案14a的線寬L1 與兩相鄰第一圖案14a的間距S1 的總和。根據本發明實施例，L1 ：S1 = 5：3。
如第3圖所示，接著進行一非等向性乾蝕刻製程，蝕除第二硬遮罩層13中未被第一圖案14a保護到的區域，如此形成第二圖案13a，其基本上符合並對準第一圖案14a。此時，由於對第二硬遮罩層13具高蝕刻選擇比，下方的第一硬遮罩層12基本上不會被蝕刻。
如第4圖所示，接著進行一光阻修整步驟，僅修整在第二圖案13a上的第一圖案14a，以形成修整特徵結構14b。上述光阻修整步驟可以包含一電漿蝕刻製程。使第一圖案14a暴露於電漿蝕刻劑中，以修整或縮減形成在第二圖案13a上的特徵結構的尺寸。上述電漿蝕刻劑可以包含各種的電漿蝕刻化學成分，例如O2 、HBr/O2 、Cl2 /O2 、N2 /He/O2 或N2 /O2 ，但不限於此。修整特徵結構14b具有一橫向尺寸或一特徵尺寸（critical dimension，CD）。
如第5圖所示，在修整特徵結構14b的上表面及側壁、第二圖案13a的上表面及側壁，及第一硬遮罩層12的顯露出的上表面，順應的沉積一側壁子材料層16。根據本發明實施例，側壁子材料層16可以是一矽氧層，其可以利用一化學氣相沉積（chemical vapor deposition，CVD）製程或原子層沉積（atomic layer deposition，ALD）製程形成。然而，需理解的是，也可以採用其它側壁子材料。
如第6圖所示，非等向性蝕刻側壁子材料層16，如此在修整特徵結構14b的側壁上自我對準形成複數個側壁子16a，並在第二圖案13a的側壁上自我對準形成複數個側壁子16b。
接著，如第7圖所示，將修整特徵結構14b選擇性的去除，留下側壁子16a、側壁子16b及第二圖案13a。去除修整特徵結構14b的方式可以利用常用的濕式清洗方法，例如稀釋氫氟酸溶液（diluted HF solution），或者利用習知的光阻去除方法，但不限於此。在去除修整特徵結構14b之後，在各個第二圖案13a上的兩個相鄰側壁子16a之間形成一間隙18a。此間隙18a的尺寸大小基本上等同於已去除的修整特徵結構14b的臨界尺寸。
如第8圖所示，利用第二圖案13a上的側壁子16a作為遮罩，進行一非等向性乾蝕刻製程，蝕刻未被側壁子16a保護到的第二圖案13a的區域，如此形成複數個圖案160，其具有更小且更密的節距P2 ，其約為原先節距P1 的四分之一。蝕刻後，剩餘的第二圖案13b係分別直接位於側壁子16a正下方。根據本發明實施例，圖案160可以是密集排列的線型圖案，且具有相等的線寬及間距。
接著，如第9圖所示，利用所形成的具有更小且更密的節距P2 的複數個圖案160作為硬遮罩，再進行一非等向性乾蝕刻製程，將圖案160轉移至第一遮罩層12，如此形成硬遮罩圖案12a，其同樣具有該更小且更密的節距P2 。
最後，如第10圖所示，再利用該具有更小且更密的節距P2 的硬遮罩圖案12a作為蝕刻硬遮罩，進行另一次的非等向性乾蝕刻製程，將硬遮罩圖案12a轉移至下方的目標材料層11中，即完成目標圖案11a，其同樣具有該更小且更密的節距P2 。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧基材
11‧‧‧目標材料層
11a‧‧‧目標圖案
12‧‧‧第一硬遮罩層
12a‧‧‧硬遮罩圖案
13‧‧‧第二硬遮罩層
13a‧‧‧第二圖案
13b‧‧‧剩餘的第二圖案
14‧‧‧光阻層
14a‧‧‧第一圖案
14b‧‧‧修整特徵結構
16‧‧‧側壁子材料層
16a、16b‧‧‧側壁子
18a‧‧‧間隙
160‧‧‧圖案
CD‧‧‧臨界尺寸
P1、P2‧‧‧節距
L1‧‧‧線寬
S1‧‧‧間距
所附圖式係提供用以方便對本發明更進一步的了解，其構成本說明書的一部分。所附圖式與說明書內容一同闡述之本發明實施例，有助於解釋本發明的原理原則。在圖式中：         第1圖至第10圖為依據本發明實施例所繪示的一種形成具有更小且更密節距的圖案的方法的示意圖。   應當注意的是，所有的圖式皆為概略性的。為方便和在圖紙上清晰起見，圖式之相對尺寸和部分零件比例係以誇大或縮小規模呈現。相同的標號一般係用來於不同的實施例中指示相對應或類似的元件。
10‧‧‧基材
11‧‧‧目標材料層
12‧‧‧第一硬遮罩層
13b‧‧‧剩餘的第二圖案
16a、16b‧‧‧側壁子
160‧‧‧圖案
P1、P2‧‧‧節距
L1‧‧‧線寬
S1‧‧‧間距

Claims (13)

  1. 一種形成圖案的方法，包含：       提供一基材，其上具有一目標材料層；       於該目標材料層上形成一第一硬遮罩層、一第二硬遮罩層及一光阻層；       進行一微影製程，將該光阻層轉變成位於該第二硬遮罩層上的一第一圖案，該第一圖案具有一節距P1 ；       蝕刻掉未被該第一圖案保護到的該第二硬遮罩層的區域，如此形成一第二圖案，其符合且對準該第一圖案；       進行一光阻整修步驟，僅整修位於該第二硬遮罩層上的該第一圖案，形成整修特徵結構；       在該修整特徵結構的上表面及側壁、該第二圖案的上表面及側壁，及該第一硬遮罩層的顯露出的上表面，順應的沉積一側壁子材料層； 非等向性蝕刻該側壁子材料層，如此在該修整特徵結構的側壁上自我對準形成複數個第一側壁子，並在該第二圖案的側壁上自我對準形成複數個第二側壁子； 將該修整特徵結構去除；以及 進行一非等向性乾蝕刻製程，蝕刻未被該第一側壁子保護到的該第二圖案的區域，如此形成複數個圖案，其具有更小且更密的節距P2 ，其為節距P1 的四分之一。
  2. 如申請專利範圍第1項所述的形成圖案的方法，其中該第一硬遮罩層包含多晶矽、氧化矽、氮化矽、含碳材料或金屬。
  3. 如申請專利範圍第2項所述的形成圖案的方法，其中該第二硬遮罩層包含一旋塗高分子材料。
  4. 如申請專利範圍第3項所述的形成圖案的方法，其中該光阻層包含I-line光阻。
  5. 如申請專利範圍第1項所述的形成圖案的方法，其中該第一圖案為線型圖案，具有該節距P1 。
  6. 如申請專利範圍第1項所述的形成圖案的方法，其中該光阻修整步驟包含一電漿蝕刻製程。
  7. 如申請專利範圍第1項所述的形成圖案的方法，其中該修整特徵結構具有一臨界尺寸。
  8. 如申請專利範圍第1項所述的形成圖案的方法，其中該側壁子材料層包含一矽氧層。
  9. 如申請專利範圍第1項所述的形成圖案的方法，其中該修整特徵結構係利用一濕式清洗方法去除。
  10. 如申請專利範圍第1項所述的形成圖案的方法，其中剩餘的該第二圖案係分別直接位於該第一側壁子正下方。
  11. 如申請專利範圍第1項所述的形成圖案的方法，其中該複數個圖案是密集排列的線型圖案，且具有相等的線寬及間距。
  12. 如申請專利範圍第1項所述的形成圖案的方法，其中另包含： 利用該具有更小且更密的節距P2 的複數個圖案作為硬遮罩，進行一非等向性乾蝕刻製程，將該圖案轉移至該第一遮罩層，如此形成一硬遮罩圖案，其同樣具有該更小且更密的節距P2 。
  13. 如申請專利範圍第12項所述的形成圖案的方法，其中另包含： 利用該具有更小且更密的節距P2 的硬遮罩圖案作為蝕刻硬遮罩，進行另一次的非等向性乾蝕刻製程，將該硬遮罩圖案轉移至下方的該目標材料層中，形成一目標圖案，其同樣具有該更小且更密的節距P2 。
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