JP4619839B2 - パターン形成方法 - Google Patents
パターン形成方法 Download PDFInfo
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- JP4619839B2 JP4619839B2 JP2005075143A JP2005075143A JP4619839B2 JP 4619839 B2 JP4619839 B2 JP 4619839B2 JP 2005075143 A JP2005075143 A JP 2005075143A JP 2005075143 A JP2005075143 A JP 2005075143A JP 4619839 B2 JP4619839 B2 JP 4619839B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16L—PIPES; JOINTS OR FITTINGS FOR PIPES; SUPPORTS FOR PIPES, CABLES OR PROTECTIVE TUBING; MEANS FOR THERMAL INSULATION IN GENERAL
- F16L15/00—Screw-threaded joints; Forms of screw-threads for such joints
- F16L15/006—Screw-threaded joints; Forms of screw-threads for such joints with straight threads
- F16L15/007—Screw-threaded joints; Forms of screw-threads for such joints with straight threads with more than one threaded section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Electrodes Of Semiconductors (AREA)
Description
光リソグラフィ技術では、光の回折効果のために光の波長で決まる解像限界があるため、半導体装置の高集積化に伴って要求されている解像限界以下の微細なパターンを形成することが困難である。
次に、図3に示すように、光リソグラフィ法により、レジスト膜14に露光装置に用いる光の波長による解像限界に近いライン幅L1、例えば60nm程度、とライン幅L1に略等しいスペース幅S1を有する第1のパターン15を形成する。
即ち、第1のパターン15のラインをスリミング幅L3が、例えばL1/4の15nm程度になるようにエッチングすることにより、ライン幅L2がライン幅L1の1/2の30nm程度、スペース幅S2がスペース幅S1の3/2の90nm程度の第1のパターン16が得られる。
この際、第2のパターン17のライン側壁の膜厚T1が第2のパターン17のライン幅L2の30nmに略等しくなるようにする。その結果、第2のパターン17の隣接するライン17a、17b間の隙間S3も第2のパターン17のスペース幅S2の1/3の30nmとなり、ライン幅L2と略等しくなる。
これにより、TEOS膜12とポリシリコン膜13が順に積層された第1のライン20aと、TEOS膜12とBSG膜18とポリシリコン膜19が順に積層された第2のライン20bがゲート電極膜10の表面に隣接して形成され、ライン幅L2、ライン幅L2に略等しいスペース幅S3を有する第3のパターン20が得られる。
10 ゲート電極膜
11 シリコン基板
12 TEOS膜(第1の膜)
13 ポリシリコン膜(第2の膜)
14 レジスト膜
15、16 第1のパターン
17 第2のパターン
18 BSG膜(第3の膜)
19 ポリシリコン膜(第4の膜)
20、30 第3のパターン
21 表面
22 段差
Claims (5)
- 基板の主面に第1および第2の膜を順に形成する工程と、
前記第2の膜上にレジスト膜を形成し、前記レジスト膜をパターニングして第1のパターンを形成する工程と、
前記第1のパターンをエッチングして、前記第1のパターンのラインの幅を細くする工程と、
前記第1のパターンをマスクとして前記第2の膜をエッチングし、前記第1のパターンが転写された第2のパターンを形成する工程と、
前記第2のパターンを被覆するように前記基板全面に所定の厚さの第3の膜を形成する工程と、
前記被覆された第2のパターンのラインの隙間に第4の膜を埋め込む工程と、
前記埋め込まれた第4の膜の両側の前記第3の膜、および前記第3の膜の下層にある前記第1の膜をエッチングして第3のパターンを形成する工程と、
を具備することを特徴とするパターン形成方法。 - 前記第1および第3の膜が、前記第2および第4の膜と異なるエッチング選択比を有することを特徴とする請求項1に記載のパターン形成方法。
- 前記第1および第3の膜がシリコン酸化膜またはシリコン窒化膜であり、前記第2および第4の膜がシリコン膜であることを特徴とする請求項1に記載のパターン形成方法。
- 前記第3の膜の厚さが、前記第2のパターンのラインの幅に略等しいことを特徴とする請求項1に記載のパターン形成方法。
- 前記エッチング後の第1のパターンのラインの幅が、前記エッチング前の第1のパターンのラインの幅の1/2に略等しいことを特徴とする請求項1に記載のパターン形成方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005075143A JP4619839B2 (ja) | 2005-03-16 | 2005-03-16 | パターン形成方法 |
US11/373,335 US7312158B2 (en) | 2005-03-16 | 2006-03-13 | Method of forming pattern |
KR1020060023863A KR100759616B1 (ko) | 2005-03-16 | 2006-03-15 | 패턴 형성 방법 및 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005075143A JP4619839B2 (ja) | 2005-03-16 | 2005-03-16 | パターン形成方法 |
Publications (2)
Publication Number | Publication Date |
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JP2006261307A JP2006261307A (ja) | 2006-09-28 |
JP4619839B2 true JP4619839B2 (ja) | 2011-01-26 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005075143A Active JP4619839B2 (ja) | 2005-03-16 | 2005-03-16 | パターン形成方法 |
Country Status (3)
Country | Link |
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US (1) | US7312158B2 (ja) |
JP (1) | JP4619839B2 (ja) |
KR (1) | KR100759616B1 (ja) |
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JPH0590603A (ja) * | 1991-09-26 | 1993-04-09 | Nippon Steel Corp | 不揮発性半導体メモリの製造方法 |
JPH10284489A (ja) * | 1997-04-11 | 1998-10-23 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002280388A (ja) * | 2001-03-15 | 2002-09-27 | Toshiba Corp | 半導体装置の製造方法 |
JP2004152784A (ja) * | 2002-10-28 | 2004-05-27 | Fujitsu Ltd | 微細パターンの作製方法及び半導体装置の製造方法 |
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JP2006261307A (ja) | 2006-09-28 |
US20060216938A1 (en) | 2006-09-28 |
KR100759616B1 (ko) | 2007-09-17 |
US7312158B2 (en) | 2007-12-25 |
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