JP2006261307A - パターン形成方法 - Google Patents
パターン形成方法 Download PDFInfo
- Publication number
- JP2006261307A JP2006261307A JP2005075143A JP2005075143A JP2006261307A JP 2006261307 A JP2006261307 A JP 2006261307A JP 2005075143 A JP2005075143 A JP 2005075143A JP 2005075143 A JP2005075143 A JP 2005075143A JP 2006261307 A JP2006261307 A JP 2006261307A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- film
- etching
- films
- forming method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16L—PIPES; JOINTS OR FITTINGS FOR PIPES; SUPPORTS FOR PIPES, CABLES OR PROTECTIVE TUBING; MEANS FOR THERMAL INSULATION IN GENERAL
- F16L15/00—Screw-threaded joints; Forms of screw-threads for such joints
- F16L15/006—Screw-threaded joints; Forms of screw-threads for such joints with straight threads
- F16L15/007—Screw-threaded joints; Forms of screw-threads for such joints with straight threads with more than one threaded section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
【解決手段】 シリコン基板11上にTEOS膜12、ポリシリコン膜13を順に形成する工程と、TEOS膜12上にレジスト膜14をパターニングして第1のパターン15を形成する工程と、第1のパターン15をエッチングしてライン幅を細くする工程と、得られた第1のパターン16をマスクとしてポリシリコン膜13をエッチングして第2のパターン17を形成する工程と、第2のパターン17を被覆するように基板11全面に所定の厚さのBSG膜18を形成する工程と、第2のパターン17のライン間の隙間にポリシリコン膜19を埋め込む工程と、ポリシリコン膜19の両側のBSG膜18およびTEOS膜12をエッチングして第3のパターン20を形成する工程と、を具備する。
【選択図】 図9
Description
光リソグラフィ技術では、光の回折効果のために光の波長で決まる解像限界があるため、半導体装置の高集積化に伴って要求されている解像限界以下の微細なパターンを形成することが困難である。
次に、図3に示すように、光リソグラフィ法により、レジスト膜14に露光装置に用いる光の波長による解像限界に近いライン幅L1、例えば60nm程度、とライン幅L1に略等しいスペース幅S1を有する第1のパターン15を形成する。
即ち、第1のパターン15のラインをスリミング幅L3が、例えばL1/4の15nm程度になるようにエッチングすることにより、ライン幅L2がライン幅L1の1/2の30nm程度、スペース幅S2がスペース幅S1の3/2の90nm程度の第1のパターン16が得られる。
この際、第2のパターン17のライン側壁の膜厚T1が第2のパターン17のライン幅L2の30nmに略等しくなるようにする。その結果、第2のパターン17の隣接するライン17a、17b間の隙間S3も第2のパターン17のスペース幅S2の1/3の30nmとなり、ライン幅L2と略等しくなる。
これにより、TEOS膜12とポリシリコン膜13が順に積層された第1のライン20aと、TEOS膜12とBSG膜18とポリシリコン膜19が順に積層された第2のライン20bがゲート電極膜10の表面に隣接して形成され、ライン幅L2、ライン幅L2に略等しいスペース幅S3を有する第3のパターン20が得られる。
10 ゲート電極膜
11 シリコン基板
12 TEOS膜(第1の膜)
13 ポリシリコン膜(第2の膜)
14 レジスト膜
15、16 第1のパターン
17 第2のパターン
18 BSG膜(第3の膜)
19 ポリシリコン膜(第4の膜)
20、30 第3のパターン
21 表面
22 段差
Claims (5)
- 基板の主面に第1および第2の膜を順に形成する工程と、
前記第2の膜上にレジスト膜を形成し、前記レジスト膜をパターニングして第1のパターンを形成する工程と、
前記第1のパターンをエッチングして、前記第1のパターンのラインの幅を細くする工程と、
前記第1のパターンをマスクとして前記第2の膜をエッチングし、前記第1のパターンが転写された第2のパターンを形成する工程と、
前記第2のパターンを被覆するように前記基板全面に所定の厚さの第3の膜を形成する工程と、
前記被覆された第2のパターンのラインの隙間に第4の膜を埋め込む工程と、
前記埋め込まれた第4の膜の両側の前記第3の膜、および前記第3の膜の下層にある前記第1の膜をエッチングして第3のパターンを形成する工程と、
を具備することを特徴とするパターン形成方法。 - 前記第1および第3の膜が、前記第2および第4の膜と異なるエッチング選択比を有することを特徴とする請求項1に記載のパターン形成方法。
- 前記第1および第3の膜がシリコン酸化膜またはシリコン窒化膜であり、前記第2および第4の膜がシリコン膜であることを特徴とする請求項1に記載のパターン形成方法。
- 前記第3の膜の厚さが、前記第2のパターンのラインの幅に略等しいことを特徴とする請求項1に記載のパターン形成方法。
- 前記エッチング後の第1のパターンのラインの幅が、前記エッチング前の第1のパターンのラインの幅の1/2に略等しいことを特徴とする請求項1に記載のパターン形成方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005075143A JP4619839B2 (ja) | 2005-03-16 | 2005-03-16 | パターン形成方法 |
US11/373,335 US7312158B2 (en) | 2005-03-16 | 2006-03-13 | Method of forming pattern |
KR1020060023863A KR100759616B1 (ko) | 2005-03-16 | 2006-03-15 | 패턴 형성 방법 및 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005075143A JP4619839B2 (ja) | 2005-03-16 | 2005-03-16 | パターン形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006261307A true JP2006261307A (ja) | 2006-09-28 |
JP4619839B2 JP4619839B2 (ja) | 2011-01-26 |
Family
ID=37035777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005075143A Active JP4619839B2 (ja) | 2005-03-16 | 2005-03-16 | パターン形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7312158B2 (ja) |
JP (1) | JP4619839B2 (ja) |
KR (1) | KR100759616B1 (ja) |
Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006303500A (ja) * | 2005-04-19 | 2006-11-02 | Samsung Electronics Co Ltd | 微細ピッチのハードマスクを用いた半導体素子の微細パターン形成方法 |
KR100752674B1 (ko) | 2006-10-17 | 2007-08-29 | 삼성전자주식회사 | 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법 |
KR100790999B1 (ko) * | 2006-10-17 | 2008-01-03 | 삼성전자주식회사 | 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법 |
KR100817089B1 (ko) | 2007-02-28 | 2008-03-26 | 삼성전자주식회사 | 이중 패터닝 기술을 이용한 반도체 소자의 미세 패턴 형성방법 |
JP2008118130A (ja) * | 2006-10-23 | 2008-05-22 | Samsung Electronics Co Ltd | 微細コンタクトホールを有する半導体素子の製造方法 |
KR100843241B1 (ko) | 2007-03-29 | 2008-07-02 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
JP2008166700A (ja) * | 2006-12-28 | 2008-07-17 | Hynix Semiconductor Inc | 半導体素子の微細パターン形成方法 |
KR100850146B1 (ko) | 2007-05-07 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
JP2008193098A (ja) * | 2007-02-06 | 2008-08-21 | Samsung Electronics Co Ltd | ダブルパターニング工程を用いる半導体素子の微細パターン形成方法 |
JP2008198991A (ja) * | 2007-02-15 | 2008-08-28 | Hynix Semiconductor Inc | 半導体素子のコンタクトホール形成方法 |
JP2008205470A (ja) * | 2007-02-16 | 2008-09-04 | Samsung Electronics Co Ltd | 半導体素子の微細金属配線パターンの形成方法 |
JP2008244417A (ja) * | 2007-03-23 | 2008-10-09 | Hynix Semiconductor Inc | 半導体素子の微細パターン形成方法 |
JP2008311623A (ja) * | 2007-06-15 | 2008-12-25 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
KR100886219B1 (ko) | 2007-06-07 | 2009-02-27 | 삼성전자주식회사 | 자기정렬된 이중 패터닝을 채택하는 미세 패턴 형성 방법 |
JP2009055022A (ja) * | 2007-08-13 | 2009-03-12 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
JP2009076902A (ja) * | 2007-09-18 | 2009-04-09 | Hynix Semiconductor Inc | 半導体素子の微細パターン形成方法 |
JP2009099792A (ja) * | 2007-10-17 | 2009-05-07 | Toshiba Corp | 半導体装置の製造方法 |
JP2009164576A (ja) * | 2008-01-07 | 2009-07-23 | Samsung Electronics Co Ltd | 半導体素子の微細パターンの形成方法 |
WO2009101878A1 (ja) * | 2008-02-15 | 2009-08-20 | Tokyo Electron Limited | パターン形成方法、半導体製造装置及び記憶媒体 |
KR100939168B1 (ko) * | 2008-02-28 | 2010-01-28 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
KR100942075B1 (ko) | 2007-12-27 | 2010-02-12 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
JP2010080903A (ja) * | 2008-02-15 | 2010-04-08 | Tokyo Electron Ltd | パターン形成方法、半導体装置の製造方法及び半導体装置の製造装置 |
US7892982B2 (en) | 2006-03-06 | 2011-02-22 | Samsung Electronics Co., Ltd. | Method for forming fine patterns of a semiconductor device using a double patterning process |
US7998874B2 (en) | 2006-03-06 | 2011-08-16 | Samsung Electronics Co., Ltd. | Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same |
US8008211B2 (en) | 2007-12-28 | 2011-08-30 | Tokyo Electron Limited | Pattern forming method, semiconductor device manufacturing apparatus and storage medium |
US8173358B2 (en) | 2008-10-09 | 2012-05-08 | Samsung Electronics Co., Ltd. | Method of forming fine patterns of a semiconductor device |
JP2012511253A (ja) * | 2008-12-04 | 2012-05-17 | マイクロン テクノロジー, インク. | 基板作製方法 |
JP2012514339A (ja) * | 2008-12-31 | 2012-06-21 | サンディスク スリーディー,エルエルシー | 柱状構造のためのレジストフィーチャおよび除去可能スペーサピッチを倍増するパターニング法 |
JP2012216846A (ja) * | 2007-12-20 | 2012-11-08 | Sk Hynix Inc | 半導体素子の形成方法 |
US8361904B2 (en) | 2005-04-19 | 2013-01-29 | Samsung Electronics Co., Ltd. | Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same |
US8658526B2 (en) | 2008-12-31 | 2014-02-25 | Sandisk 3D Llc | Methods for increased array feature density |
US8685627B2 (en) | 2007-12-20 | 2014-04-01 | Hynix Semiconductor Inc. | Method for manufacturing a semiconductor device |
WO2014123177A1 (ja) * | 2013-02-08 | 2014-08-14 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の製造方法 |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7897058B2 (en) * | 2006-02-13 | 2011-03-01 | Asml Netherlands B.V. | Device manufacturing method and computer program product |
KR100781542B1 (ko) * | 2006-06-08 | 2007-12-03 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
KR100843948B1 (ko) * | 2006-07-10 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
KR100829606B1 (ko) * | 2006-09-07 | 2008-05-14 | 삼성전자주식회사 | 미세 패턴의 형성 방법 |
KR100761857B1 (ko) * | 2006-09-08 | 2007-09-28 | 삼성전자주식회사 | 반도체 소자의 미세패턴 형성방법 및 이를 이용한 반도체소자의 제조방법 |
KR100818999B1 (ko) * | 2006-10-09 | 2008-04-02 | 삼성전자주식회사 | 마스크 제작 방법 |
JP2008098281A (ja) | 2006-10-10 | 2008-04-24 | Toshiba Corp | 半導体装置の製造方法 |
US7728405B2 (en) | 2007-03-08 | 2010-06-01 | Qimonda Ag | Carbon memory |
US7914975B2 (en) * | 2007-04-10 | 2011-03-29 | International Business Machines Corporation | Multiple exposure lithography method incorporating intermediate layer patterning |
DE102007019761A1 (de) * | 2007-04-19 | 2008-10-23 | Qimonda Ag | Verfahren zur Herstellung eines Kontaktelementes, eine Sturktur in einem Halbleiterbauelement, eine integrierte Schaltung und ein Halbleiterbauelement |
US7906368B2 (en) * | 2007-06-29 | 2011-03-15 | International Business Machines Corporation | Phase change memory with tapered heater |
US20090124084A1 (en) * | 2007-11-14 | 2009-05-14 | Elliot Tan | Fabrication of sub-resolution features for an integrated circuit |
US7863169B2 (en) * | 2007-11-30 | 2011-01-04 | International Business Machines Corporation | Lithography for printing constant line width features |
CN101971291B (zh) * | 2008-02-08 | 2013-04-03 | 朗姆研究公司 | 双掩模自对准双图案化技术(SaDPT)工艺 |
JP2009289974A (ja) * | 2008-05-29 | 2009-12-10 | Toshiba Corp | 半導体装置の製造方法 |
US8133664B2 (en) * | 2009-03-03 | 2012-03-13 | Micron Technology, Inc. | Methods of forming patterns |
KR101029391B1 (ko) * | 2009-06-17 | 2011-04-14 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성방법 |
KR101736983B1 (ko) | 2010-06-28 | 2017-05-18 | 삼성전자 주식회사 | 반도체 소자 및 반도체 소자의 패턴 형성 방법 |
US8932955B1 (en) | 2013-09-04 | 2015-01-13 | Sandisk Technologies Inc. | Triple patterning NAND flash memory with SOC |
US9613806B2 (en) * | 2013-09-04 | 2017-04-04 | Sandisk Technologies Llc | Triple patterning NAND flash memory |
US8969206B1 (en) | 2013-09-04 | 2015-03-03 | Sandisk Technologies Inc. | Triple patterning NAND flash memory with stepped mandrel |
US9224744B1 (en) | 2014-09-03 | 2015-12-29 | Sandisk Technologies Inc. | Wide and narrow patterning using common process |
US9390922B1 (en) | 2015-02-06 | 2016-07-12 | Sandisk Technologies Llc | Process for forming wide and narrow conductive lines |
US9425047B1 (en) | 2015-02-19 | 2016-08-23 | Sandisk Technologies Llc | Self-aligned process using variable-fluidity material |
US9502428B1 (en) | 2015-04-29 | 2016-11-22 | Sandisk Technologies Llc | Sidewall assisted process for wide and narrow line formation |
US9595444B2 (en) | 2015-05-14 | 2017-03-14 | Sandisk Technologies Llc | Floating gate separation in NAND flash memory |
US10446407B2 (en) | 2017-01-18 | 2019-10-15 | Tokyo Electron Limited | Method of preferential silicon nitride etching using sulfur hexafluoride |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6423574A (en) * | 1987-07-20 | 1989-01-26 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
JPH0590603A (ja) * | 1991-09-26 | 1993-04-09 | Nippon Steel Corp | 不揮発性半導体メモリの製造方法 |
JPH10284489A (ja) * | 1997-04-11 | 1998-10-23 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002280388A (ja) * | 2001-03-15 | 2002-09-27 | Toshiba Corp | 半導体装置の製造方法 |
JP2004152784A (ja) * | 2002-10-28 | 2004-05-27 | Fujitsu Ltd | 微細パターンの作製方法及び半導体装置の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5795830A (en) | 1995-06-06 | 1998-08-18 | International Business Machines Corporation | Reducing pitch with continuously adjustable line and space dimensions |
US6063688A (en) | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
KR100354440B1 (ko) | 2000-12-04 | 2002-09-28 | 삼성전자 주식회사 | 반도체 장치의 패턴 형성 방법 |
JP3406302B2 (ja) | 2001-01-16 | 2003-05-12 | 株式会社半導体先端テクノロジーズ | 微細パターンの形成方法、半導体装置の製造方法および半導体装置 |
US6638441B2 (en) | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
US6924191B2 (en) * | 2002-06-20 | 2005-08-02 | Applied Materials, Inc. | Method for fabricating a gate structure of a field effect transistor |
TWI316282B (en) * | 2003-07-23 | 2009-10-21 | Nanya Technology Corp | A method of fabricating a trench isolation with high aspect ratio |
JP4921723B2 (ja) | 2005-04-18 | 2012-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
-
2005
- 2005-03-16 JP JP2005075143A patent/JP4619839B2/ja active Active
-
2006
- 2006-03-13 US US11/373,335 patent/US7312158B2/en active Active
- 2006-03-15 KR KR1020060023863A patent/KR100759616B1/ko active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6423574A (en) * | 1987-07-20 | 1989-01-26 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
JPH0590603A (ja) * | 1991-09-26 | 1993-04-09 | Nippon Steel Corp | 不揮発性半導体メモリの製造方法 |
JPH10284489A (ja) * | 1997-04-11 | 1998-10-23 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002280388A (ja) * | 2001-03-15 | 2002-09-27 | Toshiba Corp | 半導体装置の製造方法 |
JP2004152784A (ja) * | 2002-10-28 | 2004-05-27 | Fujitsu Ltd | 微細パターンの作製方法及び半導体装置の製造方法 |
Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006303500A (ja) * | 2005-04-19 | 2006-11-02 | Samsung Electronics Co Ltd | 微細ピッチのハードマスクを用いた半導体素子の微細パターン形成方法 |
US8361904B2 (en) | 2005-04-19 | 2013-01-29 | Samsung Electronics Co., Ltd. | Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same |
US7892982B2 (en) | 2006-03-06 | 2011-02-22 | Samsung Electronics Co., Ltd. | Method for forming fine patterns of a semiconductor device using a double patterning process |
US7998874B2 (en) | 2006-03-06 | 2011-08-16 | Samsung Electronics Co., Ltd. | Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same |
JP2008103718A (ja) * | 2006-10-17 | 2008-05-01 | Samsung Electronics Co Ltd | 半導体素子の微細パターンの形成方法 |
KR100790999B1 (ko) * | 2006-10-17 | 2008-01-03 | 삼성전자주식회사 | 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법 |
KR100752674B1 (ko) | 2006-10-17 | 2007-08-29 | 삼성전자주식회사 | 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법 |
JP2008118130A (ja) * | 2006-10-23 | 2008-05-22 | Samsung Electronics Co Ltd | 微細コンタクトホールを有する半導体素子の製造方法 |
JP2008166700A (ja) * | 2006-12-28 | 2008-07-17 | Hynix Semiconductor Inc | 半導体素子の微細パターン形成方法 |
JP2008193098A (ja) * | 2007-02-06 | 2008-08-21 | Samsung Electronics Co Ltd | ダブルパターニング工程を用いる半導体素子の微細パターン形成方法 |
JP2008198991A (ja) * | 2007-02-15 | 2008-08-28 | Hynix Semiconductor Inc | 半導体素子のコンタクトホール形成方法 |
JP2008205470A (ja) * | 2007-02-16 | 2008-09-04 | Samsung Electronics Co Ltd | 半導体素子の微細金属配線パターンの形成方法 |
US7687369B2 (en) | 2007-02-16 | 2010-03-30 | Samsung Electronics Co., Ltd. | Method of forming fine metal patterns for a semiconductor device using a damascene process |
KR100817089B1 (ko) | 2007-02-28 | 2008-03-26 | 삼성전자주식회사 | 이중 패터닝 기술을 이용한 반도체 소자의 미세 패턴 형성방법 |
JP2008244417A (ja) * | 2007-03-23 | 2008-10-09 | Hynix Semiconductor Inc | 半導体素子の微細パターン形成方法 |
KR100843241B1 (ko) | 2007-03-29 | 2008-07-02 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
KR100850146B1 (ko) | 2007-05-07 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
KR100886219B1 (ko) | 2007-06-07 | 2009-02-27 | 삼성전자주식회사 | 자기정렬된 이중 패터닝을 채택하는 미세 패턴 형성 방법 |
US8071484B2 (en) | 2007-06-07 | 2011-12-06 | Samsung Electronics Co., Ltd. | Method of forming fine pattern employing self-aligned double patterning |
JP2013168687A (ja) * | 2007-06-15 | 2013-08-29 | Samsung Electronics Co Ltd | 半導体素子の製造方法 |
JP2008311623A (ja) * | 2007-06-15 | 2008-12-25 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2009055022A (ja) * | 2007-08-13 | 2009-03-12 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
JP2009076902A (ja) * | 2007-09-18 | 2009-04-09 | Hynix Semiconductor Inc | 半導体素子の微細パターン形成方法 |
JP2009099792A (ja) * | 2007-10-17 | 2009-05-07 | Toshiba Corp | 半導体装置の製造方法 |
US8685627B2 (en) | 2007-12-20 | 2014-04-01 | Hynix Semiconductor Inc. | Method for manufacturing a semiconductor device |
US9218984B2 (en) | 2007-12-20 | 2015-12-22 | SK Hynix Inc. | Method for manufacturing a semiconductor device |
JP2012216846A (ja) * | 2007-12-20 | 2012-11-08 | Sk Hynix Inc | 半導体素子の形成方法 |
KR100942075B1 (ko) | 2007-12-27 | 2010-02-12 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
US8647521B2 (en) | 2007-12-27 | 2014-02-11 | SK Hynix Inc. | Method of forming micro pattern of semiconductor device |
US8008211B2 (en) | 2007-12-28 | 2011-08-30 | Tokyo Electron Limited | Pattern forming method, semiconductor device manufacturing apparatus and storage medium |
JP2009164576A (ja) * | 2008-01-07 | 2009-07-23 | Samsung Electronics Co Ltd | 半導体素子の微細パターンの形成方法 |
JP2010080903A (ja) * | 2008-02-15 | 2010-04-08 | Tokyo Electron Ltd | パターン形成方法、半導体装置の製造方法及び半導体装置の製造装置 |
WO2009101878A1 (ja) * | 2008-02-15 | 2009-08-20 | Tokyo Electron Limited | パターン形成方法、半導体製造装置及び記憶媒体 |
US8283253B2 (en) | 2008-02-15 | 2012-10-09 | Tokyo Electron Limited | Pattern forming method, semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
KR100939168B1 (ko) * | 2008-02-28 | 2010-01-28 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
US8173358B2 (en) | 2008-10-09 | 2012-05-08 | Samsung Electronics Co., Ltd. | Method of forming fine patterns of a semiconductor device |
JP2012511253A (ja) * | 2008-12-04 | 2012-05-17 | マイクロン テクノロジー, インク. | 基板作製方法 |
US8637389B2 (en) | 2008-12-31 | 2014-01-28 | Sandisk 3D Llc | Resist feature and removable spacer pitch doubling patterning method for pillar structures |
JP2012514339A (ja) * | 2008-12-31 | 2012-06-21 | サンディスク スリーディー,エルエルシー | 柱状構造のためのレジストフィーチャおよび除去可能スペーサピッチを倍増するパターニング法 |
US8658526B2 (en) | 2008-12-31 | 2014-02-25 | Sandisk 3D Llc | Methods for increased array feature density |
WO2014123177A1 (ja) * | 2013-02-08 | 2014-08-14 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20060216938A1 (en) | 2006-09-28 |
KR20060100251A (ko) | 2006-09-20 |
KR100759616B1 (ko) | 2007-09-17 |
JP4619839B2 (ja) | 2011-01-26 |
US7312158B2 (en) | 2007-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4619839B2 (ja) | パターン形成方法 | |
US8685859B2 (en) | Self-aligned semiconductor trench structures | |
US8138093B2 (en) | Method for forming trenches having different widths and the same depth | |
KR101004691B1 (ko) | 반도체 소자의 미세패턴 형성방법 | |
US8865595B2 (en) | Device and methods for forming partially self-aligned trenches | |
US20120175745A1 (en) | Methods for fabricating semiconductor devices and semiconductor devices using the same | |
JP2009071306A (ja) | 半導体素子の微細パターン形成方法 | |
TW202109618A (zh) | 圖案化半導體裝置的方法 | |
CN109427554B (zh) | 一种化学溶液和形成半导体器件的方法 | |
JP2008535282A (ja) | フラッシュメモリ装置のポリシリコン−1を規定する方法 | |
KR100726148B1 (ko) | 반도체소자의 제조방법 | |
CN108573865B (zh) | 半导体器件及其形成方法 | |
JP2008218999A (ja) | 半導体装置の製造方法 | |
US6133128A (en) | Method for patterning polysilicon gate layer based on a photodefinable hard mask process | |
KR20100052462A (ko) | 반도체 디바이스 및 그 반도체 디바이스를 포함하는 전자 시스템의 제조 중에 대칭 포토마스크를 사용하여 대칭 또는 비대칭 피쳐들을 선택적으로 형성하는 방법 | |
KR100994714B1 (ko) | 반도체 장치 제조 방법 | |
KR100816210B1 (ko) | 반도체 장치 형성 방법 | |
JP2006032648A (ja) | パターン形成方法を含む半導体装置の製造方法 | |
KR100764452B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
KR100779015B1 (ko) | 반도체 소자의 제조 방법 | |
KR20070106277A (ko) | 피치 감소 방법 | |
TW202403851A (zh) | 基底的處理方法 | |
KR100427718B1 (ko) | 반도체 소자의 제조 방법 | |
KR20110060723A (ko) | 반도체 장치의 패턴 형성 방법 | |
JP2008016852A (ja) | フラッシュメモリ素子の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080115 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100929 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101001 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101027 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131105 Year of fee payment: 3 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4619839 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131105 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |